mirror/rtic
1
0
Fork 0
mirror of https://github.com/rtic-rs/rtic.git synced 2024-12-01 16:04:33 +01:00
Code Issues Projects Releases Packages Wiki Activity
rtic/2/api/rp2040_pac/ppb/index.html

10 lines
25 KiB
HTML
Raw Permalink Normal View History

deploy: f17915842ff18be48b6c8ed5faac378bc26ff3b3
2024-11-27 20:34:22 +01:00
<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="PPB"><title>rp2040_pac::ppb - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module ppb</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#modules">Modules</a></li><li><a href="#structs">Structs</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../index.html">rp2040_pac</a>::<wbr><a class="mod" href="#">ppb</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../src/rp2040_pac/ppb.rs.html#1-477">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>PPB</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="aircr/index.html" title="mod rp2040_pac::ppb::aircr">aircr</a></div><div class="desc docblock-short">Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</div></li><li><div class="item-name"><a class="mod" href="ccr/index.html" title="mod rp2040_pac::ppb::ccr">ccr</a></div><div class="desc docblock-short">The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.</div></li><li><div class="item-name"><a class="mod" href="cpuid/index.html" title="mod rp2040_pac::ppb::cpuid">cpuid</a></div><div class="desc docblock-short">Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</div></li><li><div class="item-name"><a class="mod" href="icsr/index.html" title="mod rp2040_pac::ppb::icsr">icsr</a></div><div class="desc docblock-short">Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</div></li><li><div class="item-name"><a class="mod" href="mpu_ctrl/index.html" title="mod rp2040_pac::ppb::mpu_ctrl">mpu_<wbr>ctrl</a></div><div class="desc docblock-short">Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.</div></li><li><div class="item-name"><a class="mod" href="mpu_rasr/index.html" title="mod rp2040_pac::ppb::mpu_rasr">mpu_<wbr>rasr</a></div><div class="desc docblock-short">Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.</div></li><li><div class="item-name"><a class="mod" href="mpu_rbar/index.html" title="mod rp2040_pac::ppb::mpu_rbar">mpu_<wbr>rbar</a></div><div class="desc docblock-short">Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.</div></li><li><div class="item-name"><a class="mod" href="mpu_rnr/index.html" title="mod rp2040_pac::ppb::mpu_rnr">mpu_rnr</a></div><div class="desc docblock-short">Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.</div></li><li><div class="item-name"><a class="mod" href="mpu_type/index.html" title="mod rp2040_pac::ppb::mpu_type">mpu_<wbr>type</a></div><div class="desc docblock-short">Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.</div></li><li><div class="item-name"><a class="mod" href="nvic_icer/index.html" title="mod rp2040_pac::ppb::nvic_icer">nvic_<wbr>icer</a></div><div class="desc docblock-short">Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.</div></li><li><div class="item-name"><a class="mod" href="nvic_icpr/index.html" title="mod rp2040_pac::ppb::nvic_icpr">nvic_<wbr>icpr</a></div><div class="desc docblock-short">Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr0/index.html" title="mod rp2040_pac::ppb::nvic_ipr0">nvic_<wbr>ipr0</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the hi
Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.<br />
These registers are only word-accessible</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr1/index.html" title="mod rp2040_pac::ppb::nvic_ipr1">nvic_<wbr>ipr1</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr2/index.html" title="mod rp2040_pac::ppb::nvic_ipr2">nvic_<wbr>ipr2</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr3/index.html" title="mod rp2040_pac::ppb::nvic_ipr3">nvic_<wbr>ipr3</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr4/index.html" title="mod rp2040_pac::ppb::nvic_ipr4">nvic_<wbr>ipr4</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr5/index.html" title="mod rp2040_pac::ppb::nvic_ipr5">nvic_<wbr>ipr5</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr6/index.html" title="mod rp2040_pac::ppb::nvic_ipr6">nvic_<wbr>ipr6</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="mod" href="nvic_ipr7/index.html" title="mod rp2040_pac::ppb::nvic_ipr7">nvic_<wbr>ipr7</a></div><div class="desc docblock-short">Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="mod" href="nvic_iser/index.html" title="mod rp2040_pac::ppb::nvic_iser">nvic_<wbr>iser</a></div><div class="desc docblock-short">Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.<br />
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.</div></li><li><div class="item-name"><a class="mod" href="nvic_ispr/index.html" title="mod rp2040_pac::ppb::nvic_ispr">nvic_<wbr>ispr</a></div><div class="desc docblock-short">The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.</div></li><li><div class="item-name"><a class="mod" href="scr/index.html" title="mod rp2040_pac::ppb::scr">scr</a></div><div class="desc docblock-short">System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</div></li><li><div class="item-name"><a class="mod" href="shcsr/index.html" title="mod rp2040_pac::ppb::shcsr">shcsr</a></div><div class="desc docblock-short">Use the System Handler Control and State Register to determine or clear the pending status of SVCall.</div></li><li><div class="item-name"><a class="mod" href="shpr2/index.html" title="mod rp2040_pac::ppb::shpr2">shpr2</a></div><div class="desc docblock-short">System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.</div></li><li><div class="item-name"><a class="mod" href="shpr3/index.html" title="mod rp2040_pac::ppb::shpr3">shpr3</a></div><div class="desc docblock-short">System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.</div></li><li><div class="item-name"><a class="mod" href="syst_calib/index.html" title="mod rp2040_pac::ppb::syst_calib">syst_<wbr>calib</a></div><div class="desc docblock-short">Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</div></li><li><div class="item-name"><a class="mod" href="syst_csr/index.html" title="mod rp2040_pac::ppb::syst_csr">syst_<wbr>csr</a></div><div class="desc docblock-short">Use the SysTick Control and Status Register to enable the SysTick features.</div></li><li><div class="item-name"><a class="mod" href="syst_cvr/index.html" title="mod rp2040_pac::ppb::syst_cvr">syst_<wbr>cvr</a></div><div class="desc docblock-short">Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.</div></li><li><div class="item-name"><a class="mod" href="syst_rvr/index.html" title="mod rp2040_pac::ppb::syst_rvr">syst_<wbr>rvr</a></div><div class="desc docblock-short">Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.<br />
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.</div></li><li><div class="item-name"><a class="mod" href="vtor/index.html" title="mod rp2040_pac::ppb::vtor">vtor</a></div><div class="desc docblock-short">The VTOR holds the vector table offset address.</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::ppb::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.AIRCR.html" title="type rp2040_pac::ppb::AIRCR">AIRCR</a></div><div class="desc docblock-short">AIRCR (rw) register accessor: Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.</div></li><li><div class="item-name"><a class="type" href="type.CCR.html" title="type rp2040_pac::ppb::CCR">CCR</a></div><div class="desc docblock-short">CCR (r) register accessor: The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.</div></li><li><div class="item-name"><a class="type" href="type.CPUID.html" title="type rp2040_pac::ppb::CPUID">CPUID</a></div><div class="desc docblock-short">CPUID (r) register accessor: Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.</div></li><li><div class="item-name"><a class="type" href="type.ICSR.html" title="type rp2040_pac::ppb::ICSR">ICSR</a></div><div class="desc docblock-short">ICSR (rw) register accessor: Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</div></li><li><div class="item-name"><a class="type" href="type.MPU_CTRL.html" title="type rp2040_pac::ppb::MPU_CTRL">MPU_<wbr>CTRL</a></div><div class="desc docblock-short">MPU_CTRL (rw) register accessor: Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.</div></li><li><div class="item-name"><a class="type" href="type.MPU_RASR.html" title="type rp2040_pac::ppb::MPU_RASR">MPU_<wbr>RASR</a></div><div class="desc docblock-short">MPU_RASR (rw) register accessor: Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.</div></li><li><div class="item-name"><a class="type" href="type.MPU_RBAR.html" title="type rp2040_pac::ppb::MPU_RBAR">MPU_<wbr>RBAR</a></div><div class="desc docblock-short">MPU_RBAR (rw) register accessor: Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.</div></li><li><div class="item-name"><a class="type" href="type.MPU_RNR.html" title="type rp2040_pac::ppb::MPU_RNR">MPU_RNR</a></div><div class="desc docblock-short">MPU_RNR (rw) register accessor: Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.</div></li><li><div class="item-name"><a class="type" href="type.MPU_TYPE.html" title="type rp2040_pac::ppb::MPU_TYPE">MPU_<wbr>TYPE</a></div><div class="desc docblock-short">MPU_TYPE (r) regist
Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.<br />
These registers are only word-accessible</div></li><li><div class="item-name"><a class="type" href="type.NVIC_IPR1.html" title="type rp2040_pac::ppb::NVIC_IPR1">NVIC_<wbr>IPR1</a></div><div class="desc docblock-short">NVIC_IPR1 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_IPR2.html" title="type rp2040_pac::ppb::NVIC_IPR2">NVIC_<wbr>IPR2</a></div><div class="desc docblock-short">NVIC_IPR2 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_IPR3.html" title="type rp2040_pac::ppb::NVIC_IPR3">NVIC_<wbr>IPR3</a></div><div class="desc docblock-short">NVIC_IPR3 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_IPR4.html" title="type rp2040_pac::ppb::NVIC_IPR4">NVIC_<wbr>IPR4</a></div><div class="desc docblock-short">NVIC_IPR4 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_IPR5.html" title="type rp2040_pac::ppb::NVIC_IPR5">NVIC_<wbr>IPR5</a></div><div class="desc docblock-short">NVIC_IPR5 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_IPR6.html" title="type rp2040_pac::ppb::NVIC_IPR6">NVIC_<wbr>IPR6</a></div><div class="desc docblock-short">NVIC_IPR6 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_IPR7.html" title="type rp2040_pac::ppb::NVIC_IPR7">NVIC_<wbr>IPR7</a></div><div class="desc docblock-short">NVIC_IPR7 (rw) register accessor: Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_ISER.html" title="type rp2040_pac::ppb::NVIC_ISER">NVIC_<wbr>ISER</a></div><div class="desc docblock-short">NVIC_ISER (rw) register accessor: Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.<br />
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.</div></li><li><div class="item-name"><a class="type" href="type.NVIC_ISPR.html" title="type rp2040_pac::ppb::NVIC_ISPR">NVIC_<wbr>ISPR</a></div><div class="desc docblock-short">NVIC_ISPR (rw) register accessor: The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.</div></li><li><div class="item-name"><a class="type" href="type.SCR.html" title="type rp2040_pac::ppb::SCR">SCR</a></div><div class="desc docblock-short">SCR (rw) register accessor: System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.</div></li><li><div class="item-name"><a class="type" href="type.SHCSR.html" title="type rp2040_pac::ppb::SHCSR">SHCSR</a></div><div class="desc docblock-short">SHCSR (rw) register accessor: Use the System Handler Control and State Register to determine or clear the pending status of SVCall.</div></li><li><div class="item-name"><a class="type" href="type.SHPR2.html" title="type rp2040_pac::ppb::SHPR2">SHPR2</a></div><div class="desc docblock-short">SHPR2 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.</div></li><li><div class="item-name"><a class="type" href="type.SHPR3.html" title="type rp2040_pac::ppb::SHPR3">SHPR3</a></div><div class="desc docblock-short">SHPR3 (rw) register accessor: System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.</div></li><li><div class="item-name"><a class="type" href="type.SYST_CALIB.html" title="type rp2040_pac::ppb::SYST_CALIB">SYST_<wbr>CALIB</a></div><div class="desc docblock-short">SYST_CALIB (r) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.</div></li><li><div class="item-name"><a class="type" href="type.SYST_CSR.html" title="type rp2040_pac::ppb::SYST_CSR">SYST_<wbr>CSR</a></div><div class="desc docblock-short">SYST_CSR (rw) register accessor: Use the SysTick Control and Status Register to enable the SysTick features.</div></li><li><div class="item-name"><a class="type" href="type.SYST_CVR.html" title="type rp2040_pac::ppb::SYST_CVR">SYST_<wbr>CVR</a></div><div class="desc docblock-short">SYST_CVR (rw) register accessor: Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.</div></li><li><div class="item-name"><a class="type" href="type.SYST_RVR.html" title="type rp2040_pac::ppb::SYST_RVR">SYST_<wbr>RVR</a></div><div class="desc docblock-short">SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.<br />
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.</div></li><li><div class="item-name"><a class="type" href="type.VTOR.html" title="type rp2040_pac::ppb::VTOR">VTOR</a></div><div class="desc docblock-short">VTOR (rw) register accessor: The VTOR holds the vector table offset address.</div></li></ul></section></div></main></body></html>
Reference in a new issue Copy permalink