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1 line
131 KiB
JavaScript
1 line
131 KiB
JavaScript
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searchState.loadedDescShard("rp2040_pac", 1, "61: Select Timer 2 as TREQ (Optional)\n62: Select Timer 3 as TREQ (Optional)\nSelect a Transfer Request signal. The channel uses the …\nField <code>TREQ_SEL</code> reader - Select a Transfer Request signal. …\nField <code>TREQ_SEL</code> writer - Select a Transfer Request signal. …\n21: Select UART0’s RX FIFO as TREQ\n20: Select UART0’s TX FIFO as TREQ\n23: Select UART1’s RX FIFO as TREQ\n22: Select UART1’s TX FIFO as TREQ\nRegister <code>CH_AL3_CTRL</code> writer\nField <code>WRITE_ERROR</code> reader - If 1, the channel received a …\nField <code>WRITE_ERROR</code> writer - If 1, the channel received a …\n39: Select the XIP SSI RX FIFO as TREQ\n38: Select the XIP SSI TX FIFO as TREQ\n37: Select the XIP Streaming FIFO as TREQ\nSelect the ADC as TREQ\nBit 31 - Logical OR of the READ_ERROR and WRITE_ERROR …\nWrites raw bits to the register.\nBit 22 - Apply byte-swap transformation to DMA data. For …\nBit 22 - Apply byte-swap transformation to DMA data. For …\nBit 24 - This flag goes high when the channel starts a new …\nBits 11:14 - When this channel completes, it will trigger …\nBits 11:14 - When this channel completes, it will trigger …\nBits 2:3 - Set the size of each bus transfer …\nBits 2:3 - Set the size of each bus transfer …\nBit 0 - DMA Channel Enable. When 1, the channel will …\nBit 0 - DMA Channel Enable. When 1, the channel will …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 1 - HIGH_PRIORITY gives a channel preferential …\nBit 1 - HIGH_PRIORITY gives a channel preferential …\nSelect I2C0’s RX FIFO as TREQ\nSelect I2C0’s TX FIFO as TREQ\nSelect I2C1’s RX FIFO as TREQ\nSelect I2C1’s TX FIFO as TREQ\nBit 4 - If 1, the read address increments with each …\nBit 4 - If 1, the read address increments with each …\nBit 5 - If 1, the write address increments with each …\nBit 5 - If 1, the write address increments with each …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nBit 21 - In QUIET mode, the channel does not generate IRQs …\nBit 21 - In QUIET mode, the channel does not generate IRQs …\nSelect the ADC as TREQ\nSelect I2C0’s RX FIFO as TREQ\nSelect I2C0’s TX FIFO as TREQ\nSelect I2C1’s RX FIFO as TREQ\nSelect I2C1’s TX FIFO as TREQ\nPermanent request, for unpaced transfers.\nSelect PIO0’s RX FIFO 0 as TREQ\nSelect PIO0’s RX FIFO 1 as TREQ\nSelect PIO0’s RX FIFO 2 as TREQ\nSelect PIO0’s RX FIFO 3 as TREQ\nSelect PIO0’s TX FIFO 0 as TREQ\nSelect PIO0’s TX FIFO 1 as TREQ\nSelect PIO0’s TX FIFO 2 as TREQ\nSelect PIO0’s TX FIFO 3 as TREQ\nSelect PIO1’s RX FIFO 0 as TREQ\nSelect PIO1’s RX FIFO 1 as TREQ\nSelect PIO1’s RX FIFO 2 as TREQ\nSelect PIO1’s RX FIFO 3 as TREQ\nSelect PIO1’s TX FIFO 0 as TREQ\nSelect PIO1’s TX FIFO 1 as TREQ\nSelect PIO1’s TX FIFO 2 as TREQ\nSelect PIO1’s TX FIFO 3 as TREQ\nSelect PWM Counter 0’s Wrap Value as TREQ\nSelect PWM Counter 1’s Wrap Value as TREQ\nSelect PWM Counter 2’s Wrap Value as TREQ\nSelect PWM Counter 3’s Wrap Value as TREQ\nSelect PWM Counter 4’s Wrap Value as TREQ\nSelect PWM Counter 5’s Wrap Value as TREQ\nSelect PWM Counter 6’s Wrap Value as TREQ\nSelect PWM Counter 7’s Wrap Value as TREQ\n<code>0</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nSelect SPI0’s RX FIFO as TREQ\nSelect SPI0’s TX FIFO as TREQ\nSelect SPI1’s RX FIFO as TREQ\nSelect SPI1’s TX FIFO as TREQ\nSelect Timer 0 as TREQ\nSelect Timer 1 as TREQ\nSelect Timer 2 as TREQ (Optional)\nSelect Timer 3 as TREQ (Optional)\nSelect UART0’s RX FIFO as TREQ\nSelect UART0’s TX FIFO as TREQ\nSelect UART1’s RX FIFO as TREQ\nSelect UART1’s TX FIFO as TREQ\nSelect the XIP SSI RX FIFO as TREQ\nSelect the XIP SSI TX FIFO as TREQ\nSelect the XIP Streaming FIFO as TREQ\nPermanent request, for unpaced transfers.\nSelect PIO0’s RX FIFO 0 as TREQ\nSelect PIO0’
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