rtic/stable/api/search.desc/rp2040_pac/rp2040_pac-desc-3-.js

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searchState.loadedDescShard("rp2040_pac", 3, "For a detailed description see freqa register\n0x08 - For a detailed description see freqa register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nControls the phase shifted output\n0x14 - Controls the phase shifted output\nThis just reads the state of the oscillator output so \n0x1c - This just reads the state of the oscillator output \nRing Oscillator Status\n0x18 - Ring Oscillator Status\nRing Oscillator control\n3358: <code>110100011110</code>\n4011: <code>111110101011</code>\nOn power-up this field is initialised to ENABLE The system \nField <code>ENABLE</code> reader - On power-up this field is \nField <code>ENABLE</code> writer - On power-up this field is \nControls the number of delay stages in the ROSC ring LOW \nField <code>FREQ_RANGE</code> reader - Controls the number of delay \nField <code>FREQ_RANGE</code> writer - Controls the number of delay \n4007: <code>111110100111</code>\n4004: <code>111110100100</code>\n4005: <code>111110100101</code>\nRegister <code>CTRL</code> reader\n4006: <code>111110100110</code>\nRegister <code>CTRL</code> writer\nWrites raw bits to the register.\n<code>110100011110</code>\nBits 12:23 - On power-up this field is initialised to \nBits 12:23 - On power-up this field is initialised to \n<code>111110101011</code>\nBits 0:11 - Controls the number of delay stages in the \nBits 0:11 - Controls the number of delay stages in the \nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\n<code>111110100111</code>\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>110100011110</code>\n<code>111110101011</code>\n<code>111110100111</code>\n<code>111110100100</code>\n<code>111110100101</code>\n<code>111110100110</code>\n<code>111110100100</code>\n<code>111110100101</code>\n<code>111110100110</code>\nGet enumerated values variant\nGet enumerated values variant\nset to 0xaa0 + div where div = 0 divides by 32 div = 1-31 \nField <code>DIV</code> reader - set to 0xaa0 + div where div = 0 \nControls the output divider\nField <code>DIV</code> writer - set to 0xaa0 + div where div = 0 \n2720: <code>101010100000</code>\nRegister <code>DIV</code> reader\nRegister <code>DIV</code> writer\nWrites raw bits to the register.\nBits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 \nBits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 \nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>101010100000</code>\n<code>101010100000</code>\nGet enumerated values variant\nRing Oscillator pause control This is used to save power \nRegister <code>DORMANT</code> reader\nRegister <code>DORMANT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DS0</code> reader - Stage 0 drive strength\nField <code>DS0</code> writer - Stage 0 drive strength\nField <code>DS1</code> reader - Stage 1 drive strength\nField <code>DS1</code> writer - Stage 1 drive strength\nField <code>DS2</code> reader - Stage 2 drive strength\nField <code>DS2</code> writer - Stage 2 drive strength\nField <code>DS3</code> reader - Stage 3 drive strength\nField <code>DS3</code> writer - Stage 3 drive strength\nThe FREQA &amp; FREQB registers control the frequency by \n38550: <code>1001011010010110</code>\nSet to 0x9696 to apply the settings Any other value in \nField <code>PASSWD</code> reader - Set to 0x9696 to apply the settings \nField <code>PASSWD</code> writer - Set to 0x9696 to apply the settings \nRegister <code>FREQA</code> reader\nRegister <code>FREQA</code> writer\nWrites raw bits to the register.\nBits 0:2 - Stage 0 drive strength\nBits 0:2 - Stage 0 drive strength\nBits 4:6 - Stage 1 drive strength\nBits 4:6 - Stage 1 drive strength\nBits 8:10 - Stage 2 drive strength\nBits 8:10 - Stage 2 drive strength\nBits 12:14 - Stage 3 drive streng