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1 line
90 KiB
JavaScript
1 line
90 KiB
JavaScript
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searchState.loadedDescShard("stm32_metapac", 2, "USB_OTG_HS peripheral clock enable during CSleep mode\nUSB_OTG_HS peripheral clock enable during CSleep mode\nUSB_OTG_HS block reset\nUSBOTG 1 and 2 kernel clock source selection\nVREF Autonomous mode enable\nVREF peripheral clock enable\nVREF peripheral clock enable\nVREF peripheral clock enable during CSleep mode\nVREF peripheral clock enable during CSleep mode\nVREF block reset\nWWDG1 reset scope control\nWWDG2 reset scope control\nWWDG1 Clock Enable\nWWDG1 Clock Enable\nWWDG1 Clock Enable During CSleep Mode\nWWDG1 Clock Enable During CSleep Mode\nWindow Watchdog reset flag\nWindow Watchdog reset flag\nWWDG2 peripheral clock enable\nWWDG2 peripheral clock enable\nWWDG2 peripheral Clocks Enable During CSleep Mode\nWWDG2 peripheral Clocks Enable During CSleep Mode\nAPB clock selected as peripheral clock\ncsi_ker selected as peripheral clock\nCSI selected as peripheral clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\nCSI selected for micro-controller clock output\nCSI selected as PLL clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\nCSI selected as wake up clock from system Stop\nCSI selected as system clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\nThe HRTIM prescaler clock source is the CPU clock (c_ck)\nTimer kernel clock equal to 2x pclk by default\nTimer kernel clock equal to 4x pclk by default\nNo clock sent to DIVMx dividers and PLLs\nNo clock\nDisable the kernel clock\nsys_ck not divided\nNo division\nDivide by 1\nrcc_hclk not divided\nDivide by 10\nDivide by 11\nDivide by 12\nsys_ck divided by 128\nDivide by 13\nDivide by 14\nDivide by 15\nsys_ck divided by 16\nrcc_hclk divided by 16\nsys_ck divided by 2\nDivision by 2\nDivide by 2\nrcc_hclk divided by 2\nsys_ck divided by 256\nDivide by 3\nsys_ck divided by 4\nDivision by 4\nDivide by 4\nrcc_hclk divided by 4\nDivide by 5\nsys_ck divided by 512\nDivide by 6\nsys_ck divided by 64\nDivide by 7\nsys_ck divided by 8\nDivision by 8\nDivide by 8\nrcc_hclk divided by 8\nDivide by 9\nAHB3 selected as peripheral clock\nHigh driving capability\nHSE selected as peripheral clock\nHSE selected as peripheral clock\nHSE selected for micro-controller clock output\nHSE selected for micro-controller clock output\nHSE selected as PLL clock\nHSE oscillator clock divided by a prescaler used as RTC …\nHSE selected as peripheral clock\nHSE selected as peripheral clock\nHSE selected as system clock\nHSI selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nHSI selected for micro-controller clock output\nHSI selected as PLL clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nHSI selected as wake up clock from system Stop\nHSI selected as system clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nHSI48 selected for micro-controller clock output\nHSI48 selected as peripheral clock\nHSI48 selected as peripheral clock\ni2s_ckin selected as peripheral clock\nI2S_CKIN selected as peripheral clock\nLow driving capability\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSE selected for micro-controller clock output\nLSE selected as peripheral clock\nLSE oscillator clock used as RTC clock\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSI selected as peripheral clock\nLSI selected as peripheral clock\nLSI selected as peripheral clock\nLSI selected for micro-controller clock output\nLSI selected as peripheral clock\nLSI oscillator clock used as RTC clock\nMedium high driving capability\nMedium low driving capability\nVCO frequency range 150 to 420 MHz\npclk selected as peripheral clock\nrcc_pclk1 selected as peripheral clock\nrcc_pclk1 selected as peripheral clock\nrcc_pclk1
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