mirror of
https://github.com/rtic-rs/rtic.git
synced 2024-11-29 23:14:34 +01:00
1 line
132 KiB
JavaScript
1 line
132 KiB
JavaScript
|
searchState.loadedDescShard("imxrt_ral", 2, "Returns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nARM CM7 platform AHB clock enable\nExclusive monitor response select of illegal command\nGlobal Interrupt\nSAI1 MCLK1 source select\nSAI1 MCLK2 source select\nSAI1 MCLK3 source select\nsai1.MCLK signal direction control\nSAI3 MCLK3 source select\nsai3.MCLK signal direction control\nARM invasive debug enable\nDCP Key selection bit.\nLock DBG_EN field for changes\nLock DCP Key OCOTP/Key MUX selection bit\nLock NIDEN field for changes\nLock OCRAM_TZ_ADDR field for changes\nLock OCRAM_TZ_EN field for changes\nLock SEC_ERR_RESP field for changes\nARM non-secure (non-invasive) debug enable\nOCRAM TrustZone (TZ) start address\nOCRAM TrustZone (TZ) enable.\nSecurity error response enable for all security gaskets …\nDebug turned off.\nDebug enabled (default).\nSelect key from SNVS Master Key.\nSelect key from OCOTP (SW_GP2).\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nDebug turned off.\nDebug enabled (default).\nThe TrustZone feature is disabled. Entire OCRAM space is …\nThe TrustZone feature is enabled. Access to address in the …\nOKEY response\nSLVError (default)\nLock M7_APC_AC_R0_CTRL field for changes\nLock M7_APC_AC_R1_CTRL field for changes\nLock M7_APC_AC_R2_CTRL field for changes\nLock M7_APC_AC_R3_CTRL field for changes\nAccess control of memory region-0\nAccess control of memory region-1\nAccess control of memory region-2\nAccess control of memory region-3\nNo access protection\nM7 debug protection enabled\nNo access protection\nM7 debug protection enabled\nNo access protection\nM7 debug protection enabled\nNo access protection\nM7 debug protection enabled\nFLEXIO1 ipg_doze mode\nFlexIO1 stop mode selection. Cannot change when ipg_stop …\nFLEXIO1 is not in doze mode\nFLEXIO1 is in doze mode\nFlexIO1 is functional in Stop mode.\nWhen this bit is equal to 1’b1 and ipg_stop is asserted, …\nUSB block cacheable attribute value of AXI transactions\nCacheable attribute is off for read/write transactions.\nCacheable attribute is on for read/write transactions.\nDTCM total size configuration\nITCM total size configuration\n0 KB (No DTCM)\n4 KB\n8 KB\n16 KB\n32 KB\n64 KB\n128 KB\n0 KB (No ITCM)\n4 KB\n8 KB\n16 KB\n32 KB\n64 KB\n128 KB\nVector table offset register out of reset\nFlexRAM bank config source select\nDTCM enable initialization out of reset\nITCM enable initialization out of reset\nLock CM7_INIT_VTOR field for changes\nuse fuse value to config\nuse FLEXRAM_BANK_CFG to config\nDTCM is disabled\nDTCM is enabled\nITCM is disabled\nITCM is enabled\nCM7_INIT_VTOR field is not locked.\nCM7_INIT_VTOR field is locked (read access only).\nFlexRAM bank config value\nlock M7_APC_AC_R0_BOT field for changes\nAPC end address of memory region-0\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nlock M7_APC_AC_R0_TOP field for changes\nAPC start address of memory region-0\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nAHB clock is not running (gated) when CM7 is sleeping and …\nAHB clock is running (enabled) when CM7 is sleeping and …\nOKAY response\nSLVError response\nGlobal interrupt request is not asserted.\nGlobal interrupt request is asserted.\nccm.ssi1_clk_root\nccm.ssi3_clk_root\niomux.sai1_ipg_clk_sai_mclk\niomux.sai3_ipg_clk_sai_mclk\nccm.ssi1_clk_root\nccm.ssi3_clk_root\niomux.sai1_ipg_clk_sai_mclk\niomux.sai3_ipg_clk_sai_mclk\nccm.spdif0_clk_root\nSPDIF_EXT_CLK\nspdif.spdif_srclk\nspdif.spdif_outclock\nsai1.MCLK is input signal\nsai1.MCLK is output signal\nccm.spdif0_clk_root\nSPDIF_EXT_CLK\nspdif.spdi
|