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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="DMA with separate read and write masters"><title>rp2040_pac::dma - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module dma</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#reexports">Re-exports</a></li><li><a href="#modules">Modules</a></li><li><a href="#structs">Structs</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../index.html">rp2040_pac</a>::<wbr><a class="mod" href="#">dma</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../src/rp2040_pac/dma.rs.html#1-668">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>DMA with separate read and write masters</p>
</div></details><h2 id="reexports" class="section-header">Re-exports<a href="#reexports" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name" id="reexport.CH"><code>pub use self::ch::<a class="struct" href="ch/struct.CH.html" title="struct rp2040_pac::dma::ch::CH">CH</a>;</code></div></li></ul><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="ch/index.html" title="mod rp2040_pac::dma::ch">ch</a></div><div class="desc docblock-short">Cluster
Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG</div></li><li><div class="item-name"><a class="mod" href="ch0_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch0_dbg_ctdreq">ch0_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch0_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch0_dbg_tcr">ch0_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch1_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch1_dbg_ctdreq">ch1_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch1_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch1_dbg_tcr">ch1_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch2_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch2_dbg_ctdreq">ch2_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch2_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch2_dbg_tcr">ch2_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch3_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch3_dbg_ctdreq">ch3_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch3_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch3_dbg_tcr">ch3_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch4_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch4_dbg_ctdreq">ch4_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch4_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch4_dbg_tcr">ch4_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod"
Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</div></li><li><div class="item-name"><a class="mod" href="timer0/index.html" title="mod rp2040_pac::dma::timer0">timer0</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="mod" href="timer1/index.html" title="mod rp2040_pac::dma::timer1">timer1</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="mod" href="timer2/index.html" title="mod rp2040_pac::dma::timer2">timer2</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="mod" href="timer3/index.html" title="mod rp2040_pac::dma::timer3">timer3</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::dma::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.CH0_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH0_DBG_CTDREQ">CH0_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH0_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH0_DBG_TCR.html" title="type rp2040_pac::dma::CH0_DBG_TCR">CH0_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH0_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH1_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH1_DBG_CTDREQ">CH1_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH1_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH1_DBG_TCR.html" title="type rp2040_pac::dma::CH1_DBG_TCR">CH1_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH1_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH2_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH2_DBG_CTDREQ">CH2_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH2_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH2_DBG_TCR.html" title="type rp2040_pac::dma::CH2_DBG_TCR">CH2_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH2_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH3_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH3_DBG_CTDREQ">CH3_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH3_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH3_DBG_TCR.html" title="type rp2040_pac::dma::CH3_DBG_TCR">CH3_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH3_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH4_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH4_DBG_CTDREQ">CH4_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH4_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any valu
Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</div></li><li><div class="item-name"><a class="type" href="type.TIMER0.html" title="type rp2040_pac::dma::TIMER0">TIMER0</a></div><div class="desc docblock-short">TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="type" href="type.TIMER1.html" title="type rp2040_pac::dma::TIMER1">TIMER1</a></div><div class="desc docblock-short">TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="type" href="type.TIMER2.html" title="type rp2040_pac::dma::TIMER2">TIMER2</a></div><div class="desc docblock-short">TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="type" href="type.TIMER3.html" title="type rp2040_pac::dma::TIMER3">TIMER3</a></div><div class="desc docblock-short">TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li></ul></section></div></main></body></html>
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