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<h1 class="menu-title">Real-Time Interrupt-driven Concurrency</h1>
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<h1 id="target-architecture"><a class="header" href="#target-architecture">Target Architecture</a></h1>
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<p>While RTIC can currently target all Cortex-m devices there are some key architecture differences that
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users should be aware of. Namely, the absence of Base Priority Mask Register (<code>BASEPRI</code>) which lends
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itself exceptionally well to the hardware priority ceiling support used in RTIC, in the ARMv6-M and
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ARMv8-M-base architectures, which forces RTIC to use source masking instead. For each implementation
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of lock and a detailed commentary of pros and cons, see the implementation of
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<a href="https://github.com/rtic-rs/rtic/blob/master/src/export.rs">lock in src/export.rs</a>.</p>
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<p>These differences influence how critical sections are realized, but functionality should be the same
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except that ARMv6-M/ARMv8-M-base cannot have tasks with shared resources bound to exception
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handlers, as these cannot be masked in hardware.</p>
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<p>Table 1 below shows a list of Cortex-m processors and which type of critical section they employ.</p>
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<h4 id="table-1-critical-section-implementation-by-processor-architecture"><a class="header" href="#table-1-critical-section-implementation-by-processor-architecture"><em>Table 1: Critical Section Implementation by Processor Architecture</em></a></h4>
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<div class="table-wrapper"><table><thead><tr><th style="text-align: left">Processor</th><th style="text-align: center">Architecture</th><th style="text-align: center">Priority Ceiling</th><th style="text-align: center">Source Masking</th></tr></thead><tbody>
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<tr><td style="text-align: left">Cortex-M0</td><td style="text-align: center">ARMv6-M</td><td style="text-align: center"></td><td style="text-align: center">✓</td></tr>
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<tr><td style="text-align: left">Cortex-M0+</td><td style="text-align: center">ARMv6-M</td><td style="text-align: center"></td><td style="text-align: center">✓</td></tr>
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<tr><td style="text-align: left">Cortex-M3</td><td style="text-align: center">ARMv7-M</td><td style="text-align: center">✓</td><td style="text-align: center"></td></tr>
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<tr><td style="text-align: left">Cortex-M4</td><td style="text-align: center">ARMv7-M</td><td style="text-align: center">✓</td><td style="text-align: center"></td></tr>
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<tr><td style="text-align: left">Cortex-M7</td><td style="text-align: center">ARMv7-M</td><td style="text-align: center">✓</td><td style="text-align: center"></td></tr>
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<tr><td style="text-align: left">Cortex-M23</td><td style="text-align: center">ARMv8-M-base</td><td style="text-align: center"></td><td style="text-align: center">✓</td></tr>
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<tr><td style="text-align: left">Cortex-M33</td><td style="text-align: center">ARMv8-M-main</td><td style="text-align: center">✓</td><td style="text-align: center"></td></tr>
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</tbody></table>
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</div>
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<h2 id="priority-ceiling"><a class="header" href="#priority-ceiling">Priority Ceiling</a></h2>
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<p>This is covered by the <a href="../by-example/resources.html">Resources</a> page of this book.</p>
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<h2 id="source-masking"><a class="header" href="#source-masking">Source Masking</a></h2>
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<p>Without a <code>BASEPRI</code> register which allows for directly setting a priority ceiling in the Nested
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Vectored Interrupt Controller (NVIC), RTIC must instead rely on disabling (masking) interrupts.
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Consider Figure 1 below, showing two tasks A and B where A has higher priority but shares a resource
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with B.</p>
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<h4 id="figure-1-shared-resources-and-source-masking"><a class="header" href="#figure-1-shared-resources-and-source-masking"><em>Figure 1: Shared Resources and Source Masking</em></a></h4>
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<pre><code class="language-text"> ┌────────────────────────────────────────────────────────────────┐
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│ │
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│ │
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3 │ Pending Preempts │
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2 │ ↑- - -A- - - - -↓A─────────► │
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1 │ B───────────────────► - - - - B────────► │
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0 │Idle┌─────► Resumes ┌────────► │
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├────┴────────────────────────────────────────────┴──────────────┤
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│ │
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└────────────────────────────────────────────────────────────────┴──► Time
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t1 t2 t3 t4
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</code></pre>
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<p>At time <em>t1</em>, task B locks the shared resource by selectively disabling (using the NVIC) all other
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tasks which have a priority equal to or less than any task which shares resources with B. In effect
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this creates a virtual priority ceiling, mirroring the <code>BASEPRI</code> approach. Task A is one such task that shares resources with
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task B. At time <em>t2</em>, task A is either spawned by task B or becomes pending through an interrupt
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condition, but does not yet preempt task B even though its priority is greater. This is because the
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NVIC is preventing it from starting due to task A being disabled. At time <em>t3</em>, task B
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releases the lock by re-enabling the tasks in the NVIC. Because task A was pending and has a higher
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priority than task B, it immediately preempts task B and is free to use the shared resource without
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risk of data race conditions. At time <em>t4</em>, task A completes and returns the execution context to B.</p>
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<p>Since source masking relies on use of the NVIC, core exception sources such as HardFault, SVCall,
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PendSV, and SysTick cannot share data with other tasks.</p>
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