mirror/rtic
1
0
Fork 0
mirror of https://github.com/rtic-rs/rtic.git synced 2024-11-25 21:19:35 +01:00
Code Issues Projects Releases Packages Wiki Activity

Expand lock explanation

Browse source 
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
This commit is contained in:
n8tlarsen 2022-12-19 17:48:52 -06:00 committed by GitHub
parent c8d60d2910
commit 60132495d9
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 7 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
book/en/src/internals/targets.md
View file

@ -2,10 +2,13 @@
While RTIC can currently target all Cortex-m devices there are some key architecure differences that
users should be aware of. Namely the absence of Base Priority Mask Register (`BASEPRI`) which lends itself exceptionally well to the hardware priority ceiling support used in RTIC, in the
ARMv6-M and ARMv8-M-base architectures requires a few tweaks from RTIC to deliver the same
features. These differences result in two flavors of critical sections: priority ceiling, and source
masking. Table 1 below shows a list of Cortex-m processors and which type of critical section they
employ.
ARMv6-M and ARMv8-M-base architectures, which forces RTIC to use source masking instead. For each implementation of lock and a detailed commentary of pros and cons, see the implementation of [lock in src/export.rs][src_export].
[src_export]: https://github.com/rtic-rs/cortex-m-rtic/blob/master/src/export.rs
These differences influence how critical sections are realized, but functionality should be the same except that ARMv6-M/ARMv8-M-base cannot have tasks with shared resources bound to exception handlers, as these cannot be masked in hardware.
Table 1 below shows a list of Cortex-m processors and which type of critical section they employ.
#### *Table 1: Critical Section Implementation by Processor Architecture*