Added esp32c6 support and example

This commit is contained in:
Wouter Geraedts 2024-04-09 15:01:27 +02:00
parent 56a3b9e5c8
commit 69dcb051e0
17 changed files with 1524 additions and 2 deletions

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[target.riscv32imac-unknown-none-elf]
runner = "espflash flash --monitor"
[build]
rustflags = [
"-C", "link-arg=-Tlinkall.x",
# Required to obtain backtraces (e.g. when using the "esp-backtrace" crate.)
# NOTE: May negatively impact performance of produced code
"-C", "force-frame-pointers",
]
target = "riscv32imac-unknown-none-elf"
[unstable]
build-std = ["core"]

917
examples/esp32c6/Cargo.lock generated Normal file
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dependencies = [
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"syn 2.0.53",
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View file

@ -0,0 +1,24 @@
[package]
name = "esp32-c6"
version = "0.1.0"
edition = "2021"
license = "MIT OR Apache-2.0"
[workspace]
[dependencies]
rtic = {path = "../../rtic/"}
esp-hal = { version = "0.16.1", features = ["esp32c6", "direct-vectoring", "interrupt-preemption"] }
esp-backtrace = { version = "0.11.0", features = [
"esp32c6",
"panic-handler",
"exception-handler",
"println",
] }
esp32c6 = {version = "0.12.0", features = ["critical-section"]}
esp-println = { version = "0.9.0", default-features=false, features = ["esp32c6", "uart"] }
[features]
test-critical-section = []
riscv-esp32c6-backend = ["rtic/riscv-esp32c6-backend"]

View file

@ -0,0 +1,33 @@
### ESP32-C3 RTIC template
This crate showcases a simple RTIC application for the ESP32-C6.
## Prerequisites
# Nightly Rust
The ESP32-C6 HAL requires a nightly build of Rust.
Following the example of the (Espressif no_std book)[https://docs.esp-rs.org/no_std-training/02_2_software.html], we use this specific build:
```rustup toolchain install nightly-2023-11-14 --component rust-src --target riscv32imac-unknown-none-elf```
# Espressif toolchain
This crate uses the most convenient option in ``cargo-espflash`` and ``espflash``
```cargo install cargo-espflash espflash```
## Running the crate
```cargo run --example sw_and_hw --features=riscv-esp32c6-backend (--release)```
should do the trick.
# Expected behavior
The program
- Prints ``init``
- Enters a high prio task
- During the execution of the high prio task, the button should be non-functional
- Pends a low prio task
- Exits the high prio task
- Enters the low prio task
- During the execution of the low prio task, the button should be functional.
- Exits the low prio task
- Prints ``idle``

View file

@ -0,0 +1,66 @@
#![no_main]
#![no_std]
#[rtic::app(device = esp32c6, dispatchers=[FROM_CPU_INTR0, FROM_CPU_INTR1])]
mod app {
use esp_backtrace as _;
use esp_hal::{
gpio::{Event, Gpio9, Input, PullUp, IO},
peripherals::Peripherals,
prelude::*,
};
use esp_println::println;
#[shared]
struct Shared {}
#[local]
struct Local {
button: Gpio9<Input<PullUp>>,
}
// do nothing in init
#[init]
fn init(_: init::Context) -> (Shared, Local) {
println!("init");
let peripherals = Peripherals::take();
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let mut button = io.pins.gpio9.into_pull_up_input();
button.listen(Event::FallingEdge);
foo::spawn().unwrap();
(Shared {}, Local { button })
}
#[idle()]
fn idle(_: idle::Context) -> ! {
println!("idle");
loop {}
}
#[task(priority = 5)]
async fn foo(_: foo::Context) {
bar::spawn().unwrap(); //enqueue low prio task
println!("Inside high prio task, press button now!");
let mut x = 0;
while x < 5000000 {
x += 1; //burn cycles
esp_hal::riscv::asm::nop();
}
println!("Leaving high prio task.");
}
#[task(priority = 2)]
async fn bar(_: bar::Context) {
println!("Inside low prio task, press button now!");
let mut x = 0;
while x < 5000000 {
x += 1; //burn cycles
esp_hal::riscv::asm::nop();
}
println!("Leaving low prio task.");
}
#[task(binds=GPIO, local=[button], priority = 3)]
fn gpio_handler(cx: gpio_handler::Context) {
cx.local.button.clear_interrupt();
println!("button");
}
}

View file

@ -0,0 +1,4 @@
[toolchain]
channel = "nightly-2023-11-14"
components = ["rust-src"]
targets = ["riscv32imc-unknown-none-elf"]

View file

@ -34,6 +34,7 @@ default = []
cortex-m-source-masking = [] cortex-m-source-masking = []
cortex-m-basepri = [] cortex-m-basepri = []
riscv-esp32c3 = [] riscv-esp32c3 = []
riscv-esp32c6 = []
# riscv-clic = [] # riscv-clic = []
# riscv-ch32 = [] # riscv-ch32 = []
riscv-slic = [] riscv-slic = []

View file

@ -3,6 +3,7 @@
feature = "cortex-m-basepri", feature = "cortex-m-basepri",
feature = "test-template", feature = "test-template",
feature = "riscv-esp32c3", feature = "riscv-esp32c3",
feature = "riscv-esp32c6",
feature = "riscv-slic", feature = "riscv-slic",
)))] )))]
compile_error!("No backend selected"); compile_error!("No backend selected");
@ -25,6 +26,12 @@ pub use esp32c3::*;
#[cfg(feature = "riscv-esp32c3")] #[cfg(feature = "riscv-esp32c3")]
mod esp32c3; mod esp32c3;
#[cfg(feature = "riscv-esp32c6")]
pub use esp32c6::*;
#[cfg(feature = "riscv-esp32c6")]
mod esp32c6;
#[cfg(feature = "riscv-slic")] #[cfg(feature = "riscv-slic")]
pub use riscv_slic::*; pub use riscv_slic::*;

View file

@ -0,0 +1,249 @@
#[cfg(feature = "riscv-esp32c6")]
pub use esp32c6::*;
#[cfg(feature = "riscv-esp32c6")]
mod esp32c6 {
use crate::{
analyze::Analysis as CodegenAnalysis,
codegen::util,
syntax::{analyze::Analysis as SyntaxAnalysis, ast::App},
};
use proc_macro2::{Span, TokenStream as TokenStream2};
use quote::quote;
use std::collections::HashSet;
use syn::{parse, Attribute, Ident};
#[allow(clippy::too_many_arguments)]
pub fn impl_mutex(
_app: &App,
_analysis: &CodegenAnalysis,
cfgs: &[Attribute],
resources_prefix: bool,
name: &Ident,
ty: &TokenStream2,
ceiling: u8,
ptr: &TokenStream2,
) -> TokenStream2 {
let path = if resources_prefix {
quote!(shared_resources::#name)
} else {
quote!(#name)
};
quote!(
#(#cfgs)*
impl<'a> rtic::Mutex for #path<'a> {
type T = #ty;
#[inline(always)]
fn lock<RTIC_INTERNAL_R>(&mut self, f: impl FnOnce(&mut #ty) -> RTIC_INTERNAL_R) -> RTIC_INTERNAL_R {
/// Priority ceiling
const CEILING: u8 = #ceiling;
unsafe {
rtic::export::lock(
#ptr,
CEILING,
f,
)
}
}
}
)
}
pub fn interrupt_ident() -> Ident {
let span = Span::call_site();
Ident::new("Interrupt", span)
}
pub fn interrupt_mod(app: &App) -> TokenStream2 {
let device = &app.args.device;
let interrupt = interrupt_ident();
quote!(#device::#interrupt)
}
pub fn extra_assertions(_: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
vec![]
}
pub fn pre_init_preprocessing(_app: &mut App, _analysis: &SyntaxAnalysis) -> parse::Result<()> {
Ok(())
}
pub fn pre_init_checks(app: &App, _: &SyntaxAnalysis) -> Vec<TokenStream2> {
let mut stmts = vec![];
// check that all dispatchers exists in the `Interrupt` enumeration regardless of whether
// they are used or not
let rt_err = util::rt_err_ident();
for name in app.args.dispatchers.keys() {
stmts.push(quote!(let _ = #rt_err::Interrupt::#name;));
}
stmts
}
pub fn pre_init_enable_interrupts(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
let mut stmts = vec![];
let mut curr_cpu_id: u8 = 1; //cpu interrupt id 0 is reserved
let rt_err = util::rt_err_ident();
let max_prio: usize = 15; //unfortunately this is not part of pac, but we know that max prio is 15.
let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
// Unmask interrupts and set their priorities
for (&priority, name) in interrupt_ids.chain(
app.hardware_tasks
.values()
.filter_map(|task| Some((&task.args.priority, &task.args.binds))),
) {
let es = format!(
"Maximum priority used by interrupt vector '{name}' is more than supported by hardware"
);
// Compile time assert that this priority is supported by the device
stmts.push(quote!(
const _: () = if (#max_prio) <= #priority as usize { ::core::panic!(#es); };
));
stmts.push(quote!(
rtic::export::enable(
#rt_err::Interrupt::#name,
#priority,
#curr_cpu_id,
);
));
curr_cpu_id += 1;
}
stmts
}
pub fn architecture_specific_analysis(
app: &App,
_analysis: &SyntaxAnalysis,
) -> parse::Result<()> {
//check if the dispatchers are supported
for name in app.args.dispatchers.keys() {
let name_s = name.to_string();
match &*name_s {
"FROM_CPU_INTR0" | "FROM_CPU_INTR1" | "FROM_CPU_INTR2" | "FROM_CPU_INTR3" => {}
_ => {
return Err(parse::Error::new(
name.span(),
"Only FROM_CPU_INTRX are supported as dispatchers",
));
}
}
}
// Check that there are enough external interrupts to dispatch the software tasks and the timer
// queue handler
let mut first = None;
let priorities = app
.software_tasks
.iter()
.map(|(name, task)| {
first = Some(name);
task.args.priority
})
.filter(|prio| *prio > 0)
.collect::<HashSet<_>>();
let need = priorities.len();
let given = app.args.dispatchers.len();
if need > given {
let s = {
format!(
"not enough interrupts to dispatch \
all software tasks (need: {need}; given: {given})"
)
};
// If not enough tasks and first still is None, may cause
// "custom attribute panicked" due to unwrap on None
return Err(parse::Error::new(first.unwrap().span(), s));
}
Ok(())
}
pub fn interrupt_entry(_app: &App, _analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
vec![]
}
pub fn interrupt_exit(_app: &App, _analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
vec![]
}
pub fn check_stack_overflow_before_init(
_app: &App,
_analysis: &CodegenAnalysis,
) -> Vec<TokenStream2> {
vec![quote!(
// Check for stack overflow using symbols from `risc-v-rt`.
extern "C" {
pub static _stack_start: u32;
pub static _bss_end: u32;
}
let stack_start = &_stack_start as *const _ as u32;
let ebss = &_bss_end as *const _ as u32;
if stack_start > ebss {
// No flip-link usage, check the SP for overflow.
if rtic::export::read_sp() <= ebss {
panic!("Stack overflow after allocating executors");
}
}
)]
}
pub fn async_entry(
_app: &App,
_analysis: &CodegenAnalysis,
dispatcher_name: Ident,
) -> Vec<TokenStream2> {
let mut stmts = vec![];
stmts.push(quote!(
rtic::export::unpend(rtic::export::Interrupt::#dispatcher_name); //simulate cortex-m behavior by unpending the interrupt on entry.
));
stmts
}
pub fn async_prio_limit(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
let max = if let Some(max) = analysis.max_async_prio {
quote!(#max)
} else {
// No limit
let device = &app.args.device;
quote!(1 << #device::NVIC_PRIO_BITS)
};
vec![quote!(
/// Holds the maximum priority level for use by async HAL drivers.
#[no_mangle]
static RTIC_ASYNC_MAX_LOGICAL_PRIO: u8 = #max;
)]
}
pub fn handler_config(
app: &App,
analysis: &CodegenAnalysis,
dispatcher_name: Ident,
) -> Vec<TokenStream2> {
let mut stmts = vec![];
let mut curr_cpu_id = 1;
//let mut ret = "";
let interrupt_ids = analysis.interrupts.iter().map(|(p, (id, _))| (p, id));
for (_, name) in interrupt_ids.chain(
app.hardware_tasks
.values()
.filter_map(|task| Some((&task.args.priority, &task.args.binds))),
) {
if *name == dispatcher_name {
let ret = &("cpu_int_".to_owned() + &curr_cpu_id.to_string() + "_handler");
stmts.push(quote!(#[export_name = #ret]));
}
curr_cpu_id += 1;
}
stmts
}
pub fn extra_modules(_app: &App, _analysis: &SyntaxAnalysis) -> Vec<TokenStream2> {
vec![]
}
}

View file

@ -15,6 +15,7 @@ macro_rules! with_backend {
feature = "cortex-m-basepri", feature = "cortex-m-basepri",
feature = "test-template", feature = "test-template",
feature = "riscv-esp32c3", feature = "riscv-esp32c3",
feature = "riscv-esp32c6",
feature = "riscv-slic", feature = "riscv-slic",
))] ))]
$($tokens)* $($tokens)*
@ -118,6 +119,7 @@ with_backend! {
feature = "cortex-m-basepri", feature = "cortex-m-basepri",
feature = "test-template", feature = "test-template",
feature = "riscv-esp32c3", feature = "riscv-esp32c3",
feature = "riscv-esp32c6",
feature = "riscv-slic", feature = "riscv-slic",
)))] )))]
compile_error!("Cannot compile. No backend feature selected."); compile_error!("Cannot compile. No backend feature selected.");

View file

@ -3,6 +3,7 @@
feature = "cortex-m-basepri", feature = "cortex-m-basepri",
feature = "test-template", feature = "test-template",
feature = "riscv-esp32c3", feature = "riscv-esp32c3",
feature = "riscv-esp32c6",
feature = "riscv-slic", feature = "riscv-slic",
)))] )))]
compile_error!("No backend selected"); compile_error!("No backend selected");
@ -16,6 +17,9 @@ pub use template::*;
#[cfg(feature = "riscv-esp32c3")] #[cfg(feature = "riscv-esp32c3")]
pub use esp32c3::*; pub use esp32c3::*;
#[cfg(feature = "riscv-esp32c6")]
pub use esp32c6::*;
#[cfg(feature = "riscv-slic")] #[cfg(feature = "riscv-slic")]
pub use riscv_slic::*; pub use riscv_slic::*;
@ -28,5 +32,8 @@ mod template;
#[cfg(feature = "riscv-esp32c3")] #[cfg(feature = "riscv-esp32c3")]
mod esp32c3; mod esp32c3;
#[cfg(feature = "riscv-esp32c6")]
mod esp32c6;
#[cfg(feature = "riscv-slic")] #[cfg(feature = "riscv-slic")]
mod riscv_slic; mod riscv_slic;

View file

@ -0,0 +1,16 @@
use syn::{
parse::{Parse, ParseStream},
Error, Result,
};
#[derive(Debug)]
pub struct BackendArgs();
impl Parse for BackendArgs {
fn parse(input: ParseStream) -> Result<Self> {
Err(Error::new(
input.span(),
"esp32c6 backend does not accept any arguments",
))
}
}

View file

@ -27,6 +27,7 @@ name = "rtic"
[dependencies] [dependencies]
riscv-slic = { git = "https://github.com/romancardenas/riscv-slic.git", rev = "2a91edb", optional = true } riscv-slic = { git = "https://github.com/romancardenas/riscv-slic.git", rev = "2a91edb", optional = true }
esp32c3 = { version = "0.21.0", optional = true } esp32c3 = { version = "0.21.0", optional = true }
esp32c6 = { version = "0.12.0", optional = true }
riscv = { version = "0.11.0", optional = true } riscv = { version = "0.11.0", optional = true }
cortex-m = { version = "0.7.0", optional = true } cortex-m = { version = "0.7.0", optional = true }
bare-metal = "1.0.0" bare-metal = "1.0.0"
@ -62,6 +63,7 @@ thumbv8main-backend = ["cortex-m", "rtic-macros/cortex-m-basepri"]
# riscv-clic-backend = ["rtic-macros/riscv-clic"] # riscv-clic-backend = ["rtic-macros/riscv-clic"]
# riscv-ch32-backend = ["rtic-macros/riscv-ch32"] # riscv-ch32-backend = ["rtic-macros/riscv-ch32"]
riscv-esp32c3-backend = ["esp32c3", "riscv", "rtic-macros/riscv-esp32c3"] riscv-esp32c3-backend = ["esp32c3", "riscv", "rtic-macros/riscv-esp32c3"]
riscv-esp32c6-backend = ["esp32c6", "riscv", "rtic-macros/riscv-esp32c6"]
riscv-clint-backend = [ riscv-clint-backend = [
"riscv", "riscv",
"riscv-slic/clint-backend", "riscv-slic/clint-backend",

View file

@ -27,6 +27,9 @@ fn main() {
"riscv-esp32c3-backend" => { "riscv-esp32c3-backend" => {
println!("cargo:rustc-cfg=feature=\"riscv-esp32c3\""); println!("cargo:rustc-cfg=feature=\"riscv-esp32c3\"");
} }
"riscv-esp32c6-backend" => {
println!("cargo:rustc-cfg=feature=\"riscv-esp32c6\"");
}
"riscv-clint-backend" => { "riscv-clint-backend" => {
println!("cargo:rustc-cfg=feature=\"riscv-slic\""); println!("cargo:rustc-cfg=feature=\"riscv-slic\"");
} }

View file

@ -36,6 +36,11 @@ mod riscv_esp32c3;
#[cfg(feature = "riscv-esp32c3")] #[cfg(feature = "riscv-esp32c3")]
pub use riscv_esp32c3::*; pub use riscv_esp32c3::*;
#[cfg(feature = "riscv-esp32c6")]
mod riscv_esp32c6;
#[cfg(feature = "riscv-esp32c6")]
pub use riscv_esp32c6::*;
#[cfg(feature = "riscv-slic")] #[cfg(feature = "riscv-slic")]
mod slic; mod slic;
#[cfg(feature = "riscv-slic")] #[cfg(feature = "riscv-slic")]

View file

@ -0,0 +1,161 @@
use esp32c6::INTPRI; //priority threshold control
pub use esp32c6::{Interrupt, Peripherals};
pub use riscv::interrupt;
pub use riscv::register::mcause; //low level interrupt enable/disable
#[cfg(all(feature = "riscv-esp32c6", not(feature = "riscv-esp32c6-backend")))]
compile_error!("Building for the esp32c6, but 'riscv-esp32c6-backend not selected'");
#[inline(always)]
pub fn run<F>(priority: u8, f: F)
where
F: FnOnce(),
{
if priority == 1 {
//if priority is 1, priority thresh should be 1
f();
unsafe {
(*INTPRI::ptr())
.cpu_int_thresh()
.write(|w| w.cpu_int_thresh().bits(1));
}
} else {
//read current thresh
let initial = unsafe {
(*INTPRI::ptr())
.cpu_int_thresh()
.read()
.cpu_int_thresh()
.bits()
};
f();
//write back old thresh
unsafe {
(*INTPRI::ptr())
.cpu_int_thresh()
.write(|w| w.cpu_int_thresh().bits(initial));
}
}
}
/// Lock implementation using threshold and global Critical Section (CS)
///
/// # Safety
///
/// The system ceiling is raised from current to ceiling
/// by either
/// - raising the threshold to the ceiling value, or
/// - disable all interrupts in case we want to
/// mask interrupts with maximum priority
///
/// Dereferencing a raw pointer inside CS
///
/// The priority.set/priority.get can safely be outside the CS
/// as being a context local cell (not affected by preemptions).
/// It is merely used in order to omit masking in case current
/// priority is current priority >= ceiling.
#[inline(always)]
pub unsafe fn lock<T, R>(ptr: *mut T, ceiling: u8, f: impl FnOnce(&mut T) -> R) -> R {
if ceiling == (15) {
//turn off interrupts completely, were at max prio
let r = critical_section::with(|_| f(&mut *ptr));
r
} else {
let current = unsafe {
(*INTPRI::ptr())
.cpu_int_thresh()
.read()
.cpu_int_thresh()
.bits()
};
unsafe {
(*INTPRI::ptr())
.cpu_int_thresh()
.write(|w| w.cpu_int_thresh().bits(ceiling + 1))
} //esp32c6 lets interrupts with prio equal to threshold through so we up it by one
let r = f(&mut *ptr);
unsafe {
(*INTPRI::ptr())
.cpu_int_thresh()
.write(|w| w.cpu_int_thresh().bits(current))
}
r
}
}
/// Sets the given software interrupt as pending
#[inline(always)]
pub fn pend(int: Interrupt) {
unsafe {
let peripherals = Peripherals::steal();
match int {
Interrupt::FROM_CPU_INTR0 => peripherals
.INTPRI
.cpu_intr_from_cpu_0()
.write(|w| w.cpu_intr_from_cpu_0().bit(true)),
Interrupt::FROM_CPU_INTR1 => peripherals
.INTPRI
.cpu_intr_from_cpu_1()
.write(|w| w.cpu_intr_from_cpu_1().bit(true)),
Interrupt::FROM_CPU_INTR2 => peripherals
.INTPRI
.cpu_intr_from_cpu_2()
.write(|w| w.cpu_intr_from_cpu_2().bit(true)),
Interrupt::FROM_CPU_INTR3 => peripherals
.INTPRI
.cpu_intr_from_cpu_3()
.write(|w| w.cpu_intr_from_cpu_3().bit(true)),
_ => panic!("Unsupported software interrupt"), //should never happen, checked at compile time
}
}
}
// Sets the given software interrupt as not pending
pub fn unpend(int: Interrupt) {
unsafe {
let peripherals = Peripherals::steal();
match int {
Interrupt::FROM_CPU_INTR0 => peripherals
.INTPRI
.cpu_intr_from_cpu_0()
.write(|w| w.cpu_intr_from_cpu_0().bit(false)),
Interrupt::FROM_CPU_INTR1 => peripherals
.INTPRI
.cpu_intr_from_cpu_1()
.write(|w| w.cpu_intr_from_cpu_1().bit(false)),
Interrupt::FROM_CPU_INTR2 => peripherals
.INTPRI
.cpu_intr_from_cpu_2()
.write(|w| w.cpu_intr_from_cpu_2().bit(false)),
Interrupt::FROM_CPU_INTR3 => peripherals
.INTPRI
.cpu_intr_from_cpu_3()
.write(|w| w.cpu_intr_from_cpu_3().bit(false)),
_ => panic!("Unsupported software interrupt"),
}
}
}
pub fn enable(int: Interrupt, prio: u8, cpu_int_id: u8) {
const INTERRUPT_MAP_BASE: u32 = 0x60010000;
let interrupt_number = int as isize;
let cpu_interrupt_number = cpu_int_id as isize;
unsafe {
let intr_map_base = INTERRUPT_MAP_BASE as *mut u32;
intr_map_base
.offset(interrupt_number)
.write_volatile(cpu_interrupt_number as u32);
//map peripheral interrupt to CPU interrupt
(*INTPRI::ptr())
.cpu_int_enable()
.modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits())); //enable the CPU interupt.
let intr = INTPRI::ptr();
let intr_prio_base = (*intr).cpu_int_pri_0().as_ptr();
intr_prio_base
.offset(cpu_interrupt_number)
.write_volatile(prio as u32);
}
}

View file

@ -154,6 +154,7 @@ pub enum Backends {
Thumbv8Base, Thumbv8Base,
Thumbv8Main, Thumbv8Main,
RiscvEsp32C3, RiscvEsp32C3,
RiscvEsp32C6,
Riscv32ImcClint, // not working yet (issues with portable-atomic features...) Riscv32ImcClint, // not working yet (issues with portable-atomic features...)
Riscv32ImacClint, Riscv32ImacClint,
} }
@ -167,7 +168,7 @@ impl Backends {
Backends::Thumbv8Base => ARMV8MBASE, Backends::Thumbv8Base => ARMV8MBASE,
Backends::Thumbv8Main => ARMV8MMAIN, Backends::Thumbv8Main => ARMV8MMAIN,
Backends::Riscv32ImcClint | Backends::RiscvEsp32C3 => RISCV32IMC, Backends::Riscv32ImcClint | Backends::RiscvEsp32C3 => RISCV32IMC,
Backends::Riscv32ImacClint => RISCV32IMAC, Backends::Riscv32ImacClint | Backends::RiscvEsp32C6 => RISCV32IMAC,
} }
} }
@ -179,6 +180,7 @@ impl Backends {
Backends::Thumbv8Base => "thumbv8base-backend", Backends::Thumbv8Base => "thumbv8base-backend",
Backends::Thumbv8Main => "thumbv8main-backend", Backends::Thumbv8Main => "thumbv8main-backend",
Backends::RiscvEsp32C3 => "riscv-esp32c3-backend", Backends::RiscvEsp32C3 => "riscv-esp32c3-backend",
Backends::RiscvEsp32C6 => "riscv-esp32c6-backend",
Backends::Riscv32ImcClint | Backends::Riscv32ImacClint => "riscv-clint-backend", Backends::Riscv32ImcClint | Backends::Riscv32ImacClint => "riscv-clint-backend",
} }
} }
@ -188,6 +190,7 @@ impl Backends {
Backends::Thumbv6 | Backends::Thumbv8Base => "cortex-m-source-masking", Backends::Thumbv6 | Backends::Thumbv8Base => "cortex-m-source-masking",
Backends::Thumbv7 | Backends::Thumbv8Main => "cortex-m-basepri", Backends::Thumbv7 | Backends::Thumbv8Main => "cortex-m-basepri",
Backends::RiscvEsp32C3 => "riscv-esp32c3", Backends::RiscvEsp32C3 => "riscv-esp32c3",
Backends::RiscvEsp32C6 => "riscv-esp32c6",
Backends::Riscv32ImcClint | Backends::Riscv32ImacClint => "riscv-clint", Backends::Riscv32ImcClint | Backends::Riscv32ImacClint => "riscv-clint",
} }
} }
@ -203,6 +206,7 @@ pub enum BuildOrCheck {
#[derive(clap::ValueEnum, Copy, Clone, Default, Debug)] #[derive(clap::ValueEnum, Copy, Clone, Default, Debug)]
pub enum Platforms { pub enum Platforms {
Esp32C3, Esp32C3,
Esp32C6,
Hifive1, Hifive1,
#[default] #[default]
Lm3s6965, Lm3s6965,
@ -217,6 +221,7 @@ impl Platforms {
pub fn name(&self) -> String { pub fn name(&self) -> String {
let name = match self { let name = match self {
Platforms::Esp32C3 => "esp32c3", Platforms::Esp32C3 => "esp32c3",
Platforms::Esp32C6 => "esp32c6",
Platforms::Hifive1 => "hifive1", Platforms::Hifive1 => "hifive1",
Platforms::Lm3s6965 => "lm3s6965", Platforms::Lm3s6965 => "lm3s6965",
Platforms::Nrf52840 => "nrf52840", Platforms::Nrf52840 => "nrf52840",
@ -232,7 +237,7 @@ impl Platforms {
pub fn rust_flags(&self) -> Vec<String> { pub fn rust_flags(&self) -> Vec<String> {
let c = "-C".to_string(); let c = "-C".to_string();
match self { match self {
Platforms::Esp32C3 => vec![c, "link-arg=-Tlinkall.x".to_string()], Platforms::Esp32C3 | Platforms::Esp32C6 => vec![c, "link-arg=-Tlinkall.x".to_string()],
Platforms::Hifive1 => vec![c, "link-arg=-Thifive1-link.x".to_string()], Platforms::Hifive1 => vec![c, "link-arg=-Thifive1-link.x".to_string()],
Platforms::Lm3s6965 => vec![c, "link-arg=-Tlink.x".to_string()], Platforms::Lm3s6965 => vec![c, "link-arg=-Tlink.x".to_string()],
Platforms::Nrf52840 => vec![ Platforms::Nrf52840 => vec![
@ -271,6 +276,7 @@ impl Platforms {
pub fn default_backend(&self) -> Backends { pub fn default_backend(&self) -> Backends {
match self { match self {
Platforms::Esp32C3 => Backends::RiscvEsp32C3, Platforms::Esp32C3 => Backends::RiscvEsp32C3,
Platforms::Esp32C6 => Backends::RiscvEsp32C6,
Platforms::Hifive1 => Backends::Riscv32ImcClint, Platforms::Hifive1 => Backends::Riscv32ImcClint,
Platforms::Lm3s6965 => Backends::Thumbv7, Platforms::Lm3s6965 => Backends::Thumbv7,
Platforms::Nrf52840 => unimplemented!(), Platforms::Nrf52840 => unimplemented!(),
@ -290,6 +296,10 @@ impl Platforms {
RISCV32IMC => Ok(None), RISCV32IMC => Ok(None),
_ => Err(()), _ => Err(()),
}, },
Platforms::Esp32C6 => match backend.to_target() {
RISCV32IMAC => Ok(None),
_ => Err(()),
},
Platforms::Hifive1 => match backend.to_target() { Platforms::Hifive1 => match backend.to_target() {
RISCV32IMC | RISCV32IMAC => Ok(None), RISCV32IMC | RISCV32IMAC => Ok(None),
_ => Err(()), _ => Err(()),