From 9bcb32329fc0e12ed7aa90eb8a796f01a851ae19 Mon Sep 17 00:00:00 2001
From: Jorgeig <jorge@jorgeig.com>
Date: Tue, 10 Aug 2021 17:51:10 +0800
Subject: [PATCH] Use cortex-m InterruptNumber iso bare_metal Nr

---
 Cargo.toml               |  4 ++--
 heterogeneous/Cargo.toml |  2 +-
 heterogeneous/src/lib.rs | 10 +++++-----
 homogeneous/Cargo.toml   |  2 +-
 homogeneous/src/lib.rs   | 10 +++++-----
 src/lib.rs               |  4 ++--
 6 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index 5aff249bb1..dbe6140c80 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -13,7 +13,7 @@ license = "MIT OR Apache-2.0"
 name = "cortex-m-rtic"
 readme = "README.md"
 repository = "https://github.com/rtic-rs/cortex-m-rtic"
-version = "0.5.7"
+version = "0.5.8"
 
 [lib]
 name = "rtic"
@@ -51,7 +51,7 @@ name = "types"
 required-features = ["__v7"]
 
 [dependencies]
-cortex-m = "0.6.2"
+cortex-m = "0.7.3"
 cortex-m-rtic-macros = { path = "macros", version = "0.5.3" }
 rtic-core = "0.3.0"
 cortex-m-rt = "0.6.9"
diff --git a/heterogeneous/Cargo.toml b/heterogeneous/Cargo.toml
index 54808a2fe3..fa477f263f 100644
--- a/heterogeneous/Cargo.toml
+++ b/heterogeneous/Cargo.toml
@@ -7,7 +7,7 @@ publish = false
 version = "0.0.0-alpha.0"
 
 [dependencies]
-bare-metal = "0.2.4"
+cortex-m = "0.7.3"
 
 [dependencies.cortex-m-rtic]
 path = ".."
diff --git a/heterogeneous/src/lib.rs b/heterogeneous/src/lib.rs
index 1bda7c851b..848e1cd910 100644
--- a/heterogeneous/src/lib.rs
+++ b/heterogeneous/src/lib.rs
@@ -7,7 +7,7 @@ use core::{
     ops::{Add, Sub},
 };
 
-use bare_metal::Nr;
+use cortex_m::interrupt::InterruptNumber;
 use rtic::{Fraction, Monotonic, MultiCore};
 
 // both cores have the exact same interrupts
@@ -16,7 +16,7 @@ pub use Interrupt_0 as Interrupt_1;
 // Fake priority bits
 pub const NVIC_PRIO_BITS: u8 = 3;
 
-pub fn xpend(_core: u8, _interrupt: impl Nr) {}
+pub fn xpend(_core: u8, _interrupt: impl InterruptNumber) {}
 
 /// Fake monotonic timer
 pub struct MT;
@@ -92,8 +92,8 @@ pub enum Interrupt_0 {
     I7 = 7,
 }
 
-unsafe impl Nr for Interrupt_0 {
-    fn nr(&self) -> u8 {
-        *self as u8
+unsafe impl InterruptNumber for Interrupt_0 {
+    fn number(self) -> u16 {
+        self as u16
     }
 }
diff --git a/homogeneous/Cargo.toml b/homogeneous/Cargo.toml
index 111fe5dfb3..65fa79cae1 100644
--- a/homogeneous/Cargo.toml
+++ b/homogeneous/Cargo.toml
@@ -7,7 +7,7 @@ publish = false
 version = "0.0.0-alpha.0"
 
 [dependencies]
-bare-metal = "0.2.4"
+cortex-m = "0.7.3"
 
 [dependencies.cortex-m-rtic]
 path = ".."
diff --git a/homogeneous/src/lib.rs b/homogeneous/src/lib.rs
index 1bda7c851b..848e1cd910 100644
--- a/homogeneous/src/lib.rs
+++ b/homogeneous/src/lib.rs
@@ -7,7 +7,7 @@ use core::{
     ops::{Add, Sub},
 };
 
-use bare_metal::Nr;
+use cortex_m::interrupt::InterruptNumber;
 use rtic::{Fraction, Monotonic, MultiCore};
 
 // both cores have the exact same interrupts
@@ -16,7 +16,7 @@ pub use Interrupt_0 as Interrupt_1;
 // Fake priority bits
 pub const NVIC_PRIO_BITS: u8 = 3;
 
-pub fn xpend(_core: u8, _interrupt: impl Nr) {}
+pub fn xpend(_core: u8, _interrupt: impl InterruptNumber) {}
 
 /// Fake monotonic timer
 pub struct MT;
@@ -92,8 +92,8 @@ pub enum Interrupt_0 {
     I7 = 7,
 }
 
-unsafe impl Nr for Interrupt_0 {
-    fn nr(&self) -> u8 {
-        *self as u8
+unsafe impl InterruptNumber for Interrupt_0 {
+    fn number(self) -> u16 {
+        self as u16
     }
 }
diff --git a/src/lib.rs b/src/lib.rs
index 5003653168..e00b8d279c 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -45,7 +45,7 @@
 use core::ops::Sub;
 
 use cortex_m::{
-    interrupt::Nr,
+    interrupt::InterruptNumber,
     peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, TPIU},
 };
 #[cfg(all(not(feature = "heterogeneous"), not(feature = "homogeneous")))]
@@ -170,7 +170,7 @@ pub trait MultiCore {}
 /// [`NVIC::pend`](../cortex_m/peripheral/struct.NVIC.html#method.pend)
 pub fn pend<I>(interrupt: I)
 where
-    I: Nr,
+    I: InterruptNumber,
 {
     NVIC::pend(interrupt)
 }