From c8d60d2910137381c9e6101b92976d47e256701e Mon Sep 17 00:00:00 2001 From: n8tlarsen <96437952+n8tlarsen@users.noreply.github.com> Date: Mon, 19 Dec 2022 17:45:53 -0600 Subject: [PATCH] Improve basepri explanation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Henrik Tjäder --- book/en/src/internals/targets.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/book/en/src/internals/targets.md b/book/en/src/internals/targets.md index 0104cdba8c..65c0712534 100644 --- a/book/en/src/internals/targets.md +++ b/book/en/src/internals/targets.md @@ -1,7 +1,7 @@ # Target Architecture While RTIC can currently target all Cortex-m devices there are some key architecure differences that -users should be aware. Namely the absence of hardware priority ceiling (BASEPRI) support in the +users should be aware of. Namely the absence of Base Priority Mask Register (`BASEPRI`) which lends itself exceptionally well to the hardware priority ceiling support used in RTIC, in the ARMv6-M and ARMv8-M-base architectures requires a few tweaks from RTIC to deliver the same features. These differences result in two flavors of critical sections: priority ceiling, and source masking. Table 1 below shows a list of Cortex-m processors and which type of critical section they