Commit graph

79 commits

Author SHA1 Message Date
Emil Fresk
07bd57a20f Fix style 2022-08-03 11:30:32 +02:00
bors[bot]
b87fca3d21
Merge #652
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill

The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error:

```
error[E0432]: unresolved import `cortex_m::register::basepri`
  --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5
   |
25 | use cortex_m::register::basepri;
   |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register`
```

I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check.

Context:
[cortex-m:src/register/mod.rs](4e90862520/src/register/mod.rs (L33)):
```
#[cfg(all(not(armv6m), not(armv8m_base)))]
pub mod basepri;
```

[cortex-m:build.rs](4e90862520/build.rs (L21)):
```
    } else if target.starts_with("thumbv8m.base") {
        println!("cargo:rustc-cfg=cortex_m");
        println!("cargo:rustc-cfg=armv8m");
        println!("cargo:rustc-cfg=armv8m_base");
```

Co-authored-by: David Watson <david@neonquill.com>
2022-07-27 19:15:09 +00:00
David Watson
368ab1d4fb Remove use of basepri register on thumbv8m.base
The basepri register appears to be aviable on thumbv8m.main but not
thumbv8m.base. At the very least, attempting to compile against a
Cortex-M23 based Microchip ATSAML10E16A generates an error:

```
error[E0432]: unresolved import `cortex_m::register::basepri`
  --> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5
   |
25 | use cortex_m::register::basepri;
   |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register`
```

This is an attempt to account for the fact that thumbv8m.base (M23)
MCUs don't have the BASEPRI register but have more than 32
interrupts. This moves away from the architecture specific config
flags and switches to a more functional flag.

Make the mask size depend on the max interrupt id

Rather than assuming a fixed interrupt count of 32 this code uses an
array of u32 bitmasks to calculate the priority mask. The size of this
array is calculated at compile time based on the size of the largest
interrupt id being used in the target code. For thumbv6m this should
be equivalent to the previous version that used a single u32 mask. For
thumbv8m.base it will be larger depending on the interrupts used.

Don't write 0s to the ISER and ICER registers

Writing 0s to these registers is a no-op. Since these masks should be
calculated at compile time, this conditional should result in writes
being optimized out of the code.

Prevent panic on non-arm targets

Panicking on unknown targets was breaking things like the doc build on
linux. This change should only panic when building on unknown arm
targets.
2022-07-27 21:04:24 +02:00
Gabriel Górski
f15614e7cb Update CHANGELOG.md 2022-07-27 20:29:14 +02:00
Henrik Tjäder
563a3c9d4c Release RTIC v1.1.3 2022-06-23 13:58:50 +02:00
Henrik Tjäder
8af754fc72 Bump rtic-syntax to v1.0.2 and fix Changelog 2022-06-23 13:36:14 +02:00
Emil Fresk
906abba71e Prepare v1.1.2 2022-05-09 13:33:49 +02:00
Emil Fresk
9f38a39377 Masks take 3 2022-04-20 10:56:13 +02:00
Emil Fresk
f247cc0b3a Fixed macro version 2022-04-13 19:28:04 +02:00
Henrik Tjäder
4f99399e29 Release RTIC v1.1
Bump versions, including using using latest rtic-syntax
2022-04-13 08:27:17 +02:00
Per Lindgren
f86dab5ff3 Added support for SRP based scheduling for armv6m 2022-03-02 13:23:47 +01:00
bors[bot]
790b074e18
Merge #620
620: Add CHANGELOG instructions and fix incorrectly placed item r=korken89 a=AfoHT



Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-03-01 18:24:46 +00:00
Henrik Tjäder
71d953f0e5 Add CHANGELOG instructions and fix incorrectly placed item 2022-02-22 19:34:54 +01:00
Henrik Tjäder
5ed93bd1bf Clippy with pedantic suggestions 2022-02-22 18:56:21 +01:00
bors[bot]
57da1e0403
Merge #616
616: rtic::mutex::prelude::* fixes glob import lint r=korken89 a=AfoHT

Running cargo Clippy with pedantic rules denied

```
cargo clippy -- --deny clippy::pedantic
```

it will complain:

```
error: usage of wildcard import
   |
16 | use rtic::mutex_prelude::*;
   |     ^^^^^^^^^^^^^^^^^^^^^^ help: try: `rtic::mutex_prelude::{Mutex, TupleExt01, TupleExt02, TupleExt03, TupleExt04, TupleExt05, TupleExt06, TupleExt07, TupleExt08, TupleExt09, TupleExt10, TupleExt11, TupleExt12, TupleExt13, TupleExt14, TupleExt15, TupleExt16, TupleExt17, TupleExt18, TupleExt19, TupleExt20, TupleExt21, TupleExt22, TupleExt23, TupleExt24, TupleExt25, TupleExt26, TupleExt27, TupleExt28, TupleExt29, TupleExt30, TupleExt31, TupleExt32}`
   |
   = note: `-D clippy::wildcard-imports` implied by `-D clippy::pedantic`
   = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#wildcard_imports

error: could not compile --- due to previous error
Error: command `cargo clippy -- --deny clippy::all --deny clippy::pedantic` failed, exit status: 101

```

Looking at the Clippy [wildcard-imports rule](https://rust-lang.github.io/rust-clippy/master/#wildcard_imports)
the exception is for wildcards on modules named prelude. Thus, `prelude::*` is OK.

Current state: `use rtic-core::prelude as mutex_prelude` almost fits the bill, but `mutex_prelude != prelude`.

As this was part of user facing API I don’t think we can remove the current setup,
so rtic-core `Mutex`, `Exclusive` and multi-lock `TupleExt0X` retained in
old location to be backwards compatible.


Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-02-22 17:47:48 +00:00
Henrik Tjäder
2c14c9bce3 rtic::mutex::prelude::* fixes glob import lint
rtic-core Mutex, Exclusive and multi-lock retained in
old location to not be backwards breaking
2022-02-18 18:42:19 +01:00
bors[bot]
110a82f7b6
Merge #608
608: Debug bors r=perlindgren a=AfoHT



Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-02-15 19:25:56 +00:00
Henrik Tjäder
da25327226 Create tiny change 2022-02-15 20:08:38 +01:00
Henrik Tjäder
dfb6e36311 action-rs tool-cache is deprecated, always failing 2022-02-15 20:08:18 +01:00
Henrik Tjäder
5f3c5f7f2c CHANGELOG merge=union 2022-02-15 19:51:54 +01:00
Henrik Tjäder
a8a55a3913 Docs: Fix dated migration docs for spawn 2022-02-10 10:25:50 +01:00
Henrik Tjäder
4d3758a6b2 Update CHANGELOG 2022-02-10 09:54:15 +01:00
Henrik Tjäder
e9675c9a61 Update CHANGELOG 2022-02-10 09:09:55 +01:00
Henrik Tjäder
532765719f docs: make mdBook emit error codes 2022-02-09 17:45:52 +01:00
Henrik Tjäder
7af09cb126 book: Restore accidentally removed files 2022-02-08 19:08:29 +01:00
bors[bot]
9f8248a0c9
Merge #593
593: RTIC macro expansion: Try to find target-dir r=korken89 a=AfoHT

Seems over-engineered, but for projects where 

```
[build]
target-dir = "target"
```
is set to anything other than default `target` RTIC did simply not produce any `rtic-expansion.rs`.

This changes the approach to not giving up if not finding `target/` by looking at `OUT_DIR` and traversing back until `TARGET` is found.

As the `TARGET` target-triple variable is not available, approximate the `TARGET` folder (found in `target-dir`) with `s.starts_with("thumbv")`.

`target-dir` as set in `.cargo/config` will now be the parent directory of the `Path` ending with `TARGET`

## Example running with default target:
```
cortex-m-rtic on  expansionoutdir [$!?] is 📦 v1.0.0 via R v1.58.0 took 4s
❯ cargo build --example spawn --target thumbv7em-none-eabihf
OUT_DIR
"/home/henrik/rust/rtic/cortex-m-rtic/target/thumbv7em-none-eabihf/debug/build/cortex-m-rtic-5bd81e8412a790d5/out"

target/ exists

Write file:
target/rtic-expansion.rs

    Finished dev [unoptimized + debuginfo] target(s) in 7.20s

```

## Contrived example
With `.cargo/config` containing:

```
[build]
target-dir = "/tmp/cargothingy/../rust/./target/cargo"`
```

```
cortex-m-rtic on  expansionoutdir [$!?] is 📦 v1.0.0 via R v1.58.0 took 3s
❯ cargo build --example spawn --target thumbv7em-none-eabihf
OUT_DIR
"/tmp/cargothingy/../rust/./target/cargo/thumbv7em-none-eabihf/debug/build/cortex-m-rtic-5bd81e8412a790d5/out"
"/tmp/cargothingy/../rust/./target/cargo"

Write file:
/tmp/cargothingy/../rust/./target/cargo/rtic-expansion.rs

    Finished dev [unoptimized + debuginfo] target(s) in 6.42s

```

## Less extreme with relative paths
```
[build]
target-dir = "../../cargothingy/target/buildfiles/and-stuff"
```

```
OUT_DIR
"/home/henrik/rust/rtic/cortex-m-rtic/../../cargothingy/target/buildfiles/and-stuff/thumbv7em-none-eabihf/debug/build/cortex-m-rtic-5bd81e8412a790d5/out"
"/home/henrik/rust/rtic/cortex-m-rtic/../../cargothingy/target/buildfiles/and-stuff"

Write file:
/home/henrik/rust/rtic/cortex-m-rtic/../../cargothingy/target/buildfiles/and-stuff/rtic-expansion.rs

    Finished dev [unoptimized + debuginfo] target(s) in 6.78s

```

Note: If the user creates a folder named target in the same directory where `Cargo.toml`/crate root is, that will be used for storing the expansion.

```
<...>
OUT_DIR
"/home/henrik/rust/rtic/cortex-m-rtic/../../cargothingy/target/buildfiles/and-stuff/thumbv7em-none-eabihf/debug/build/cortex-m-rtic-5bd81e8412a790d5/out"

target/ exists

Write file:
target/rtic-expansion.rs

    Finished dev [unoptimized + debuginfo] target(s) in 6.62s
```


Co-authored-by: Henrik Tjäder <henrik@grepit.se>
2022-02-05 09:52:26 +00:00
Robert Jördens
b855c1bc9b add changelog entry 2022-02-04 20:09:32 +01:00
Henrik Tjäder
9f54b4aca8 RTIC macro expansion: Try to find target-dir 2022-01-28 21:21:06 +01:00
Per Lindgren
305e8295d5 Drift free timing examples 2022-01-04 22:21:57 +01:00
Emil Fresk
5d645b1311 Added changelog enforcer 2022-01-03 18:37:54 +01:00
Henrik Tjäder
2b90cd3433 Bump version to 1.0.0 2021-12-25 14:59:27 +01:00
Henrik Tjäder
d81a4da6fb Update changelog 2021-12-14 22:26:16 +01:00
Emil Fresk
5ab5112271 Update versions and changelog 2021-11-09 11:12:04 +01:00
Henrik Tjäder
f7d4b5dc70 CHANGELOG: Add links to v0.6.x 2021-11-08 20:40:59 +01:00
Henrik Tjäder
1438a5b0ea Update changelog from v0.5.x branch 2021-11-08 20:28:57 +01:00
Henrik Tjäder
eb345b7dbb Update CHANGELOG 2021-11-08 18:39:09 +01:00
Emil Fresk
552be420cb Prepare rc.2 release 2021-09-28 10:56:36 +02:00
Emil Fresk
ea8efa4831 Preparing 0.6.0-rc.1 2021-09-27 15:40:21 +02:00
Emil Fresk
f3d9fd9b63 Update changelog and version 2021-07-09 12:54:19 +02:00
Emil Fresk
e8676daeb9 Fixed changelog 2021-05-28 09:07:21 +02:00
Emil Fresk
c17348d290 Prepare release alpha.4 2021-05-27 18:10:24 +02:00
Emil Fresk
cfd0c6ca26 0.6.0-alpha.2 release 2021-04-08 10:33:40 +02:00
Emil Fresk
9cbe639ebf Updated changelog, use released version of rtic-core 2020-11-14 16:16:45 +01:00
Henrik Tjäder
1208e59083 Update the Changelog 2020-11-14 12:58:49 +00:00
Per Lindgren
96cd625223 extern task 2020-10-29 19:29:46 +01:00
Henrik Tjäder
1b99ca6b10 Updating the changelog 2020-10-23 22:19:12 +00:00
Per Lindgren
1c244a995d move dispatchers to app argument 2020-10-23 23:58:09 +02:00
Emil Fresk
697ee6e14c Preparing v0.5.5 release 2020-08-27 14:53:50 +02:00
Emil Fresk
5711a2472d Preparing for 0.5.4 release 2020-08-26 12:41:39 +02:00
Emil Fresk
95032aa56b Updated CHANGELOG 2020-06-12 09:51:09 +02:00