* Rebase to master
* using interrupt_mod
* bug fixes
* fix other backends
* Add changelog
* forgot about rtic-macros
* backend-specific configuration
* core peripherals optional over macro argument
* pre_init_preprocessing binding
* CI for RISC-V (WIP)
* separation of concerns
* add targets for RISC-V examples
* remove qemu feature
* prepare examples folder
* move examples all together
* move ci out of examples
* minor changes
* add cortex-m
* new xtask: proof of concept
* fix build.yml
* feature typo
* clean rtic examples
* reproduce weird issue
* remove unsafe code in user app
* update dependencies
* allow builds on riscv32imc
* let's fix QEMU
* Update .github/workflows/build.yml
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
* New build.rs
* removing test features
* adapt ui test to new version of clippy
* add more examples to RISC-V backend
* proper configuration of heapless for riscv32imc
* opt-out examples for riscv32imc
* point to new version of riscv-slic
* adapt new macro bindings
* adapt examples and CI to stable
* fix cortex-m CI
* Review
---------
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
The RTIC book mentions Embassy+RTIC but gives no examples.
fmt.
Add feature flag
Seems CI does not deal with 2 levels of depth.
Forgot to stage.
Thumb m arch.
Co-authored-by: Corey Schuhen <cschuhen@gmail.com>
* Fix nrf::timer
* Bootstrap nrf52840-blinky example
* More work on nrf blinky example
* Fix README
* Add asserts for correct timer functionality
* Add correctness check to other monotonics as well
* Update Changelog
* Fix potential timing issues
* Fix race condition in nrf::rtc
* Add changelog
* Add rtc blinky example
* Change rtc example to RC lf clock source
* Add changelog to rtic-time
* Add changelog
* Attempt to fix CI
* Update teensy4-blinky Cargo.lock
New semihosting 0.5 does not use error handling,
returns directly and as semihosting is generally slow
this led to missing print statements.
Workaround is to add NOP, which seems sufficient
to let it flush the buffers
