678: Bump actions/cache from 2 to 3 r=AfoHT a=dependabot[bot]
Bumps [actions/cache](https://github.com/actions/cache) from 2 to 3.
<details>
<summary>Release notes</summary>
<p><em>Sourced from <a href="https://github.com/actions/cache/releases">actions/cache's releases</a>.</em></p>
<blockquote>
<h2>v3.0.0</h2>
<ul>
<li>
<p>This change adds a minimum runner version(node12 -> node16), which can break users using an out-of-date/fork of the runner. This would be most commonly affecting users on GHES 3.3 or before, as those runners do not support node16 actions and they can use actions from github.com via <a href="https://docs.github.com/en/enterprise-server@3.0/admin/github-actions/managing-access-to-actions-from-githubcom/enabling-automatic-access-to-githubcom-actions-using-github-connect">github connect</a> or manually copying the repo to their GHES instance.</p>
</li>
<li>
<p>Few dependencies and cache action usage examples have also been updated.</p>
</li>
</ul>
<h2>v2.1.7</h2>
<p>Support 10GB cache upload using the latest version <code>1.0.8</code> of <a href="https://www.npmjs.com/package/`@actions/cache"><code>@actions/cache</code>` </a></p>
<h2>v2.1.6</h2>
<ul>
<li>Catch unhandled "bad file descriptor" errors that sometimes occurs when the cache server returns non-successful response (<a href="https://github-redirect.dependabot.com/actions/cache/pull/596">actions/cache#596</a>)</li>
</ul>
<h2>v2.1.5</h2>
<ul>
<li>Fix permissions error seen when extracting caches with GNU tar that were previously created using BSD tar (<a href="https://github-redirect.dependabot.com/actions/cache/issues/527">actions/cache#527</a>)</li>
</ul>
<h2>v2.1.4</h2>
<ul>
<li>Make caching more verbose <a href="https://github-redirect.dependabot.com/actions/toolkit/pull/650">#650</a></li>
<li>Use GNU tar on macOS if available <a href="https://github-redirect.dependabot.com/actions/toolkit/pull/701">#701</a></li>
</ul>
<h2>v2.1.3</h2>
<ul>
<li>Upgrades <code>`@actions/core</code>` to v1.2.6 for <a href="https://github.com/advisories/GHSA-mfwh-5m23-j46w">CVE-2020-15228</a>. This action was not using the affected methods.</li>
<li>Fix error handling in <code>uploadChunk</code> where 400-level errors were not being detected and handled correctly</li>
</ul>
<h2>v2.1.2</h2>
<ul>
<li>Adds input to limit the chunk upload size, useful for self-hosted runners with slower upload speeds</li>
<li>No-op when executing on GHES</li>
</ul>
<h2>v2.1.1</h2>
<ul>
<li>Update <code>`@actions/cache</code>` package to <code>v1.0.2</code> which allows cache action to use posix format when taring files.</li>
</ul>
<h2>v2.1.0</h2>
<ul>
<li>Replaces the <code>http-client</code> with the Azure Storage SDK for NodeJS when downloading cache content from Azure. This should help improve download performance and reliability as the SDK downloads files in 4 MB chunks, which can be parallelized and retried independently</li>
<li>Display download progress and speed</li>
</ul>
</blockquote>
</details>
<details>
<summary>Changelog</summary>
<p><em>Sourced from <a href="https://github.com/actions/cache/blob/main/RELEASES.md">actions/cache's changelog</a>.</em></p>
<blockquote>
<h1>Releases</h1>
<h3>3.0.0</h3>
<ul>
<li>Updated minimum runner version support from node 12 -> node 16</li>
</ul>
<h3>3.0.1</h3>
<ul>
<li>Added support for caching from GHES 3.5.</li>
<li>Fixed download issue for files > 2GB during restore.</li>
</ul>
<h3>3.0.2</h3>
<ul>
<li>Added support for dynamic cache size cap on GHES.</li>
</ul>
<h3>3.0.3</h3>
<ul>
<li>Fixed avoiding empty cache save when no files are available for caching. (<a href="https://github-redirect.dependabot.com/actions/cache/issues/624">issue</a>)</li>
</ul>
<h3>3.0.4</h3>
<ul>
<li>Fixed tar creation error while trying to create tar with path as <code>~/</code> home folder on <code>ubuntu-latest</code>. (<a href="https://github-redirect.dependabot.com/actions/cache/issues/689">issue</a>)</li>
</ul>
<h3>3.0.5</h3>
<ul>
<li>Removed error handling by consuming actions/cache 3.0 toolkit, Now cache server error handling will be done by toolkit. (<a href="https://github-redirect.dependabot.com/actions/cache/pull/834">PR</a>)</li>
</ul>
<h3>3.0.6</h3>
<ul>
<li>Fixed <a href="https://github-redirect.dependabot.com/actions/cache/issues/809">#809</a> - zstd -d: no such file or directory error</li>
<li>Fixed <a href="https://github-redirect.dependabot.com/actions/cache/issues/833">#833</a> - cache doesn't work with github workspace directory</li>
</ul>
<h3>3.0.7</h3>
<ul>
<li>Fixed <a href="https://github-redirect.dependabot.com/actions/cache/issues/810">#810</a> - download stuck issue. A new timeout is introduced in the download process to abort the download if it gets stuck and doesn't finish within an hour.</li>
</ul>
<h3>3.0.8</h3>
<ul>
<li>Fix zstd not working for windows on gnu tar in issues <a href="https://github-redirect.dependabot.com/actions/cache/issues/888">#888</a> and <a href="https://github-redirect.dependabot.com/actions/cache/issues/891">#891</a>.</li>
<li>Allowing users to provide a custom timeout as input for aborting download of a cache segment using an environment variable <code>SEGMENT_DOWNLOAD_TIMEOUT_MINS</code>. Default is 60 minutes.</li>
</ul>
<h3>3.0.9</h3>
<ul>
<li>Enhanced the warning message for cache unavailablity in case of GHES.</li>
</ul>
<h3>3.0.10</h3>
<ul>
<li>Fix a bug with sorting inputs.</li>
<li>Update definition for restore-keys in README.md</li>
</ul>
<h3>3.0.11</h3>
<ul>
<li>Update toolkit version to 3.0.5 to include <code>`@actions/core@^1.10.0</code></li>`
<li>Update <code>`@actions/cache</code>` to use updated <code>saveState</code> and <code>setOutput</code> functions from <code>`@actions/core@^1.10.0</code></li>`
</ul>
<h3>3.1.0-beta.1</h3>
<ul>
<li>Update <code>`@actions/cache</code>` on windows to use gnu tar and zstd by default and fallback to bsdtar and zstd if gnu tar is not available. (<a href="https://github-redirect.dependabot.com/actions/cache/issues/984">issue</a>)</li>
</ul>
<h3>3.1.0-beta.2</h3>
<ul>
<li>Added support for fallback to gzip to restore old caches on windows.</li>
</ul>
<h3>3.1.0-beta.3</h3>
<!-- raw HTML omitted -->
</blockquote>
<p>... (truncated)</p>
</details>
<details>
<summary>Commits</summary>
<ul>
<li><a href="4723a57e26"><code>4723a57</code></a> Revert compression changes related to windows but keep version logging (<a href="https://github-redirect.dependabot.com/actions/cache/issues/1049">#1049</a>)</li>
<li><a href="d1507cccba"><code>d1507cc</code></a> Merge pull request <a href="https://github-redirect.dependabot.com/actions/cache/issues/1042">#1042</a> from me-and/correct-readme-re-windows</li>
<li><a href="3337563725"><code>3337563</code></a> Merge branch 'main' into correct-readme-re-windows</li>
<li><a href="60c7666709"><code>60c7666</code></a> save/README.md: Fix typo in example (<a href="https://github-redirect.dependabot.com/actions/cache/issues/1040">#1040</a>)</li>
<li><a href="b053f2b699"><code>b053f2b</code></a> Fix formatting error in restore/README.md (<a href="https://github-redirect.dependabot.com/actions/cache/issues/1044">#1044</a>)</li>
<li><a href="501277cfd7"><code>501277c</code></a> README.md: remove outdated Windows cache tip link</li>
<li><a href="c1a5de879e"><code>c1a5de8</code></a> Upgrade codeql to v2 (<a href="https://github-redirect.dependabot.com/actions/cache/issues/1023">#1023</a>)</li>
<li><a href="9b0be58822"><code>9b0be58</code></a> Release compression related changes for windows (<a href="https://github-redirect.dependabot.com/actions/cache/issues/1039">#1039</a>)</li>
<li><a href="c17f4bf466"><code>c17f4bf</code></a> GA for granular cache (<a href="https://github-redirect.dependabot.com/actions/cache/issues/1035">#1035</a>)</li>
<li><a href="ac25611cae"><code>ac25611</code></a> docs: fix an invalid link in workarounds.md (<a href="https://github-redirect.dependabot.com/actions/cache/issues/929">#929</a>)</li>
<li>Additional commits viewable in <a href="https://github.com/actions/cache/compare/v2...v3">compare view</a></li>
</ul>
</details>
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679: Update panic-semihosting requirement from 0.5.2 to 0.6.0 r=AfoHT a=dependabot[bot]
Updates the requirements on [panic-semihosting](https://github.com/rust-embedded/cortex-m) to permit the latest version.
<details>
<summary>Changelog</summary>
<p><em>Sourced from <a href="https://github.com/rust-embedded/cortex-m/blob/master/CHANGELOG.md">panic-semihosting's changelog</a>.</em></p>
<blockquote>
<h2>[v0.6.0] - 2019-03-12</h2>
<h3>Fixed</h3>
<ul>
<li>Fix numerous registers which were incorrectly included for thumbv6</li>
<li><code>SHCRS</code> renamed to <code>SHCSR</code> in <code>SCB</code></li>
</ul>
<h3>Added</h3>
<ul>
<li>
<p>Support for ARMv8-M (<code>thumbv8.base</code> and <code>thumbv8.main</code>)</p>
</li>
<li>
<p><code>SCB</code> gained methods to set and clear <code>SLEEPONEXIT</code> bit</p>
</li>
<li>
<p><code>NVIC</code> gained <code>STIR</code> register and methods to request an interrupt</p>
</li>
<li>
<p><code>DCB</code> gained methods to check if debugger is attached</p>
</li>
</ul>
<h2>[v0.5.8] - 2018-10-27</h2>
<h3>Added</h3>
<ul>
<li>
<p><code>SCB</code> gained methods to set, clear and check the pending state of the PendSV
exception.</p>
</li>
<li>
<p><code>SCB</code> gained methods to set, clear and check the pending state of the SysTick
exception.</p>
</li>
<li>
<p><code>SCB</code> gained methods to set and get the priority of system handlers like
SVCall and SysTick.</p>
</li>
<li>
<p><code>NVIC</code> gained <em>static</em> methods, <code>pend</code> and <code>unpend</code>, to set and clear the
pending state of interrupts.</p>
</li>
</ul>
<h3>Changed</h3>
<ul>
<li>The <code>NVIC.{clear,set}_pending</code> methods have been deprecated in favor of
<code>NVIC::{unpend,pend}</code>.</li>
</ul>
<h2>[v0.5.7] - 2018-09-06</h2>
<h3>Added</h3>
<ul>
<li><code>DCB::enable_trace()</code> and <code>DCB::disable_trace()</code></li>
</ul>
<h3>Changed</h3>
<ul>
<li><code>iprintln!</code> no longer depends on <code>iprint!</code>. <code>cortex_m::iprintln!</code> will work
even if <code>cortex_m::iprint</code> has not been imported.</li>
</ul>
<h2>[v0.5.6] - 2018-08-27</h2>
<!-- raw HTML omitted -->
</blockquote>
<p>... (truncated)</p>
</details>
<details>
<summary>Commits</summary>
<ul>
<li><a href="c61e3af53a"><code>c61e3af</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/135">#135</a></li>
<li><a href="3e580d9d92"><code>3e580d9</code></a> v0.6.0</li>
<li><a href="563c27a152"><code>563c27a</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/106">#106</a></li>
<li><a href="3b574e88fb"><code>3b574e8</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/127">#127</a></li>
<li><a href="771fc84d6e"><code>771fc84</code></a> Fix STIR register test, remove armv6m-related offsets in NVIC</li>
<li><a href="ac5f677f57"><code>ac5f677</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/97">#97</a></li>
<li><a href="04ee333b63"><code>04ee333</code></a> Merge <a href="https://github-redirect.dependabot.com/rust-embedded/cortex-m/issues/126">#126</a></li>
<li><a href="2ff4735cda"><code>2ff4735</code></a> Update is_debugger_attached so as not to clear S_RESET_ST and S_RETIRE_ST</li>
<li><a href="2a15caa848"><code>2a15caa</code></a> Fix rebase syntax error; disable STIR test on armv6m</li>
<li><a href="595fbd7346"><code>595fbd7</code></a> Expand is_debugger_attached note</li>
<li>Additional commits viewable in <a href="https://github.com/rust-embedded/cortex-m/compare/v0.5.2...v0.6.0">compare view</a></li>
</ul>
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Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
669: CI: Run rustup and cargo directly r=korken89 a=AfoHT
actions-rs seems abandoned: See [link](https://github.com/actions-rs/toolchain/issues/216)
As GHA bundles rustup using it directly is trivial
Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
660: Clarify r=AfoHT a=01joja
I made 3 suggested changes
- `.cargo/config` -> `.cargo/config.toml`. Now extensions for vs code recognizes that it is a toml-file.
- Moved a note about how to configure target in cargo.toml to by-example.md from app_init.md.
- changed all occurrences of `.cargo/config` to `.cargo/config.toml` in the ru and eng version of the book.
Co-authored-by: Jonas Jacobsson <01joja@gmail.com>
652: Remove use of basepri register on thumbv8m.base r=AfoHT a=neonquill
The basepri register appears to be aviable on thumbv8m.main but not thumbv8m.base. At the very least, attempting to compile against a Cortex-M23 based Microchip ATSAML10E16A generates an error:
```
error[E0432]: unresolved import `cortex_m::register::basepri`
--> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5
|
25 | use cortex_m::register::basepri;
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register`
```
I wasn't sure if it made more sense to replace the `armv7m` config flag with something related to basepri availability or to get closer to matching the cortex-m use of several architecture specific flags. In the end i chose to make the minimal change possible and just narrowed the existing `thumbv8m` check.
Context:
[cortex-m:src/register/mod.rs](4e90862520/src/register/mod.rs (L33)):
```
#[cfg(all(not(armv6m), not(armv8m_base)))]
pub mod basepri;
```
[cortex-m:build.rs](4e90862520/build.rs (L21)):
```
} else if target.starts_with("thumbv8m.base") {
println!("cargo:rustc-cfg=cortex_m");
println!("cargo:rustc-cfg=armv8m");
println!("cargo:rustc-cfg=armv8m_base");
```
Co-authored-by: David Watson <david@neonquill.com>
The basepri register appears to be aviable on thumbv8m.main but not
thumbv8m.base. At the very least, attempting to compile against a
Cortex-M23 based Microchip ATSAML10E16A generates an error:
```
error[E0432]: unresolved import `cortex_m::register::basepri`
--> /Users/dwatson/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rtic-1.1.3/src/export.rs:25:5
|
25 | use cortex_m::register::basepri;
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^ no `basepri` in `register`
```
This is an attempt to account for the fact that thumbv8m.base (M23)
MCUs don't have the BASEPRI register but have more than 32
interrupts. This moves away from the architecture specific config
flags and switches to a more functional flag.
Make the mask size depend on the max interrupt id
Rather than assuming a fixed interrupt count of 32 this code uses an
array of u32 bitmasks to calculate the priority mask. The size of this
array is calculated at compile time based on the size of the largest
interrupt id being used in the target code. For thumbv6m this should
be equivalent to the previous version that used a single u32 mask. For
thumbv8m.base it will be larger depending on the interrupts used.
Don't write 0s to the ISER and ICER registers
Writing 0s to these registers is a no-op. Since these masks should be
calculated at compile time, this conditional should result in writes
being optimized out of the code.
Prevent panic on non-arm targets
Panicking on unknown targets was breaking things like the doc build on
linux. This change should only panic when building on unknown arm
targets.
653: Allow custom `link_section` attributes for late resources r=AfoHT a=vccggorski
This commit makes RTIC aware of user-provided `link_section` attributes,
letting user override default section mapping.
Co-authored-by: Gabriel Górski <gabriel.gorski@volvocars.com>
649: Bump rtic-syntax to v1.0.2 and fix Changelog r=korken89 a=AfoHT
Use the latest rtic-syntax, update the changelog with the last few undocumented releases
Co-authored-by: Henrik Tjäder <henrik@grepit.se>
645: fix ci: use SYST::PTR r=korken89 a=japaric
SYST::ptr has been deprecated in cortex-m v0.7.5
SYST::PTR is available since cortex-m v0.7.0
CI was failing due to a warning turned into an error by `deny(warnings)`
Co-authored-by: Jorge Aparicio <jorge.aparicio@ferrous-systems.com>
