searchState.loadedDescShard("rp2040_pac", 1, "61: Select Timer 2 as TREQ (Optional)\n62: Select Timer 3 as TREQ (Optional)\nSelect a Transfer Request signal. The channel uses the …\nField <code>TREQ_SEL</code> reader - Select a Transfer Request signal. …\nField <code>TREQ_SEL</code> writer - Select a Transfer Request signal. …\n21: Select UART0’s RX FIFO as TREQ\n20: Select UART0’s TX FIFO as TREQ\n23: Select UART1’s RX FIFO as TREQ\n22: Select UART1’s TX FIFO as TREQ\nRegister <code>CH_AL3_CTRL</code> writer\nField <code>WRITE_ERROR</code> reader - If 1, the channel received a …\nField <code>WRITE_ERROR</code> writer - If 1, the channel received a …\n39: Select the XIP SSI RX FIFO as TREQ\n38: Select the XIP SSI TX FIFO as TREQ\n37: Select the XIP Streaming FIFO as TREQ\nSelect the ADC as TREQ\nBit 31 - Logical OR of the READ_ERROR and WRITE_ERROR …\nWrites raw bits to the register.\nBit 22 - Apply byte-swap transformation to DMA data. For …\nBit 22 - Apply byte-swap transformation to DMA data. For …\nBit 24 - This flag goes high when the channel starts a new …\nBits 11:14 - When this channel completes, it will trigger …\nBits 11:14 - When this channel completes, it will trigger …\nBits 2:3 - Set the size of each bus transfer …\nBits 2:3 - Set the size of each bus transfer …\nBit 0 - DMA Channel Enable. When 1, the channel will …\nBit 0 - DMA Channel Enable. When 1, the channel will …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 1 - HIGH_PRIORITY gives a channel preferential …\nBit 1 - HIGH_PRIORITY gives a channel preferential …\nSelect I2C0’s RX FIFO as TREQ\nSelect I2C0’s TX FIFO as TREQ\nSelect I2C1’s RX FIFO as TREQ\nSelect I2C1’s TX FIFO as TREQ\nBit 4 - If 1, the read address increments with each …\nBit 4 - If 1, the read address increments with each …\nBit 5 - If 1, the write address increments with each …\nBit 5 - If 1, the write address increments with each …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nBit 21 - In QUIET mode, the channel does not generate IRQs …\nBit 21 - In QUIET mode, the channel does not generate IRQs …\nSelect the ADC as TREQ\nSelect I2C0’s RX FIFO as TREQ\nSelect I2C0’s TX FIFO as TREQ\nSelect I2C1’s RX FIFO as TREQ\nSelect I2C1’s TX FIFO as TREQ\nPermanent request, for unpaced transfers.\nSelect PIO0’s RX FIFO 0 as TREQ\nSelect PIO0’s RX FIFO 1 as TREQ\nSelect PIO0’s RX FIFO 2 as TREQ\nSelect PIO0’s RX FIFO 3 as TREQ\nSelect PIO0’s TX FIFO 0 as TREQ\nSelect PIO0’s TX FIFO 1 as TREQ\nSelect PIO0’s TX FIFO 2 as TREQ\nSelect PIO0’s TX FIFO 3 as TREQ\nSelect PIO1’s RX FIFO 0 as TREQ\nSelect PIO1’s RX FIFO 1 as TREQ\nSelect PIO1’s RX FIFO 2 as TREQ\nSelect PIO1’s RX FIFO 3 as TREQ\nSelect PIO1’s TX FIFO 0 as TREQ\nSelect PIO1’s TX FIFO 1 as TREQ\nSelect PIO1’s TX FIFO 2 as TREQ\nSelect PIO1’s TX FIFO 3 as TREQ\nSelect PWM Counter 0’s Wrap Value as TREQ\nSelect PWM Counter 1’s Wrap Value as TREQ\nSelect PWM Counter 2’s Wrap Value as TREQ\nSelect PWM Counter 3’s Wrap Value as TREQ\nSelect PWM Counter 4’s Wrap Value as TREQ\nSelect PWM Counter 5’s Wrap Value as TREQ\nSelect PWM Counter 6’s Wrap Value as TREQ\nSelect PWM Counter 7’s Wrap Value as TREQ\n<code>0</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nSelect SPI0’s RX FIFO as TREQ\nSelect SPI0’s TX FIFO as TREQ\nSelect SPI1’s RX FIFO as TREQ\nSelect SPI1’s TX FIFO as TREQ\nSelect Timer 0 as TREQ\nSelect Timer 1 as TREQ\nSelect Timer 2 as TREQ (Optional)\nSelect Timer 3 as TREQ (Optional)\nSelect UART0’s RX FIFO as TREQ\nSelect UART0’s TX FIFO as TREQ\nSelect UART1’s RX FIFO as TREQ\nSelect UART1’s TX FIFO as TREQ\nSelect the XIP SSI RX FIFO as TREQ\nSelect the XIP SSI TX FIFO as TREQ\nSelect the XIP Streaming FIFO as TREQ\nPermanent request, for unpaced transfers.\nSelect PIO0’s RX FIFO 0 as TREQ\nSelect PIO0’s RX FIFO 1 as TREQ\nSelect PIO0’s RX FIFO 2 as TREQ\nSelect PIO0’s RX FIFO 3 as TREQ\nSelect PIO0’s TX FIFO 0 as TREQ\nSelect PIO0’s TX FIFO 1 as TREQ\nSelect PIO0’s TX FIFO 2 as TREQ\nSelect PIO0’s TX FIFO 3 as TREQ\nSelect PIO1’s RX FIFO 0 as TREQ\nSelect PIO1’s RX FIFO 1 as TREQ\nSelect PIO1’s RX FIFO 2 as TREQ\nSelect PIO1’s RX FIFO 3 as TREQ\nSelect PIO1’s TX FIFO 0 as TREQ\nSelect PIO1’s TX FIFO 1 as TREQ\nSelect PIO1’s TX FIFO 2 as TREQ\nSelect PIO1’s TX FIFO 3 as TREQ\nSelect PWM Counter 0’s Wrap Value as TREQ\nSelect PWM Counter 1’s Wrap Value as TREQ\nSelect PWM Counter 2’s Wrap Value as TREQ\nSelect PWM Counter 3’s Wrap Value as TREQ\nSelect PWM Counter 4’s Wrap Value as TREQ\nSelect PWM Counter 5’s Wrap Value as TREQ\nSelect PWM Counter 6’s Wrap Value as TREQ\nSelect PWM Counter 7’s Wrap Value as TREQ\nBit 30 - If 1, the channel received a read bus error. …\nBit 30 - If 1, the channel received a read bus error. …\n<code>0</code>\nBit 10 - Select whether RING_SIZE applies to read or write …\nBit 10 - Select whether RING_SIZE applies to read or write …\nBits 6:9 - Size of address wrap region. If 0, don’t …\nBits 6:9 - Size of address wrap region. If 0, don’t …\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 23 - If 1, this channel’s data transfers are visible …\nBit 23 - If 1, this channel’s data transfers are visible …\nSelect SPI0’s RX FIFO as TREQ\nSelect SPI0’s TX FIFO as TREQ\nSelect SPI1’s RX FIFO as TREQ\nSelect SPI1’s TX FIFO as TREQ\nSelect Timer 0 as TREQ\nSelect Timer 1 as TREQ\nSelect Timer 2 as TREQ (Optional)\nSelect Timer 3 as TREQ (Optional)\nBits 15:20 - Select a Transfer Request signal. The channel …\nBits 15:20 - Select a Transfer Request signal. The channel …\nSelect UART0’s RX FIFO as TREQ\nSelect UART0’s TX FIFO as TREQ\nSelect UART1’s RX FIFO as TREQ\nSelect UART1’s TX FIFO as TREQ\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nBit 29 - If 1, the channel received a write bus error. …\nBit 29 - If 1, the channel received a write bus error. …\nSelect the XIP SSI RX FIFO as TREQ\nSelect the XIP SSI TX FIFO as TREQ\nSelect the XIP Streaming FIFO as TREQ\nAlias for channel 0 READ_ADDR register This is a trigger …\nRegister <code>CH_AL3_READ_ADDR_TRIG</code> reader\nRegister <code>CH_AL3_READ_ADDR_TRIG</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nAlias for channel 0 TRANS_COUNT register\nRegister <code>CH_AL3_TRANS_COUNT</code> reader\nRegister <code>CH_AL3_TRANS_COUNT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nAlias for channel 0 WRITE_ADDR register\nRegister <code>CH_AL3_WRITE_ADDR</code> reader\nRegister <code>CH_AL3_WRITE_ADDR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\n36: Select the ADC as TREQ\nField <code>AHB_ERROR</code> reader - Logical OR of the READ_ERROR and …\nField <code>BSWAP</code> reader - Apply byte-swap transformation to DMA …\nField <code>BSWAP</code> writer - Apply byte-swap transformation to DMA …\nField <code>BUSY</code> reader - This flag goes high when the channel …\nField <code>CHAIN_TO</code> reader - When this channel completes, it …\nField <code>CHAIN_TO</code> writer - When this channel completes, it …\nDMA Channel 0 Control and Status\nSet the size of each bus transfer (byte/halfword/word). …\nField <code>DATA_SIZE</code> reader - Set the size of each bus transfer …\nField <code>DATA_SIZE</code> writer - Set the size of each bus transfer …\nField <code>EN</code> reader - DMA Channel Enable. When 1, the channel …\nField <code>EN</code> writer - DMA Channel Enable. When 1, the channel …\nField <code>HIGH_PRIORITY</code> reader - HIGH_PRIORITY gives a channel …\nField <code>HIGH_PRIORITY</code> writer - HIGH_PRIORITY gives a channel …\n33: Select I2C0’s RX FIFO as TREQ\n32: Select I2C0’s TX FIFO as TREQ\n35: Select I2C1’s RX FIFO as TREQ\n34: Select I2C1’s TX FIFO as TREQ\nField <code>INCR_READ</code> reader - If 1, the read address increments …\nField <code>INCR_READ</code> writer - If 1, the read address increments …\nField <code>INCR_WRITE</code> reader - If 1, the write address …\nField <code>INCR_WRITE</code> writer - If 1, the write address …\nField <code>IRQ_QUIET</code> reader - In QUIET mode, the channel does …\nField <code>IRQ_QUIET</code> writer - In QUIET mode, the channel does …\n63: Permanent request, for unpaced transfers.\n4: Select PIO0’s RX FIFO 0 as TREQ\n5: Select PIO0’s RX FIFO 1 as TREQ\n6: Select PIO0’s RX FIFO 2 as TREQ\n7: Select PIO0’s RX FIFO 3 as TREQ\n0: Select PIO0’s TX FIFO 0 as TREQ\n1: Select PIO0’s TX FIFO 1 as TREQ\n2: Select PIO0’s TX FIFO 2 as TREQ\n3: Select PIO0’s TX FIFO 3 as TREQ\n12: Select PIO1’s RX FIFO 0 as TREQ\n13: Select PIO1’s RX FIFO 1 as TREQ\n14: Select PIO1’s RX FIFO 2 as TREQ\n15: Select PIO1’s RX FIFO 3 as TREQ\n8: Select PIO1’s TX FIFO 0 as TREQ\n9: Select PIO1’s TX FIFO 1 as TREQ\n10: Select PIO1’s TX FIFO 2 as TREQ\n11: Select PIO1’s TX FIFO 3 as TREQ\n24: Select PWM Counter 0’s Wrap Value as TREQ\n25: Select PWM Counter 1’s Wrap Value as TREQ\n26: Select PWM Counter 2’s Wrap Value as TREQ\n27: Select PWM Counter 3’s Wrap Value as TREQ\n28: Select PWM Counter 4’s Wrap Value as TREQ\n29: Select PWM Counter 5’s Wrap Value as TREQ\n30: Select PWM Counter 6’s Wrap Value as TREQ\n31: Select PWM Counter 7’s Wrap Value as TREQ\nRegister <code>CH_CTRL_TRIG</code> reader\nField <code>READ_ERROR</code> reader - If 1, the channel received a …\nField <code>READ_ERROR</code> writer - If 1, the channel received a …\n0: <code>0</code>\nField <code>RING_SEL</code> reader - Select whether RING_SIZE applies …\nField <code>RING_SEL</code> writer - Select whether RING_SIZE applies …\nSize of address wrap region. If 0, don’t wrap. For …\nField <code>RING_SIZE</code> reader - Size of address wrap region. If …\nField <code>RING_SIZE</code> writer - Size of address wrap region. If …\n0: <code>0</code>\n1: <code>1</code>\n2: <code>10</code>\nField <code>SNIFF_EN</code> reader - If 1, this channel’s data …\nField <code>SNIFF_EN</code> writer - If 1, this channel’s data …\n17: Select SPI0’s RX FIFO as TREQ\n16: Select SPI0’s TX FIFO as TREQ\n19: Select SPI1’s RX FIFO as TREQ\n18: Select SPI1’s TX FIFO as TREQ\n59: Select Timer 0 as TREQ\n60: Select Timer 1 as TREQ\n61: Select Timer 2 as TREQ (Optional)\n62: Select Timer 3 as TREQ (Optional)\nSelect a Transfer Request signal. The channel uses the …\nField <code>TREQ_SEL</code> reader - Select a Transfer Request signal. …\nField <code>TREQ_SEL</code> writer - Select a Transfer Request signal. …\n21: Select UART0’s RX FIFO as TREQ\n20: Select UART0’s TX FIFO as TREQ\n23: Select UART1’s RX FIFO as TREQ\n22: Select UART1’s TX FIFO as TREQ\nRegister <code>CH_CTRL_TRIG</code> writer\nField <code>WRITE_ERROR</code> reader - If 1, the channel received a …\nField <code>WRITE_ERROR</code> writer - If 1, the channel received a …\n39: Select the XIP SSI RX FIFO as TREQ\n38: Select the XIP SSI TX FIFO as TREQ\n37: Select the XIP Streaming FIFO as TREQ\nSelect the ADC as TREQ\nBit 31 - Logical OR of the READ_ERROR and WRITE_ERROR …\nWrites raw bits to the register.\nBit 22 - Apply byte-swap transformation to DMA data. For …\nBit 22 - Apply byte-swap transformation to DMA data. For …\nBit 24 - This flag goes high when the channel starts a new …\nBits 11:14 - When this channel completes, it will trigger …\nBits 11:14 - When this channel completes, it will trigger …\nBits 2:3 - Set the size of each bus transfer …\nBits 2:3 - Set the size of each bus transfer …\nBit 0 - DMA Channel Enable. When 1, the channel will …\nBit 0 - DMA Channel Enable. When 1, the channel will …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 1 - HIGH_PRIORITY gives a channel preferential …\nBit 1 - HIGH_PRIORITY gives a channel preferential …\nSelect I2C0’s RX FIFO as TREQ\nSelect I2C0’s TX FIFO as TREQ\nSelect I2C1’s RX FIFO as TREQ\nSelect I2C1’s TX FIFO as TREQ\nBit 4 - If 1, the read address increments with each …\nBit 4 - If 1, the read address increments with each …\nBit 5 - If 1, the write address increments with each …\nBit 5 - If 1, the write address increments with each …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nBit 21 - In QUIET mode, the channel does not generate IRQs …\nBit 21 - In QUIET mode, the channel does not generate IRQs …\nSelect the ADC as TREQ\nSelect I2C0’s RX FIFO as TREQ\nSelect I2C0’s TX FIFO as TREQ\nSelect I2C1’s RX FIFO as TREQ\nSelect I2C1’s TX FIFO as TREQ\nPermanent request, for unpaced transfers.\nSelect PIO0’s RX FIFO 0 as TREQ\nSelect PIO0’s RX FIFO 1 as TREQ\nSelect PIO0’s RX FIFO 2 as TREQ\nSelect PIO0’s RX FIFO 3 as TREQ\nSelect PIO0’s TX FIFO 0 as TREQ\nSelect PIO0’s TX FIFO 1 as TREQ\nSelect PIO0’s TX FIFO 2 as TREQ\nSelect PIO0’s TX FIFO 3 as TREQ\nSelect PIO1’s RX FIFO 0 as TREQ\nSelect PIO1’s RX FIFO 1 as TREQ\nSelect PIO1’s RX FIFO 2 as TREQ\nSelect PIO1’s RX FIFO 3 as TREQ\nSelect PIO1’s TX FIFO 0 as TREQ\nSelect PIO1’s TX FIFO 1 as TREQ\nSelect PIO1’s TX FIFO 2 as TREQ\nSelect PIO1’s TX FIFO 3 as TREQ\nSelect PWM Counter 0’s Wrap Value as TREQ\nSelect PWM Counter 1’s Wrap Value as TREQ\nSelect PWM Counter 2’s Wrap Value as TREQ\nSelect PWM Counter 3’s Wrap Value as TREQ\nSelect PWM Counter 4’s Wrap Value as TREQ\nSelect PWM Counter 5’s Wrap Value as TREQ\nSelect PWM Counter 6’s Wrap Value as TREQ\nSelect PWM Counter 7’s Wrap Value as TREQ\n<code>0</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nSelect SPI0’s RX FIFO as TREQ\nSelect SPI0’s TX FIFO as TREQ\nSelect SPI1’s RX FIFO as TREQ\nSelect SPI1’s TX FIFO as TREQ\nSelect Timer 0 as TREQ\nSelect Timer 1 as TREQ\nSelect Timer 2 as TREQ (Optional)\nSelect Timer 3 as TREQ (Optional)\nSelect UART0’s RX FIFO as TREQ\nSelect UART0’s TX FIFO as TREQ\nSelect UART1’s RX FIFO as TREQ\nSelect UART1’s TX FIFO as TREQ\nSelect the XIP SSI RX FIFO as TREQ\nSelect the XIP SSI TX FIFO as TREQ\nSelect the XIP Streaming FIFO as TREQ\nPermanent request, for unpaced transfers.\nSelect PIO0’s RX FIFO 0 as TREQ\nSelect PIO0’s RX FIFO 1 as TREQ\nSelect PIO0’s RX FIFO 2 as TREQ\nSelect PIO0’s RX FIFO 3 as TREQ\nSelect PIO0’s TX FIFO 0 as TREQ\nSelect PIO0’s TX FIFO 1 as TREQ\nSelect PIO0’s TX FIFO 2 as TREQ\nSelect PIO0’s TX FIFO 3 as TREQ\nSelect PIO1’s RX FIFO 0 as TREQ\nSelect PIO1’s RX FIFO 1 as TREQ\nSelect PIO1’s RX FIFO 2 as TREQ\nSelect PIO1’s RX FIFO 3 as TREQ\nSelect PIO1’s TX FIFO 0 as TREQ\nSelect PIO1’s TX FIFO 1 as TREQ\nSelect PIO1’s TX FIFO 2 as TREQ\nSelect PIO1’s TX FIFO 3 as TREQ\nSelect PWM Counter 0’s Wrap Value as TREQ\nSelect PWM Counter 1’s Wrap Value as TREQ\nSelect PWM Counter 2’s Wrap Value as TREQ\nSelect PWM Counter 3’s Wrap Value as TREQ\nSelect PWM Counter 4’s Wrap Value as TREQ\nSelect PWM Counter 5’s Wrap Value as TREQ\nSelect PWM Counter 6’s Wrap Value as TREQ\nSelect PWM Counter 7’s Wrap Value as TREQ\nBit 30 - If 1, the channel received a read bus error. …\nBit 30 - If 1, the channel received a read bus error. …\n<code>0</code>\nBit 10 - Select whether RING_SIZE applies to read or write …\nBit 10 - Select whether RING_SIZE applies to read or write …\nBits 6:9 - Size of address wrap region. If 0, don’t …\nBits 6:9 - Size of address wrap region. If 0, don’t …\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 23 - If 1, this channel’s data transfers are visible …\nBit 23 - If 1, this channel’s data transfers are visible …\nSelect SPI0’s RX FIFO as TREQ\nSelect SPI0’s TX FIFO as TREQ\nSelect SPI1’s RX FIFO as TREQ\nSelect SPI1’s TX FIFO as TREQ\nSelect Timer 0 as TREQ\nSelect Timer 1 as TREQ\nSelect Timer 2 as TREQ (Optional)\nSelect Timer 3 as TREQ (Optional)\nBits 15:20 - Select a Transfer Request signal. The channel …\nBits 15:20 - Select a Transfer Request signal. The channel …\nSelect UART0’s RX FIFO as TREQ\nSelect UART0’s TX FIFO as TREQ\nSelect UART1’s RX FIFO as TREQ\nSelect UART1’s TX FIFO as TREQ\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nBit 29 - If 1, the channel received a write bus error. …\nBit 29 - If 1, the channel received a write bus error. …\nSelect the XIP SSI RX FIFO as TREQ\nSelect the XIP SSI TX FIFO as TREQ\nSelect the XIP Streaming FIFO as TREQ\nDMA Channel 0 Read Address pointer This register updates …\nRegister <code>CH_READ_ADDR</code> reader\nRegister <code>CH_READ_ADDR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDMA Channel 0 Transfer Count Program the number of bus …\nRegister <code>CH_TRANS_COUNT</code> reader\nRegister <code>CH_TRANS_COUNT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDMA Channel 0 Write Address pointer This register updates …\nRegister <code>CH_WRITE_ADDR</code> reader\nRegister <code>CH_WRITE_ADDR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CHAN_ABORT</code> reader - Each bit corresponds to a …\nAbort an in-progress transfer sequence on one or more …\nField <code>CHAN_ABORT</code> writer - Each bit corresponds to a …\nRegister <code>CHAN_ABORT</code> reader\nRegister <code>CHAN_ABORT</code> writer\nWrites raw bits to the register.\nBits 0:15 - Each bit corresponds to a channel. Writing a 1 …\nBits 0:15 - Each bit corresponds to a channel. Writing a 1 …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDebug RAF, WAF, TDF levels\nRegister <code>FIFO_LEVELS</code> reader\nField <code>RAF_LVL</code> reader - Current Read-Address-FIFO fill level\nField <code>TDF_LVL</code> reader - Current Transfer-Data-FIFO fill …\nField <code>WAF_LVL</code> reader - Current Write-Address-FIFO fill …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:23 - Current Read-Address-FIFO fill level\nBits 0:7 - Current Transfer-Data-FIFO fill level\nBits 8:15 - Current Write-Address-FIFO fill level\nField <code>INTE0</code> reader - Set bit n to pass interrupts from …\nInterrupt Enables for IRQ 0\nField <code>INTE0</code> writer - Set bit n to pass interrupts from …\nRegister <code>INTE0</code> reader\nRegister <code>INTE0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - Set bit n to pass interrupts from channel n to …\nBits 0:15 - Set bit n to pass interrupts from channel n to …\nCalls <code>U::from(self)</code>.\nField <code>INTE1</code> reader - Set bit n to pass interrupts from …\nInterrupt Enables for IRQ 1\nField <code>INTE1</code> writer - Set bit n to pass interrupts from …\nRegister <code>INTE1</code> reader\nRegister <code>INTE1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - Set bit n to pass interrupts from channel n to …\nBits 0:15 - Set bit n to pass interrupts from channel n to …\nCalls <code>U::from(self)</code>.\nField <code>INTF0</code> reader - Write 1s to force the corresponding …\nForce Interrupts\nField <code>INTF0</code> writer - Write 1s to force the corresponding …\nRegister <code>INTF0</code> reader\nRegister <code>INTF0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - Write 1s to force the corresponding bits in …\nBits 0:15 - Write 1s to force the corresponding bits in …\nCalls <code>U::from(self)</code>.\nField <code>INTF1</code> reader - Write 1s to force the corresponding …\nForce Interrupts for IRQ 1\nField <code>INTF1</code> writer - Write 1s to force the corresponding …\nRegister <code>INTF1</code> reader\nRegister <code>INTF1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - Write 1s to force the corresponding bits in …\nBits 0:15 - Write 1s to force the corresponding bits in …\nCalls <code>U::from(self)</code>.\nField <code>INTR</code> reader - Raw interrupt status for DMA Channels …\nInterrupt Status (raw)\nField <code>INTR</code> writer - Raw interrupt status for DMA Channels …\nRegister <code>INTR</code> reader\nRegister <code>INTR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15 - Raw interrupt status for DMA Channels 0..15. …\nBits 0:15 - Raw interrupt status for DMA Channels 0..15. …\nField <code>INTS0</code> reader - Indicates active channel interrupt …\nInterrupt Status for IRQ 0\nField <code>INTS0</code> writer - Indicates active channel interrupt …\nRegister <code>INTS0</code> reader\nRegister <code>INTS0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15 - Indicates active channel interrupt requests …\nBits 0:15 - Indicates active channel interrupt requests …\nField <code>INTS1</code> reader - Indicates active channel interrupt …\nInterrupt Status (masked) for IRQ 1\nField <code>INTS1</code> writer - Indicates active channel interrupt …\nRegister <code>INTS1</code> reader\nRegister <code>INTS1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15 - Indicates active channel interrupt requests …\nBits 0:15 - Indicates active channel interrupt requests …\nField <code>MULTI_CHAN_TRIGGER</code> reader - Each bit in this …\nTrigger one or more channels simultaneously\nField <code>MULTI_CHAN_TRIGGER</code> writer - Each bit in this …\nRegister <code>MULTI_CHAN_TRIGGER</code> reader\nRegister <code>MULTI_CHAN_TRIGGER</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15 - Each bit in this register corresponds to a DMA …\nBits 0:15 - Each bit in this register corresponds to a DMA …\nField <code>N_CHANNELS</code> reader -\nThe number of channels this DMA instance is equipped with. …\nRegister <code>N_CHANNELS</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:4\nField <code>BSWAP</code> reader - Locally perform a byte reverse on the …\nField <code>BSWAP</code> writer - Locally perform a byte reverse on the …\nValue on reset: 0\nField <code>CALC</code> reader -\nField <code>CALC</code> writer -\n2: Calculate a CRC-16-CCITT\n3: Calculate a CRC-16-CCITT with bit reversed data\n0: Calculate a CRC-32 (IEEE802.3 polynomial)\n1: Calculate a CRC-32 (IEEE802.3 polynomial) with bit …\nField <code>DMACH</code> reader - DMA channel for Sniffer to observe\nField <code>DMACH</code> writer - DMA channel for Sniffer to observe\nField <code>EN</code> reader - Enable sniffer\nField <code>EN</code> writer - Enable sniffer\n14: XOR reduction over all data. == 1 if the total 1 …\nField <code>OUT_INV</code> reader - If set, the result appears inverted …\nField <code>OUT_INV</code> writer - If set, the result appears inverted …\nField <code>OUT_REV</code> reader - If set, the result appears …\nField <code>OUT_REV</code> writer - If set, the result appears …\nRegister <code>SNIFF_CTRL</code> reader\nSniffer Control\n15: Calculate a simple 32-bit checksum (addition with a 32 …\nRegister <code>SNIFF_CTRL</code> writer\nWrites raw bits to the register.\nBit 9 - Locally perform a byte reverse on the sniffed …\nBit 9 - Locally perform a byte reverse on the sniffed …\nBits 5:8\nBits 5:8\nCalculate a CRC-16-CCITT\nCalculate a CRC-16-CCITT with bit reversed data\nCalculate a CRC-32 (IEEE802.3 polynomial)\nCalculate a CRC-32 (IEEE802.3 polynomial) with bit …\nBits 1:4 - DMA channel for Sniffer to observe\nBits 1:4 - DMA channel for Sniffer to observe\nBit 0 - Enable sniffer\nBit 0 - Enable sniffer\nXOR reduction over all data. == 1 if the total 1 …\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalculate a CRC-16-CCITT\nCalculate a CRC-16-CCITT with bit reversed data\nCalculate a CRC-32 (IEEE802.3 polynomial)\nCalculate a CRC-32 (IEEE802.3 polynomial) with bit …\nXOR reduction over all data. == 1 if the total 1 …\nCalculate a simple 32-bit checksum (addition with a 32 bit …\nBit 11 - If set, the result appears inverted (bitwise …\nBit 11 - If set, the result appears inverted (bitwise …\nBit 10 - If set, the result appears bit-reversed when …\nBit 10 - If set, the result appears bit-reversed when …\nCalculate a simple 32-bit checksum (addition with a 32 bit …\nGet enumerated values variant\nRegister <code>SNIFF_DATA</code> reader\nData accumulator for sniff hardware Write an initial seed …\nRegister <code>SNIFF_DATA</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>TIMER0</code> reader\nPacing (X/Y) Fractional Timer The pacing timer produces …\nRegister <code>TIMER0</code> writer\nField <code>X</code> reader - Pacing Timer Dividend. Specifies the X …\nField <code>X</code> writer - Pacing Timer Dividend. Specifies the X …\nField <code>Y</code> reader - Pacing Timer Divisor. Specifies the Y …\nField <code>Y</code> writer - Pacing Timer Divisor. Specifies the Y …\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nRegister <code>TIMER1</code> reader\nPacing (X/Y) Fractional Timer The pacing timer produces …\nRegister <code>TIMER1</code> writer\nField <code>X</code> reader - Pacing Timer Dividend. Specifies the X …\nField <code>X</code> writer - Pacing Timer Dividend. Specifies the X …\nField <code>Y</code> reader - Pacing Timer Divisor. Specifies the Y …\nField <code>Y</code> writer - Pacing Timer Divisor. Specifies the Y …\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nRegister <code>TIMER2</code> reader\nPacing (X/Y) Fractional Timer The pacing timer produces …\nRegister <code>TIMER2</code> writer\nField <code>X</code> reader - Pacing Timer Dividend. Specifies the X …\nField <code>X</code> writer - Pacing Timer Dividend. Specifies the X …\nField <code>Y</code> reader - Pacing Timer Divisor. Specifies the Y …\nField <code>Y</code> writer - Pacing Timer Divisor. Specifies the Y …\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nRegister <code>TIMER3</code> reader\nPacing (X/Y) Fractional Timer The pacing timer produces …\nRegister <code>TIMER3</code> writer\nField <code>X</code> reader - Pacing Timer Dividend. Specifies the X …\nField <code>X</code> writer - Pacing Timer Dividend. Specifies the X …\nField <code>Y</code> reader - Pacing Timer Divisor. Specifies the Y …\nField <code>Y</code> writer - Pacing Timer Divisor. Specifies the Y …\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 16:31 - Pacing Timer Dividend. Specifies the X value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nBits 0:15 - Pacing Timer Divisor. Specifies the Y value …\nBit-wise field reader\nBit-wise write field proxy\nBit-wise write field proxy\nBit-wise write field proxy\nBit-wise write field proxy\nBit-wise write field proxy\nBit-wise write field proxy\nBit-wise write field proxy\nField reader.\nRaw field type\nWrite field Proxy with unsafe <code>bits</code>\nWrite field Proxy with safe <code>bits</code>\nSpecifies the register bits that are not changed if you …\nRegister reader.\nReset value of the register.\nRaw register type (<code>u8</code>, <code>u16</code>, <code>u32</code>, …)\nTrait implemented by readable registers to enable the <code>read</code> …\nThis structure provides volatile access to registers.\nRaw register type\nReset value of the register.\nRaw register type (<code>u8</code>, <code>u16</code>, <code>u32</code>, …).\nRaw field type (<code>u8</code>, <code>u16</code>, <code>u32</code>, …).\nRegister writer.\nField width\nField width\nField width\nField width\nField width\nField width\nField width\nField width\nField width\nTrait implemented by writeable registers.\nSpecifies the register bits that are not changed if you …\nReturns the underlying memory address of register.\nValue of the field as raw bits.\nWrites bit to the field\nWrites bit to the field\nWrites bit to the field\nWrites bit to the field\nWrites bit to the field\nWrites bit to the field\nWrites bit to the field\nReturns <code>true</code> if the bit is clear (0).\nReturns <code>true</code> if the bit is set (1).\nReads raw bits from register.\nReads raw bits from field.\nWrites raw bits to the field\nWrites raw bits to the field\nClears the field bit\nClears the field bit\nClears the field bit by passing one\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nMask for bits of width <code>WI</code>\nModifies the contents of the register by reading and then …\nField offset\nField offset\nField offset\nField offset\nField offset\nField offset\nField offset\nField offset\nField offset\nMask for bits of width 1\nReads the contents of a <code>Readable</code> register.\nWrites the reset value to <code>Writable</code> register.\nReset value of the register.\nSets the field bit\nSets the field bit\nSets the field bit by passing zero\nToggle the field bit by passing one\nToggle the field bit by passing zero\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nWrites <code>variant</code> to the field\nField width\nField width\nField width\nField width\nField width\nField width\nField width\nField width\nField width\nWrites bits to a <code>Writable</code> register.\nWrites 0 to a <code>Writable</code> register.\nIC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK …\nIC_CLR_ACTIVITY (r) register accessor: Clear ACTIVITY …\nIC_CLR_GEN_CALL (r) register accessor: Clear GEN_CALL …\nIC_CLR_INTR (r) register accessor: Clear Combined and …\nIC_CLR_RD_REQ (r) register accessor: Clear RD_REQ …\nIC_CLR_RESTART_DET (r) register accessor: Clear …\nIC_CLR_RX_DONE (r) register accessor: Clear RX_DONE …\nIC_CLR_RX_OVER (r) register accessor: Clear RX_OVER …\nIC_CLR_RX_UNDER (r) register accessor: Clear RX_UNDER …\nIC_CLR_START_DET (r) register accessor: Clear START_DET …\nIC_CLR_STOP_DET (r) register accessor: Clear STOP_DET …\nIC_CLR_TX_ABRT (r) register accessor: Clear TX_ABRT …\nIC_CLR_TX_OVER (r) register accessor: Clear TX_OVER …\nIC_COMP_PARAM_1 (r) register accessor: Component Parameter …\nIC_COMP_TYPE (r) register accessor: I2C Component Type …\nIC_COMP_VERSION (r) register accessor: I2C Component …\nIC_CON (rw) register accessor: I2C Control Register. This …\nIC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer …\nIC_DMA_CR (rw) register accessor: DMA Control Register\nIC_DMA_RDLR (rw) register accessor: I2C Receive Data Level …\nIC_DMA_TDLR (rw) register accessor: DMA Transmit Data …\nIC_ENABLE (rw) register accessor: I2C Enable Register\nIC_ENABLE_STATUS (r) register accessor: I2C Enable Status …\nIC_FS_SCL_HCNT (rw) register accessor: Fast Mode or Fast …\nIC_FS_SCL_LCNT (rw) register accessor: Fast Mode or Fast …\nIC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ …\nIC_INTR_MASK (rw) register accessor: I2C Interrupt Mask …\nIC_INTR_STAT (r) register accessor: I2C Interrupt Status …\nIC_RAW_INTR_STAT (r) register accessor: I2C Raw Interrupt …\nIC_RXFLR (r) register accessor: I2C Receive FIFO Level …\nIC_RX_TL (rw) register accessor: I2C Receive FIFO …\nIC_SAR (rw) register accessor: I2C Slave Address Register\nIC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time …\nIC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register\nIC_SLV_DATA_NACK_ONLY (rw) register accessor: Generate …\nIC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C …\nIC_SS_SCL_LCNT (rw) register accessor: Standard Speed I2C …\nIC_STATUS (r) register accessor: I2C Status Register\nIC_TAR (rw) register accessor: I2C Target Address Register\nIC_TXFLR (r) register accessor: I2C Transmit FIFO Level …\nIC_TX_ABRT_SOURCE (r) register accessor: I2C Transmit …\nIC_TX_TL (rw) register accessor: I2C Transmit FIFO …\nRegister block\nReturns the argument unchanged.\nI2C ACK General Call Register\n0x98 - I2C ACK General Call Register\nClear ACTIVITY Interrupt Register\n0x5c - Clear ACTIVITY Interrupt Register\nClear GEN_CALL Interrupt Register\n0x68 - Clear GEN_CALL Interrupt Register\nClear Combined and Individual Interrupt Register\n0x40 - Clear Combined and Individual Interrupt Register\nClear RD_REQ Interrupt Register\n0x50 - Clear RD_REQ Interrupt Register\nClear RESTART_DET Interrupt Register\n0xa8 - Clear RESTART_DET Interrupt Register\nClear RX_DONE Interrupt Register\n0x58 - Clear RX_DONE Interrupt Register\nClear RX_OVER Interrupt Register\n0x48 - Clear RX_OVER Interrupt Register\nClear RX_UNDER Interrupt Register\n0x44 - Clear RX_UNDER Interrupt Register\nClear START_DET Interrupt Register\n0x64 - Clear START_DET Interrupt Register\nClear STOP_DET Interrupt Register\n0x60 - Clear STOP_DET Interrupt Register\nClear TX_ABRT Interrupt Register\n0x54 - Clear TX_ABRT Interrupt Register\nClear TX_OVER Interrupt Register\n0x4c - Clear TX_OVER Interrupt Register\nComponent Parameter Register 1\n0xf4 - Component Parameter Register 1\nI2C Component Type Register\n0xfc - I2C Component Type Register\nI2C Component Version Register\n0xf8 - I2C Component Version Register\nI2C Control Register. This register can be written only …\n0x00 - I2C Control Register. This register can be written …\nI2C Rx/Tx Data Buffer and Command Register; this is the …\n0x10 - I2C Rx/Tx Data Buffer and Command Register; this is …\nDMA Control Register\n0x88 - DMA Control Register\nI2C Receive Data Level Register\n0x90 - I2C Receive Data Level Register\nDMA Transmit Data Level Register\n0x8c - DMA Transmit Data Level Register\nI2C Enable Register\n0x6c - I2C Enable Register\nI2C Enable Status Register\n0x9c - I2C Enable Status Register\nFast Mode or Fast Mode Plus I2C Clock SCL High Count …\n0x1c - Fast Mode or Fast Mode Plus I2C Clock SCL High …\nFast Mode or Fast Mode Plus I2C Clock SCL Low Count …\n0x20 - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count …\nI2C SS, FS or FM+ spike suppression limit\n0xa0 - I2C SS, FS or FM+ spike suppression limit\nI2C Interrupt Mask Register.\n0x30 - I2C Interrupt Mask Register.\nI2C Interrupt Status Register\n0x2c - I2C Interrupt Status Register\nI2C Raw Interrupt Status Register\n0x34 - I2C Raw Interrupt Status Register\nI2C Receive FIFO Threshold Register\n0x38 - I2C Receive FIFO Threshold Register\nI2C Receive FIFO Level Register This register contains the …\n0x78 - I2C Receive FIFO Level Register This register …\nI2C Slave Address Register\n0x08 - I2C Slave Address Register\nI2C SDA Hold Time Length Register\n0x7c - I2C SDA Hold Time Length Register\nI2C SDA Setup Register\n0x94 - I2C SDA Setup Register\nGenerate Slave Data NACK Register\n0x84 - Generate Slave Data NACK Register\nStandard Speed I2C Clock SCL High Count Register\n0x14 - Standard Speed I2C Clock SCL High Count Register\nStandard Speed I2C Clock SCL Low Count Register\n0x18 - Standard Speed I2C Clock SCL Low Count Register\nI2C Status Register\n0x70 - I2C Status Register\nI2C Target Address Register\n0x04 - I2C Target Address Register\nI2C Transmit Abort Source Register\n0x80 - I2C Transmit Abort Source Register\nI2C Transmit FIFO Threshold Register\n0x3c - I2C Transmit FIFO Threshold Register\nI2C Transmit FIFO Level Register This register contains …\n0x74 - I2C Transmit FIFO Level Register This register …\nCalls <code>U::from(self)</code>.\nACK General Call. When set to 1, DW_apb_i2c responds with …\nField <code>ACK_GEN_CALL</code> reader - ACK General Call. When set to …\nField <code>ACK_GEN_CALL</code> writer - ACK General Call. When set to …\n0: Generate NACK for a General Call\n1: Generate ACK for a General Call\nI2C ACK General Call Register\nRegister <code>IC_ACK_GENERAL_CALL</code> reader\nRegister <code>IC_ACK_GENERAL_CALL</code> writer\nBit 0 - ACK General Call. When set to 1, DW_apb_i2c …\nBit 0 - ACK General Call. When set to 1, DW_apb_i2c …\nWrites raw bits to the register.\nGenerate NACK for a General Call\nGenerate ACK for a General Call\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nGenerate NACK for a General Call\nGenerate ACK for a General Call\nGet enumerated values variant\nField <code>CLR_ACTIVITY</code> reader - Reading this register clears …\nClear ACTIVITY Interrupt Register\nRegister <code>IC_CLR_ACTIVITY</code> reader\nBit 0 - Reading this register clears the ACTIVITY …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_GEN_CALL</code> reader - Read this register to clear …\nClear GEN_CALL Interrupt Register\nRegister <code>IC_CLR_GEN_CALL</code> reader\nBit 0 - Read this register to clear the GEN_CALL interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_INTR</code> reader - Read this register to clear the …\nClear Combined and Individual Interrupt Register\nRegister <code>IC_CLR_INTR</code> reader\nBit 0 - Read this register to clear the combined …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_RD_REQ</code> reader - Read this register to clear the …\nClear RD_REQ Interrupt Register\nRegister <code>IC_CLR_RD_REQ</code> reader\nBit 0 - Read this register to clear the RD_REQ interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_RESTART_DET</code> reader - Read this register to clear …\nClear RESTART_DET Interrupt Register\nRegister <code>IC_CLR_RESTART_DET</code> reader\nBit 0 - Read this register to clear the RESTART_DET …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_RX_DONE</code> reader - Read this register to clear the …\nClear RX_DONE Interrupt Register\nRegister <code>IC_CLR_RX_DONE</code> reader\nBit 0 - Read this register to clear the RX_DONE interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_RX_OVER</code> reader - Read this register to clear the …\nClear RX_OVER Interrupt Register\nRegister <code>IC_CLR_RX_OVER</code> reader\nBit 0 - Read this register to clear the RX_OVER interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_RX_UNDER</code> reader - Read this register to clear …\nClear RX_UNDER Interrupt Register\nRegister <code>IC_CLR_RX_UNDER</code> reader\nBit 0 - Read this register to clear the RX_UNDER interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_START_DET</code> reader - Read this register to clear …\nClear START_DET Interrupt Register\nRegister <code>IC_CLR_START_DET</code> reader\nBit 0 - Read this register to clear the START_DET …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_STOP_DET</code> reader - Read this register to clear …\nClear STOP_DET Interrupt Register\nRegister <code>IC_CLR_STOP_DET</code> reader\nBit 0 - Read this register to clear the STOP_DET interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_TX_ABRT</code> reader - Read this register to clear the …\nClear TX_ABRT Interrupt Register\nRegister <code>IC_CLR_TX_ABRT</code> reader\nBit 0 - Read this register to clear the TX_ABRT interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>CLR_TX_OVER</code> reader - Read this register to clear the …\nClear TX_OVER Interrupt Register\nRegister <code>IC_CLR_TX_OVER</code> reader\nBit 0 - Read this register to clear the TX_OVER interrupt …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ADD_ENCODED_PARAMS</code> reader - Encoded parameters not …\nField <code>APB_DATA_WIDTH</code> reader - APB data bus width is 32 bits\nField <code>HAS_DMA</code> reader - DMA handshaking signals are enabled\nField <code>HC_COUNT_VALUES</code> reader - Programmable count values …\nComponent Parameter Register 1\nField <code>INTR_IO</code> reader - COMBINED Interrupt outputs\nField <code>MAX_SPEED_MODE</code> reader - MAX SPEED MODE = FAST MODE\nRegister <code>IC_COMP_PARAM_1</code> reader\nField <code>RX_BUFFER_DEPTH</code> reader - RX Buffer Depth = 16\nField <code>TX_BUFFER_DEPTH</code> reader - TX Buffer Depth = 16\nBit 7 - Encoded parameters not visible\nBits 0:1 - APB data bus width is 32 bits\nReturns the argument unchanged.\nBit 6 - DMA handshaking signals are enabled\nBit 4 - Programmable count values for each mode.\nCalls <code>U::from(self)</code>.\nBit 5 - COMBINED Interrupt outputs\nBits 2:3 - MAX SPEED MODE = FAST MODE\nBits 8:15 - RX Buffer Depth = 16\nBits 16:23 - TX Buffer Depth = 16\nField <code>IC_COMP_TYPE</code> reader - Designware Component Type …\nI2C Component Type Register\nRegister <code>IC_COMP_TYPE</code> reader\nReturns the argument unchanged.\nBits 0:31 - Designware Component Type number = …\nCalls <code>U::from(self)</code>.\nField <code>IC_COMP_VERSION</code> reader -\nI2C Component Version Register\nRegister <code>IC_COMP_VERSION</code> reader\nReturns the argument unchanged.\nBits 0:31\nCalls <code>U::from(self)</code>.\n1: Slave 10Bit addressing\n1: Master 10Bit addressing mode\n0: Slave 7Bit addressing\n0: Master 7Bit addressing mode\n0: Master mode is disabled\n0: Master restart disabled\n0: slave issues STOP_DET intr always\n0: Default behaviour of TX_EMPTY interrupt\n0: Overflow when RX_FIFO is full\n1: Master mode is enabled\n1: Master restart enabled\n1: slave issues STOP_DET intr only if addressed\n1: Controlled generation of TX_EMPTY interrupt\n1: Hold bus when RX_FIFO is full\n2: Fast or Fast Plus mode of operation\n3: High Speed mode of operation\nControls whether the DW_apb_i2c starts its transfers in 7- …\nField <code>IC_10BITADDR_MASTER</code> reader - Controls whether the …\nField <code>IC_10BITADDR_MASTER</code> writer - Controls whether the …\nWhen acting as a slave, this bit controls whether the …\nField <code>IC_10BITADDR_SLAVE</code> reader - When acting as a slave, …\nField <code>IC_10BITADDR_SLAVE</code> writer - When acting as a slave, …\nI2C Control Register. This register can be written only …\nDetermines whether RESTART conditions may be sent when …\nField <code>IC_RESTART_EN</code> reader - Determines whether RESTART …\nField <code>IC_RESTART_EN</code> writer - Determines whether RESTART …\nThis bit controls whether I2C has its slave disabled, …\nField <code>IC_SLAVE_DISABLE</code> reader - This bit controls whether …\nField <code>IC_SLAVE_DISABLE</code> writer - This bit controls whether …\nThis bit controls whether the DW_apb_i2c master is enabled.\nField <code>MASTER_MODE</code> reader - This bit controls whether the …\nField <code>MASTER_MODE</code> writer - This bit controls whether the …\nRegister <code>IC_CON</code> reader\nThis bit controls whether DW_apb_i2c should hold the bus …\nField <code>RX_FIFO_FULL_HLD_CTRL</code> reader - This bit controls …\nField <code>RX_FIFO_FULL_HLD_CTRL</code> writer - This bit controls …\n1: Slave mode is disabled\n0: Slave mode is enabled\nThese bits control at which speed the DW_apb_i2c operates; …\nField <code>SPEED</code> reader - These bits control at which speed the …\nField <code>SPEED</code> writer - These bits control at which speed the …\n1: Standard Speed mode of operation\nIn slave mode: - 1’b1: issues the STOP_DET interrupt …\nField <code>STOP_DET_IFADDRESSED</code> reader - In slave mode: - 1’…\nField <code>STOP_DET_IFADDRESSED</code> writer - In slave mode: - 1’…\nField <code>STOP_DET_IF_MASTER_ACTIVE</code> reader - Master issues the …\nThis bit controls the generation of the TX_EMPTY …\nField <code>TX_EMPTY_CTRL</code> reader - This bit controls the …\nField <code>TX_EMPTY_CTRL</code> writer - This bit controls the …\nRegister <code>IC_CON</code> writer\nSlave 10Bit addressing\nMaster 10Bit addressing mode\nSlave 7Bit addressing\nMaster 7Bit addressing mode\nWrites raw bits to the register.\nMaster mode is disabled\nMaster restart disabled\nslave issues STOP_DET intr always\nDefault behaviour of TX_EMPTY interrupt\nOverflow when RX_FIFO is full\nMaster mode is enabled\nMaster restart enabled\nslave issues STOP_DET intr only if addressed\nControlled generation of TX_EMPTY interrupt\nHold bus when RX_FIFO is full\nFast or Fast Plus mode of operation\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nHigh Speed mode of operation\nBit 4 - Controls whether the DW_apb_i2c starts its …\nBit 4 - Controls whether the DW_apb_i2c starts its …\nBit 3 - When acting as a slave, this bit controls whether …\nBit 3 - When acting as a slave, this bit controls whether …\nBit 5 - Determines whether RESTART conditions may be sent …\nBit 5 - Determines whether RESTART conditions may be sent …\nBit 6 - This bit controls whether I2C has its slave …\nBit 6 - This bit controls whether I2C has its slave …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSlave 10Bit addressing\nMaster 10Bit addressing mode\nSlave 7Bit addressing\nMaster 7Bit addressing mode\nMaster mode is disabled\nMaster restart disabled\nslave issues STOP_DET intr always\nDefault behaviour of TX_EMPTY interrupt\nOverflow when RX_FIFO is full\nMaster mode is enabled\nMaster restart enabled\nslave issues STOP_DET intr only if addressed\nControlled generation of TX_EMPTY interrupt\nHold bus when RX_FIFO is full\nFast or Fast Plus mode of operation\nHigh Speed mode of operation\nSlave mode is disabled\nSlave mode is enabled\nStandard Speed mode of operation\nBit 0 - This bit controls whether the DW_apb_i2c master is …\nBit 0 - This bit controls whether the DW_apb_i2c master is …\nBit 9 - This bit controls whether DW_apb_i2c should hold …\nBit 9 - This bit controls whether DW_apb_i2c should hold …\nSlave mode is disabled\nSlave mode is enabled\nBits 1:2 - These bits control at which speed the …\nBits 1:2 - These bits control at which speed the …\nStandard Speed mode of operation\nBit 10 - Master issues the STOP_DET interrupt irrespective …\nBit 7 - In slave mode: - 1’b1: issues the STOP_DET …\nBit 7 - In slave mode: - 1’b1: issues the STOP_DET …\nBit 8 - This bit controls the generation of the TX_EMPTY …\nBit 8 - This bit controls the generation of the TX_EMPTY …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\n1: Non sequential data byte received\nThis bit controls whether a read or a write is performed. …\nField <code>CMD</code> reader - This bit controls whether a read or a …\nField <code>CMD</code> writer - This bit controls whether a read or a …\nField <code>DAT</code> reader - This register contains the data to be …\nField <code>DAT</code> writer - This register contains the data to be …\n0: Don’t Issue STOP after this command\n0: Don’t Issue RESTART before this command\n1: Issue STOP after this command\n1: Issue RESTART before this command\nIndicates the first data byte received after the address …\nField <code>FIRST_DATA_BYTE</code> reader - Indicates the first data …\nI2C Rx/Tx Data Buffer and Command Register; this is the …\n0: Sequential data byte received\nRegister <code>IC_DATA_CMD</code> reader\n1: Master Read Command\nThis bit controls whether a RESTART is issued before the …\nField <code>RESTART</code> reader - This bit controls whether a RESTART …\nField <code>RESTART</code> writer - This bit controls whether a RESTART …\nThis bit controls whether a STOP is issued after the byte …\nField <code>STOP</code> reader - This bit controls whether a STOP is …\nField <code>STOP</code> writer - This bit controls whether a STOP is …\nRegister <code>IC_DATA_CMD</code> writer\n0: Master Write Command\nWrites raw bits to the register.\nBit 8 - This bit controls whether a read or a write is …\nBit 8 - This bit controls whether a read or a write is …\nBits 0:7 - This register contains the data to be …\nBits 0:7 - This register contains the data to be …\nDon’t Issue STOP after this command\nDon’t Issue RESTART before this command\nIssue STOP after this command\nIssue RESTART before this command\nBit 11 - Indicates the first data byte received after the …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nNon sequential data byte received\nDon’t Issue STOP after this command\nDon’t Issue RESTART before this command\nIssue STOP after this command\nIssue RESTART before this command\nSequential data byte received\nMaster Read Command\nMaster Write Command\nMaster Read Command\nBit 10 - This bit controls whether a RESTART is issued …\nBit 10 - This bit controls whether a RESTART is issued …\nBit 9 - This bit controls whether a STOP is issued after …\nBit 9 - This bit controls whether a STOP is issued after …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nMaster Write Command\n0: Receive FIFO DMA channel disabled\n0: transmit FIFO DMA channel disabled\n1: Receive FIFO DMA channel enabled\n1: Transmit FIFO DMA channel enabled\nDMA Control Register\nRegister <code>IC_DMA_CR</code> reader\nReceive DMA Enable. This bit enables/disables the receive …\nField <code>RDMAE</code> reader - Receive DMA Enable. This bit …\nField <code>RDMAE</code> writer - Receive DMA Enable. This bit …\nTransmit DMA Enable. This bit enables/disables the …\nField <code>TDMAE</code> reader - Transmit DMA Enable. This bit …\nField <code>TDMAE</code> writer - Transmit DMA Enable. This bit …\nRegister <code>IC_DMA_CR</code> writer\nWrites raw bits to the register.\nReceive FIFO DMA channel disabled\ntransmit FIFO DMA channel disabled\nReceive FIFO DMA channel enabled\nTransmit FIFO DMA channel enabled\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nReceive FIFO DMA channel disabled\ntransmit FIFO DMA channel disabled\nReceive FIFO DMA channel enabled\nTransmit FIFO DMA channel enabled\nBit 0 - Receive DMA Enable. This bit enables/disables the …\nBit 0 - Receive DMA Enable. This bit enables/disables the …\nBit 1 - Transmit DMA Enable. This bit enables/disables the …\nBit 1 - Transmit DMA Enable. This bit enables/disables the …\nGet enumerated values variant\nGet enumerated values variant\nField <code>DMARDL</code> reader - Receive Data Level. This bit field …\nField <code>DMARDL</code> writer - Receive Data Level. This bit field …\nI2C Receive Data Level Register\nRegister <code>IC_DMA_RDLR</code> reader\nRegister <code>IC_DMA_RDLR</code> writer\nWrites raw bits to the register.\nBits 0:3 - Receive Data Level. This bit field controls the …\nBits 0:3 - Receive Data Level. This bit field controls the …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DMATDL</code> reader - Transmit Data Level. This bit field …\nField <code>DMATDL</code> writer - Transmit Data Level. This bit field …\nDMA Transmit Data Level Register\nRegister <code>IC_DMA_TDLR</code> reader\nRegister <code>IC_DMA_TDLR</code> writer\nWrites raw bits to the register.\nBits 0:3 - Transmit Data Level. This bit field controls …\nBits 0:3 - Transmit Data Level. This bit field controls …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nWhen set, the controller initiates the transfer abort. - …\nField <code>ABORT</code> reader - When set, the controller initiates …\nField <code>ABORT</code> writer - When set, the controller initiates …\n1: Tx Command execution blocked\n0: ABORT operation not in progress\n0: I2C is disabled\n1: I2C is enabled\n1: ABORT operation in progress\nControls whether the DW_apb_i2c is enabled. - 0: Disables …\nField <code>ENABLE</code> reader - Controls whether the DW_apb_i2c is …\nField <code>ENABLE</code> writer - Controls whether the DW_apb_i2c is …\nI2C Enable Register\n0: Tx Command execution not blocked\nRegister <code>IC_ENABLE</code> reader\nIn Master mode: - 1’b1: Blocks the transmission of data …\nField <code>TX_CMD_BLOCK</code> reader - In Master mode: - 1’b1: …\nField <code>TX_CMD_BLOCK</code> writer - In Master mode: - 1’b1: …\nRegister <code>IC_ENABLE</code> writer\nBit 1 - When set, the controller initiates the transfer …\nBit 1 - When set, the controller initiates the transfer …\nWrites raw bits to the register.\nTx Command execution blocked\nABORT operation not in progress\nI2C is disabled\nBit 0 - Controls whether the DW_apb_i2c is enabled. - 0: …\nBit 0 - Controls whether the DW_apb_i2c is enabled. - 0: …\nI2C is enabled\nABORT operation in progress\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nTx Command execution blocked\nABORT operation not in progress\nI2C is disabled\nI2C is enabled\nABORT operation in progress\nTx Command execution not blocked\nTx Command execution not blocked\nBit 2 - In Master mode: - 1’b1: Blocks the transmission …\nBit 2 - In Master mode: - 1’b1: Blocks the transmission …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\n1: Slave is disabled when it is active\n1: Slave RX Data is lost\n0: I2C disabled\n1: I2C enabled\nI2C Enable Status Register\nic_en Status. This bit always reflects the value driven on …\nField <code>IC_EN</code> reader - ic_en Status. This bit always …\n0: Slave is disabled when it is idle\n0: Slave RX Data is not lost\nRegister <code>IC_ENABLE_STATUS</code> reader\nSlave Disabled While Busy (Transmit, Receive). This bit …\nField <code>SLV_DISABLED_WHILE_BUSY</code> reader - Slave Disabled …\nSlave Received Data Lost. This bit indicates if a …\nField <code>SLV_RX_DATA_LOST</code> reader - Slave Received Data Lost. …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 0 - ic_en Status. This bit always reflects the value …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSlave is disabled when it is active\nSlave RX Data is lost\nI2C disabled\nI2C enabled\nSlave is disabled when it is idle\nSlave RX Data is not lost\nBit 1 - Slave Disabled While Busy (Transmit, Receive). …\nBit 2 - Slave Received Data Lost. This bit indicates if a …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nField <code>IC_FS_SCL_HCNT</code> reader - This register must be set …\nFast Mode or Fast Mode Plus I2C Clock SCL High Count …\nField <code>IC_FS_SCL_HCNT</code> writer - This register must be set …\nRegister <code>IC_FS_SCL_HCNT</code> reader\nRegister <code>IC_FS_SCL_HCNT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - This register must be set before any I2C bus …\nBits 0:15 - This register must be set before any I2C bus …\nCalls <code>U::from(self)</code>.\nField <code>IC_FS_SCL_LCNT</code> reader - This register must be set …\nFast Mode or Fast Mode Plus I2C Clock SCL Low Count …\nField <code>IC_FS_SCL_LCNT</code> writer - This register must be set …\nRegister <code>IC_FS_SCL_LCNT</code> reader\nRegister <code>IC_FS_SCL_LCNT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - This register must be set before any I2C bus …\nBits 0:15 - This register must be set before any I2C bus …\nCalls <code>U::from(self)</code>.\nField <code>IC_FS_SPKLEN</code> reader - This register must be set …\nI2C SS, FS or FM+ spike suppression limit\nField <code>IC_FS_SPKLEN</code> writer - This register must be set …\nRegister <code>IC_FS_SPKLEN</code> reader\nRegister <code>IC_FS_SPKLEN</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:7 - This register must be set before any I2C bus …\nBits 0:7 - This register must be set before any I2C bus …\nCalls <code>U::from(self)</code>.\n1: RX_UNDER interrupt is unmasked\n1: RX_OVER interrupt is unmasked\n1: RX_FULL interrupt is unmasked\n1: TX_OVER interrupt is unmasked\n1: TX_EMPTY interrupt is unmasked\n1: RD_REQ interrupt is unmasked\n1: TX_ABORT interrupt is unmasked\n1: RX_DONE interrupt is unmasked\n1: ACTIVITY interrupt is unmasked\n1: STOP_DET interrupt is unmasked\n1: START_DET interrupt is unmasked\n1: GEN_CALL interrupt is unmasked\n1: RESTART_DET interrupt is unmasked\n0: RX_UNDER interrupt is masked\n0: RX_OVER interrupt is masked\n0: RX_FULL interrupt is masked\n0: TX_OVER interrupt is masked\n0: TX_EMPTY interrupt is masked\n0: RD_REQ interrupt is masked\n0: TX_ABORT interrupt is masked\n0: RX_DONE interrupt is masked\n0: ACTIVITY interrupt is masked\n0: STOP_DET interrupt is masked\n0: START_DET interrupt is masked\n0: GEN_CALL interrupt is masked\n0: RESTART_DET interrupt is masked\nI2C Interrupt Mask Register.\nThis bit masks the R_ACTIVITY interrupt in IC_INTR_STAT …\nField <code>M_ACTIVITY</code> reader - This bit masks the R_ACTIVITY …\nField <code>M_ACTIVITY</code> writer - This bit masks the R_ACTIVITY …\nThis bit masks the R_GEN_CALL interrupt in IC_INTR_STAT …\nField <code>M_GEN_CALL</code> reader - This bit masks the R_GEN_CALL …\nField <code>M_GEN_CALL</code> writer - This bit masks the R_GEN_CALL …\nThis bit masks the R_RD_REQ interrupt in IC_INTR_STAT …\nField <code>M_RD_REQ</code> reader - This bit masks the R_RD_REQ …\nField <code>M_RD_REQ</code> writer - This bit masks the R_RD_REQ …\nThis bit masks the R_RESTART_DET interrupt in IC_INTR_STAT …\nField <code>M_RESTART_DET</code> reader - This bit masks the …\nField <code>M_RESTART_DET</code> writer - This bit masks the …\nThis bit masks the R_RX_DONE interrupt in IC_INTR_STAT …\nField <code>M_RX_DONE</code> reader - This bit masks the R_RX_DONE …\nField <code>M_RX_DONE</code> writer - This bit masks the R_RX_DONE …\nThis bit masks the R_RX_FULL interrupt in IC_INTR_STAT …\nField <code>M_RX_FULL</code> reader - This bit masks the R_RX_FULL …\nField <code>M_RX_FULL</code> writer - This bit masks the R_RX_FULL …\nThis bit masks the R_RX_OVER interrupt in IC_INTR_STAT …\nField <code>M_RX_OVER</code> reader - This bit masks the R_RX_OVER …\nField <code>M_RX_OVER</code> writer - This bit masks the R_RX_OVER …\nThis bit masks the R_RX_UNDER interrupt in IC_INTR_STAT …\nField <code>M_RX_UNDER</code> reader - This bit masks the R_RX_UNDER …\nField <code>M_RX_UNDER</code> writer - This bit masks the R_RX_UNDER …\nThis bit masks the R_START_DET interrupt in IC_INTR_STAT …\nField <code>M_START_DET</code> reader - This bit masks the R_START_DET …\nField <code>M_START_DET</code> writer - This bit masks the R_START_DET …\nThis bit masks the R_STOP_DET interrupt in IC_INTR_STAT …\nField <code>M_STOP_DET</code> reader - This bit masks the R_STOP_DET …\nField <code>M_STOP_DET</code> writer - This bit masks the R_STOP_DET …\nThis bit masks the R_TX_ABRT interrupt in IC_INTR_STAT …\nField <code>M_TX_ABRT</code> reader - This bit masks the R_TX_ABRT …\nField <code>M_TX_ABRT</code> writer - This bit masks the R_TX_ABRT …\nThis bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT …\nField <code>M_TX_EMPTY</code> reader - This bit masks the R_TX_EMPTY …\nField <code>M_TX_EMPTY</code> writer - This bit masks the R_TX_EMPTY …\nThis bit masks the R_TX_OVER interrupt in IC_INTR_STAT …\nField <code>M_TX_OVER</code> reader - This bit masks the R_TX_OVER …\nField <code>M_TX_OVER</code> writer - This bit masks the R_TX_OVER …\nRegister <code>IC_INTR_MASK</code> reader\nRegister <code>IC_INTR_MASK</code> writer\nWrites raw bits to the register.\nRX_UNDER interrupt is unmasked\nRX_OVER interrupt is unmasked\nRX_FULL interrupt is unmasked\nTX_OVER interrupt is unmasked\nTX_EMPTY interrupt is unmasked\nRD_REQ interrupt is unmasked\nTX_ABORT interrupt is unmasked\nRX_DONE interrupt is unmasked\nACTIVITY interrupt is unmasked\nSTOP_DET interrupt is unmasked\nSTART_DET interrupt is unmasked\nGEN_CALL interrupt is unmasked\nRESTART_DET interrupt is unmasked\nRX_UNDER interrupt is masked\nRX_OVER interrupt is masked\nRX_FULL interrupt is masked\nTX_OVER interrupt is masked\nTX_EMPTY interrupt is masked\nRD_REQ interrupt is masked\nTX_ABORT interrupt is masked\nRX_DONE interrupt is masked\nACTIVITY interrupt is masked\nSTOP_DET interrupt is masked\nSTART_DET interrupt is masked\nGEN_CALL interrupt is masked\nRESTART_DET interrupt is masked\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nRX_UNDER interrupt is unmasked\nRX_OVER interrupt is unmasked\nRX_FULL interrupt is unmasked\nTX_OVER interrupt is unmasked\nTX_EMPTY interrupt is unmasked\nRD_REQ interrupt is unmasked\nTX_ABORT interrupt is unmasked\nRX_DONE interrupt is unmasked\nACTIVITY interrupt is unmasked\nSTOP_DET interrupt is unmasked\nSTART_DET interrupt is unmasked\nGEN_CALL interrupt is unmasked\nRESTART_DET interrupt is unmasked\nRX_UNDER interrupt is masked\nRX_OVER interrupt is masked\nRX_FULL interrupt is masked\nTX_OVER interrupt is masked\nTX_EMPTY interrupt is masked\nRD_REQ interrupt is masked\nTX_ABORT interrupt is masked\nRX_DONE interrupt is masked\nACTIVITY interrupt is masked\nSTOP_DET interrupt is masked\nSTART_DET interrupt is masked\nGEN_CALL interrupt is masked\nRESTART_DET interrupt is masked\nBit 8 - This bit masks the R_ACTIVITY interrupt in …\nBit 8 - This bit masks the R_ACTIVITY interrupt in …\nBit 11 - This bit masks the R_GEN_CALL interrupt in …\nBit 11 - This bit masks the R_GEN_CALL interrupt in …\nBit 5 - This bit masks the R_RD_REQ interrupt in …\nBit 5 - This bit masks the R_RD_REQ interrupt in …\nBit 12 - This bit masks the R_RESTART_DET interrupt in …\nBit 12 - This bit masks the R_RESTART_DET interrupt in …\nBit 7 - This bit masks the R_RX_DONE interrupt in …\nBit 7 - This bit masks the R_RX_DONE interrupt in …\nBit 2 - This bit masks the R_RX_FULL interrupt in …\nBit 2 - This bit masks the R_RX_FULL interrupt in …\nBit 1 - This bit masks the R_RX_OVER interrupt in …\nBit 1 - This bit masks the R_RX_OVER interrupt in …\nBit 0 - This bit masks the R_RX_UNDER interrupt in …\nBit 0 - This bit masks the R_RX_UNDER interrupt in …\nBit 10 - This bit masks the R_START_DET interrupt in …\nBit 10 - This bit masks the R_START_DET interrupt in …\nBit 9 - This bit masks the R_STOP_DET interrupt in …\nBit 9 - This bit masks the R_STOP_DET interrupt in …\nBit 6 - This bit masks the R_TX_ABRT interrupt in …\nBit 6 - This bit masks the R_TX_ABRT interrupt in …\nBit 4 - This bit masks the R_TX_EMPTY interrupt in …\nBit 4 - This bit masks the R_TX_EMPTY interrupt in …\nBit 3 - This bit masks the R_TX_OVER interrupt in …\nBit 3 - This bit masks the R_TX_OVER interrupt in …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\n1: RX_UNDER interrupt is active\n1: R_RX_OVER interrupt is active\n1: R_RX_FULL interrupt is active\n1: R_TX_OVER interrupt is active\n1: R_TX_EMPTY interrupt is active\n1: R_RD_REQ interrupt is active\n1: R_TX_ABRT interrupt is active\n1: R_RX_DONE interrupt is active\n1: R_ACTIVITY interrupt is active\n1: R_STOP_DET interrupt is active\n1: R_START_DET interrupt is active\n1: R_GEN_CALL interrupt is active\n1: R_RESTART_DET interrupt is active\nI2C Interrupt Status Register\n0: RX_UNDER interrupt is inactive\n0: R_RX_OVER interrupt is inactive\n0: R_RX_FULL interrupt is inactive\n0: R_TX_OVER interrupt is inactive\n0: R_TX_EMPTY interrupt is inactive\n0: R_RD_REQ interrupt is inactive\n0: R_TX_ABRT interrupt is inactive\n0: R_RX_DONE interrupt is inactive\n0: R_ACTIVITY interrupt is inactive\n0: R_STOP_DET interrupt is inactive\n0: R_START_DET interrupt is inactive\n0: R_GEN_CALL interrupt is inactive\n0: R_RESTART_DET interrupt is inactive\nRegister <code>IC_INTR_STAT</code> reader\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_ACTIVITY</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_GEN_CALL</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_RD_REQ</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_RESTART_DET</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_RX_DONE</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_RX_FULL</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_RX_OVER</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_RX_UNDER</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_START_DET</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_STOP_DET</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_TX_ABRT</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_TX_EMPTY</code> reader - See IC_RAW_INTR_STAT for a …\nSee IC_RAW_INTR_STAT for a detailed description of …\nField <code>R_TX_OVER</code> reader - See IC_RAW_INTR_STAT for a …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nRX_UNDER interrupt is active\nR_RX_OVER interrupt is active\nR_RX_FULL interrupt is active\nR_TX_OVER interrupt is active\nR_TX_EMPTY interrupt is active\nR_RD_REQ interrupt is active\nR_TX_ABRT interrupt is active\nR_RX_DONE interrupt is active\nR_ACTIVITY interrupt is active\nR_STOP_DET interrupt is active\nR_START_DET interrupt is active\nR_GEN_CALL interrupt is active\nR_RESTART_DET interrupt is active\nRX_UNDER interrupt is inactive\nR_RX_OVER interrupt is inactive\nR_RX_FULL interrupt is inactive\nR_TX_OVER interrupt is inactive\nR_TX_EMPTY interrupt is inactive\nR_RD_REQ interrupt is inactive\nR_TX_ABRT interrupt is inactive\nR_RX_DONE interrupt is inactive\nR_ACTIVITY interrupt is inactive\nR_STOP_DET interrupt is inactive\nR_START_DET interrupt is inactive\nR_GEN_CALL interrupt is inactive\nR_RESTART_DET interrupt is inactive\nBit 8 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 11 - See IC_RAW_INTR_STAT for a detailed description …\nBit 5 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 12 - See IC_RAW_INTR_STAT for a detailed description …\nBit 7 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 2 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 1 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 0 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 10 - See IC_RAW_INTR_STAT for a detailed description …\nBit 9 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 6 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 4 - See IC_RAW_INTR_STAT for a detailed description of …\nBit 3 - See IC_RAW_INTR_STAT for a detailed description of …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\n1: RX_UNDER interrupt is active\n1: RX_OVER interrupt is active\n1: RX_FULL interrupt is active\n1: TX_OVER interrupt is active\n1: TX_EMPTY interrupt is active\n1: RD_REQ interrupt is active\n1: TX_ABRT interrupt is active\n1: RX_DONE interrupt is active\n1: RAW_INTR_ACTIVITY interrupt is active\n1: STOP_DET interrupt is active\n1: START_DET interrupt is active\n1: GEN_CALL interrupt is active\n1: RESTART_DET interrupt is active\nThis bit captures DW_apb_i2c activity and stays set until …\nField <code>ACTIVITY</code> reader - This bit captures DW_apb_i2c …\nSet only when a General Call address is received and it is …\nField <code>GEN_CALL</code> reader - Set only when a General Call …\nI2C Raw Interrupt Status Register\n0: RX_UNDER interrupt is inactive\n0: RX_OVER interrupt is inactive\n0: RX_FULL interrupt is inactive\n0: TX_OVER interrupt is inactive\n0: TX_EMPTY interrupt is inactive\n0: RD_REQ interrupt is inactive\n0: TX_ABRT interrupt is inactive\n0: RX_DONE interrupt is inactive\n0: RAW_INTR_ACTIVITY interrupt is inactive\n0: STOP_DET interrupt is inactive\n0: START_DET interrupt is inactive\n0: GEN_CALL interrupt is inactive\n0: RESTART_DET interrupt is inactive\nRegister <code>IC_RAW_INTR_STAT</code> reader\nThis bit is set to 1 when DW_apb_i2c is acting as a slave …\nField <code>RD_REQ</code> reader - This bit is set to 1 when DW_apb_i2c …\nIndicates whether a RESTART condition has occurred on the …\nField <code>RESTART_DET</code> reader - Indicates whether a RESTART …\nWhen the DW_apb_i2c is acting as a slave-transmitter, this …\nField <code>RX_DONE</code> reader - When the DW_apb_i2c is acting as a …\nSet when the receive buffer reaches or goes above the …\nField <code>RX_FULL</code> reader - Set when the receive buffer reaches …\nSet if the receive buffer is completely filled to …\nField <code>RX_OVER</code> reader - Set if the receive buffer is …\nSet if the processor attempts to read the receive buffer …\nField <code>RX_UNDER</code> reader - Set if the processor attempts to …\nIndicates whether a START or RESTART condition has …\nField <code>START_DET</code> reader - Indicates whether a START or …\nIndicates whether a STOP condition has occurred on the I2C …\nField <code>STOP_DET</code> reader - Indicates whether a STOP condition …\nThis bit indicates if DW_apb_i2c, as an I2C transmitter, …\nField <code>TX_ABRT</code> reader - This bit indicates if DW_apb_i2c, …\nThe behavior of the TX_EMPTY interrupt status differs …\nField <code>TX_EMPTY</code> reader - The behavior of the TX_EMPTY …\nSet during transmit if the transmit buffer is filled to …\nField <code>TX_OVER</code> reader - Set during transmit if the transmit …\nBit 8 - This bit captures DW_apb_i2c activity and stays …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 11 - Set only when a General Call address is received …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nRX_UNDER interrupt is active\nRX_OVER interrupt is active\nRX_FULL interrupt is active\nTX_OVER interrupt is active\nTX_EMPTY interrupt is active\nRD_REQ interrupt is active\nTX_ABRT interrupt is active\nRX_DONE interrupt is active\nRAW_INTR_ACTIVITY interrupt is active\nSTOP_DET interrupt is active\nSTART_DET interrupt is active\nGEN_CALL interrupt is active\nRESTART_DET interrupt is active\nRX_UNDER interrupt is inactive\nRX_OVER interrupt is inactive\nRX_FULL interrupt is inactive\nTX_OVER interrupt is inactive\nTX_EMPTY interrupt is inactive\nRD_REQ interrupt is inactive\nTX_ABRT interrupt is inactive\nRX_DONE interrupt is inactive\nRAW_INTR_ACTIVITY interrupt is inactive\nSTOP_DET interrupt is inactive\nSTART_DET interrupt is inactive\nGEN_CALL interrupt is inactive\nRESTART_DET interrupt is inactive\nBit 5 - This bit is set to 1 when DW_apb_i2c is acting as …\nBit 12 - Indicates whether a RESTART condition has …\nBit 7 - When the DW_apb_i2c is acting as a …\nBit 2 - Set when the receive buffer reaches or goes above …\nBit 1 - Set if the receive buffer is completely filled to …\nBit 0 - Set if the processor attempts to read the receive …\nBit 10 - Indicates whether a START or RESTART condition …\nBit 9 - Indicates whether a STOP condition has occurred on …\nBit 6 - This bit indicates if DW_apb_i2c, as an I2C …\nBit 4 - The behavior of the TX_EMPTY interrupt status …\nBit 3 - Set during transmit if the transmit buffer is …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nI2C Receive FIFO Threshold Register\nRegister <code>IC_RX_TL</code> reader\nField <code>RX_TL</code> reader - Receive FIFO Threshold Level.\nField <code>RX_TL</code> writer - Receive FIFO Threshold Level.\nRegister <code>IC_RX_TL</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - Receive FIFO Threshold Level.\nBits 0:7 - Receive FIFO Threshold Level.\nI2C Receive FIFO Level Register This register contains the …\nRegister <code>IC_RXFLR</code> reader\nField <code>RXFLR</code> reader - Receive FIFO Level. Contains the …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:4 - Receive FIFO Level. Contains the number of …\nField <code>IC_SAR</code> reader - The IC_SAR holds the slave address …\nI2C Slave Address Register\nField <code>IC_SAR</code> writer - The IC_SAR holds the slave address …\nRegister <code>IC_SAR</code> reader\nRegister <code>IC_SAR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:9 - The IC_SAR holds the slave address when the I2C …\nBits 0:9 - The IC_SAR holds the slave address when the I2C …\nCalls <code>U::from(self)</code>.\nI2C SDA Hold Time Length Register\nField <code>IC_SDA_RX_HOLD</code> reader - Sets the required SDA hold …\nField <code>IC_SDA_RX_HOLD</code> writer - Sets the required SDA hold …\nField <code>IC_SDA_TX_HOLD</code> reader - Sets the required SDA hold …\nField <code>IC_SDA_TX_HOLD</code> writer - Sets the required SDA hold …\nRegister <code>IC_SDA_HOLD</code> reader\nRegister <code>IC_SDA_HOLD</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 16:23 - Sets the required SDA hold time in units of …\nBits 16:23 - Sets the required SDA hold time in units of …\nBits 0:15 - Sets the required SDA hold time in units of …\nBits 0:15 - Sets the required SDA hold time in units of …\nCalls <code>U::from(self)</code>.\nI2C SDA Setup Register\nRegister <code>IC_SDA_SETUP</code> reader\nField <code>SDA_SETUP</code> reader - SDA Setup. It is recommended that …\nField <code>SDA_SETUP</code> writer - SDA Setup. It is recommended that …\nRegister <code>IC_SDA_SETUP</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - SDA Setup. It is recommended that if the …\nBits 0:7 - SDA Setup. It is recommended that if the …\n0: Slave receiver generates NACK normally\n1: Slave receiver generates NACK upon data reception only\nGenerate Slave Data NACK Register\nGenerate NACK. This NACK generation only occurs when …\nField <code>NACK</code> reader - Generate NACK. This NACK generation …\nField <code>NACK</code> writer - Generate NACK. This NACK generation …\nRegister <code>IC_SLV_DATA_NACK_ONLY</code> reader\nRegister <code>IC_SLV_DATA_NACK_ONLY</code> writer\nWrites raw bits to the register.\nSlave receiver generates NACK normally\nSlave receiver generates NACK upon data reception only\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSlave receiver generates NACK normally\nSlave receiver generates NACK upon data reception only\nBit 0 - Generate NACK. This NACK generation only occurs …\nBit 0 - Generate NACK. This NACK generation only occurs …\nGet enumerated values variant\nField <code>IC_SS_SCL_HCNT</code> reader - This register must be set …\nStandard Speed I2C Clock SCL High Count Register\nField <code>IC_SS_SCL_HCNT</code> writer - This register must be set …\nRegister <code>IC_SS_SCL_HCNT</code> reader\nRegister <code>IC_SS_SCL_HCNT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - This register must be set before any I2C bus …\nBits 0:15 - This register must be set before any I2C bus …\nCalls <code>U::from(self)</code>.\nField <code>IC_SS_SCL_LCNT</code> reader - This register must be set …\nStandard Speed I2C Clock SCL Low Count Register\nField <code>IC_SS_SCL_LCNT</code> writer - This register must be set …\nRegister <code>IC_SS_SCL_LCNT</code> reader\nRegister <code>IC_SS_SCL_LCNT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:15 - This register must be set before any I2C bus …\nBits 0:15 - This register must be set before any I2C bus …\nCalls <code>U::from(self)</code>.\n1: I2C is active\n1: Master not idle\n1: Slave not idle\nI2C Activity Status. Reset value: 0x0\nField <code>ACTIVITY</code> reader - I2C Activity Status. Reset value: …\n1: Tx FIFO is empty\n0: Rx FIFO is empty\n0: Tx FIFO is full\n1: Rx FIFO is full\nI2C Status Register\n0: Master is idle\n0: Slave is idle\n0: I2C is idle\nMaster FSM Activity Status. When the Master Finite State …\nField <code>MST_ACTIVITY</code> reader - Master FSM Activity Status. …\n0: Tx FIFO not empty\n1: Rx FIFO not empty\n1: Tx FIFO not full\n0: Rx FIFO not full\nRegister <code>IC_STATUS</code> reader\nReceive FIFO Completely Full. When the receive FIFO is …\nField <code>RFF</code> reader - Receive FIFO Completely Full. When the …\nReceive FIFO Not Empty. This bit is set when the receive …\nField <code>RFNE</code> reader - Receive FIFO Not Empty. This bit is …\nSlave FSM Activity Status. When the Slave Finite State …\nField <code>SLV_ACTIVITY</code> reader - Slave FSM Activity Status. …\nTransmit FIFO Completely Empty. When the transmit FIFO is …\nField <code>TFE</code> reader - Transmit FIFO Completely Empty. When …\nTransmit FIFO Not Full. Set when the transmit FIFO …\nField <code>TFNF</code> reader - Transmit FIFO Not Full. Set when the …\nBit 0 - I2C Activity Status. Reset value: 0x0\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nI2C is active\nMaster not idle\nSlave not idle\nTx FIFO is empty\nRx FIFO is empty\nTx FIFO is full\nRx FIFO is full\nMaster is idle\nSlave is idle\nI2C is idle\nTx FIFO not empty\nRx FIFO not empty\nTx FIFO not full\nRx FIFO not full\nBit 5 - Master FSM Activity Status. When the Master Finite …\nBit 4 - Receive FIFO Completely Full. When the receive …\nBit 3 - Receive FIFO Not Empty. This bit is set when the …\nBit 6 - Slave FSM Activity Status. When the Slave Finite …\nBit 2 - Transmit FIFO Completely Empty. When the transmit …\nBit 1 - Transmit FIFO Not Full. Set when the transmit FIFO …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\n0: Disables programming of GENERAL_CALL or START_BYTE …\n1: Enables programming of GENERAL_CALL or START_BYTE …\nIf bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is …\nField <code>GC_OR_START</code> reader - If bit 11 (SPECIAL) is set to 1 …\nField <code>GC_OR_START</code> writer - If bit 11 (SPECIAL) is set to 1 …\n0: GENERAL_CALL byte transmission\nField <code>IC_TAR</code> reader - This is the target address for any …\nI2C Target Address Register\nField <code>IC_TAR</code> writer - This is the target address for any …\nRegister <code>IC_TAR</code> reader\nThis bit indicates whether software performs a Device-ID …\nField <code>SPECIAL</code> reader - This bit indicates whether software …\nField <code>SPECIAL</code> writer - This bit indicates whether software …\n1: START byte transmission\nRegister <code>IC_TAR</code> writer\nWrites raw bits to the register.\nDisables programming of GENERAL_CALL or START_BYTE …\nEnables programming of GENERAL_CALL or START_BYTE …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 10 - If bit 11 (SPECIAL) is set to 1 and bit …\nBit 10 - If bit 11 (SPECIAL) is set to 1 and bit …\nGENERAL_CALL byte transmission\nBits 0:9 - This is the target address for any master …\nBits 0:9 - This is the target address for any master …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nDisables programming of GENERAL_CALL or START_BYTE …\nEnables programming of GENERAL_CALL or START_BYTE …\nGENERAL_CALL byte transmission\nSTART byte transmission\nBit 11 - This bit indicates whether software performs a …\nBit 11 - This bit indicates whether software performs a …\nSTART byte transmission\nGet enumerated values variant\nGet enumerated values variant\nThis field indicates that the Master is in 10-bit address …\nField <code>ABRT_10ADDR1_NOACK</code> reader - This field indicates …\nThis field indicates that the Master is in 10-bit address …\nField <code>ABRT_10ADDR2_NOACK</code> reader - This field indicates …\n1: Master trying to read in 10Bit addressing mode when …\nThis field indicates that the restart is disabled …\nField <code>ABRT_10B_RD_NORSTRT</code> reader - This field indicates …\n0: Master not trying to read in 10Bit addressing mode when …\nThis field indicates that the Master is in 7-bit …\nField <code>ABRT_7B_ADDR_NOACK</code> reader - This field indicates …\nThis field indicates that DW_apb_i2c in master mode has …\n1: GCALL not ACKed by any slave\nField <code>ABRT_GCALL_NOACK</code> reader - This field indicates that …\n0: GCALL not ACKed by any slave-scenario not present\nThis field indicates that DW_apb_i2c in the master mode …\n1: GCALL is followed by read from bus\nField <code>ABRT_GCALL_READ</code> reader - This field indicates that …\n0: GCALL is followed by read from bus-scenario not present\nThis field indicates that the Master is in High Speed mode …\nField <code>ABRT_HS_ACKDET</code> reader - This field indicates that …\n1: HS Master code ACKed in HS Mode\n0: HS Master code ACKed in HS Mode- scenario not present\nThis field indicates that the restart is disabled …\n1: User trying to switch Master to HS mode when RESTART …\nField <code>ABRT_HS_NORSTRT</code> reader - This field indicates that …\n0: User trying to switch Master to HS mode when RESTART …\n1: Master or Slave-Transmitter lost arbitration\n0: Master or Slave-Transmitter lost arbitration- scenario …\nThis field indicates that the User tries to initiate a …\n1: User initiating master operation when MASTER disabled\nField <code>ABRT_MASTER_DIS</code> reader - This field indicates that …\n0: User initiating master operation when MASTER disabled- …\nThis field indicates that the Master has sent a START Byte …\n1: ACK detected for START byte\nField <code>ABRT_SBYTE_ACKDET</code> reader - This field indicates that …\n0: ACK detected for START byte- scenario not present\nTo clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must …\n1: User trying to send START byte when RESTART disabled\nField <code>ABRT_SBYTE_NORSTRT</code> reader - To clear Bit 9, the …\n0: User trying to send START byte when RESTART disabled- …\nThis field specifies that the Slave has received a read …\n1: Slave flushes existing data in TX-FIFO upon getting …\nField <code>ABRT_SLVFLUSH_TXFIFO</code> reader - This field specifies …\n0: Slave flushes existing data in TX-FIFO upon getting …\n1: When the processor side responds to a slave mode …\n1: Slave trying to transmit to remote master in read mode\nField <code>ABRT_SLVRD_INTX</code> reader - 1: When the processor side …\n0: Slave trying to transmit to remote master in read mode- …\nThis field indicates that a Slave has lost the bus while …\n1: Slave lost arbitration to remote master\nField <code>ABRT_SLV_ARBLOST</code> reader - This field indicates that …\n0: Slave lost arbitration to remote master- scenario not …\nThis field indicates the master-mode only bit. When the …\n1: Transmitted data not ACKed by addressed slave\nField <code>ABRT_TXDATA_NOACK</code> reader - This field indicates the …\n0: Transmitted data non-ACKed by addressed slave-scenario …\nThis is a master-mode-only bit. Master has detected the …\n1: Transfer abort detected by master\nField <code>ABRT_USER_ABRT</code> reader - This is a master-mode-only …\n0: Transfer abort detected by master- scenario not present\n1: This abort is generated because of NOACK for 7-bit …\n1: Byte 1 of 10Bit Address not ACKed by any slave\n1: Byte 2 of 10Bit Address not ACKed by any slave\nThis field specifies that the Master has lost arbitration, …\nField <code>ARB_LOST</code> reader - This field specifies that the …\nI2C Transmit Abort Source Register\n0: This abort is not generated\n0: This abort is not generated\n0: This abort is not generated\nRegister <code>IC_TX_ABRT_SOURCE</code> reader\nField <code>TX_FLUSH_CNT</code> reader - This field indicates the …\nBit 1 - This field indicates that the Master is in 10-bit …\nBit 2 - This field indicates that the Master is in 10-bit …\nBit 10 - This field indicates that the restart is disabled …\nBit 0 - This field indicates that the Master is in 7-bit …\nBit 4 - This field indicates that DW_apb_i2c in master …\nBit 5 - This field indicates that DW_apb_i2c in the master …\nBit 6 - This field indicates that the Master is in High …\nBit 8 - This field indicates that the restart is disabled …\nBit 11 - This field indicates that the User tries to …\nBit 7 - This field indicates that the Master has sent a …\nBit 9 - To clear Bit 9, the source of the …\nBit 14 - This field indicates that a Slave has lost the …\nBit 13 - This field specifies that the Slave has received …\nBit 15 - 1: When the processor side responds to a slave …\nBit 3 - This field indicates the master-mode only bit. …\nBit 16 - This is a master-mode-only bit. Master has …\nBit 12 - This field specifies that the Master has lost …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nMaster trying to read in 10Bit addressing mode when …\nMaster not trying to read in 10Bit addressing mode when …\nGCALL not ACKed by any slave\nGCALL not ACKed by any slave-scenario not present\nGCALL is followed by read from bus\nGCALL is followed by read from bus-scenario not present\nHS Master code ACKed in HS Mode\nHS Master code ACKed in HS Mode- scenario not present\nUser trying to switch Master to HS mode when RESTART …\nUser trying to switch Master to HS mode when RESTART …\nMaster or Slave-Transmitter lost arbitration\nMaster or Slave-Transmitter lost arbitration- scenario not …\nUser initiating master operation when MASTER disabled\nUser initiating master operation when MASTER disabled- …\nACK detected for START byte\nACK detected for START byte- scenario not present\nUser trying to send START byte when RESTART disabled\nUser trying to send START byte when RESTART disabled- …\nSlave lost arbitration to remote master\nSlave lost arbitration to remote master- scenario not …\nSlave flushes existing data in TX-FIFO upon getting read …\nSlave flushes existing data in TX-FIFO upon getting read …\nSlave trying to transmit to remote master in read mode\nSlave trying to transmit to remote master in read mode- …\nTransmitted data not ACKed by addressed slave\nTransmitted data non-ACKed by addressed slave-scenario not …\nTransfer abort detected by master\nTransfer abort detected by master- scenario not present\nThis abort is generated because of NOACK for 7-bit address\nByte 1 of 10Bit Address not ACKed by any slave\nByte 2 of 10Bit Address not ACKed by any slave\nThis abort is not generated\nThis abort is not generated\nThis abort is not generated\nBits 23:31 - This field indicates the number of Tx FIFO …\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nI2C Transmit FIFO Threshold Register\nRegister <code>IC_TX_TL</code> reader\nField <code>TX_TL</code> reader - Transmit FIFO Threshold Level.\nField <code>TX_TL</code> writer - Transmit FIFO Threshold Level.\nRegister <code>IC_TX_TL</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - Transmit FIFO Threshold Level.\nBits 0:7 - Transmit FIFO Threshold Level.\nI2C Transmit FIFO Level Register This register contains …\nRegister <code>IC_TXFLR</code> reader\nField <code>TXFLR</code> reader - Transmit FIFO Level. Contains the …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:4 - Transmit FIFO Level. Contains the number of …\nDORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable …\nDORMANT_WAKE_INTF (rw) register accessor: Interrupt Force …\nDORMANT_WAKE_INTS (r) register accessor: Interrupt status …\nCluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL\nINTR (rw) register accessor: Raw Interrupts\nPROC0_INTE (rw) register accessor: Interrupt Enable for …\nPROC0_INTF (rw) register accessor: Interrupt Force for …\nPROC0_INTS (r) register accessor: Interrupt status after …\nPROC1_INTE (rw) register accessor: Interrupt Enable for …\nPROC1_INTF (rw) register accessor: Interrupt Force for …\nPROC1_INTS (r) register accessor: Interrupt status after …\nRegister block\nInterrupt Enable for dormant_wake\n0x160..0x170 - Interrupt Enable for dormant_wake\nIterator for array of: 0x160..0x170 - Interrupt Enable for …\nInterrupt Force for dormant_wake\n0x170..0x180 - Interrupt Force for dormant_wake\nIterator for array of: 0x170..0x180 - Interrupt Force for …\nInterrupt status after masking &amp; forcing for dormant_wake\n0x180..0x190 - Interrupt status after masking &amp; forcing …\nIterator for array of: 0x180..0x190 - Interrupt status …\nReturns the argument unchanged.\nCluster Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL\n0x00..0xf0 - Cluster GPIO%s, containing GPIO*_STATUS, GPIO*…\nIterator for array of: 0x00..0xf0 - Cluster GPIO%s, …\nCalls <code>U::from(self)</code>.\nRaw Interrupts\n0xf0..0x100 - Raw Interrupts\nIterator for array of: 0xf0..0x100 - Raw Interrupts\nInterrupt Enable for proc0\n0x100..0x110 - Interrupt Enable for proc0\nIterator for array of: 0x100..0x110 - Interrupt Enable for …\nInterrupt Force for proc0\n0x110..0x120 - Interrupt Force for proc0\nIterator for array of: 0x110..0x120 - Interrupt Force for …\nInterrupt status after masking &amp; forcing for proc0\n0x120..0x130 - Interrupt status after masking &amp; forcing …\nIterator for array of: 0x120..0x130 - Interrupt status …\nInterrupt Enable for proc1\n0x130..0x140 - Interrupt Enable for proc1\nIterator for array of: 0x130..0x140 - Interrupt Enable for …\nInterrupt Force for proc1\n0x140..0x150 - Interrupt Force for proc1\nIterator for array of: 0x140..0x150 - Interrupt Force for …\nInterrupt status after masking &amp; forcing for proc1\n0x150..0x160 - Interrupt status after masking &amp; forcing …\nIterator for array of: 0x150..0x160 - Interrupt status …\nInterrupt Enable for dormant_wake\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_HIGH</code> writer -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_EDGE_LOW</code> writer -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> writer -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> writer -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> writer -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_EDGE_LOW</code> writer -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> writer -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> writer -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> writer -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_EDGE_LOW</code> writer -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> writer -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> writer -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> writer -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_EDGE_LOW</code> writer -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> writer -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> writer -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> writer -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_EDGE_LOW</code> writer -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> writer -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> writer -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> writer -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_EDGE_LOW</code> writer -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> writer -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> writer -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> writer -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_EDGE_LOW</code> writer -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> writer -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> writer -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> writer -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_EDGE_LOW</code> writer -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> writer -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> writer -\nRegister <code>DORMANT_WAKE_INTE%s</code> reader\nRegister <code>DORMANT_WAKE_INTE%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 27\nBit 27\nBit 26\nBit 26\nBit 25\nBit 25\nBit 24\nBit 24\nBit 31\nBit 31\nBit 30\nBit 30\nBit 29\nBit 29\nBit 28\nBit 28\nCalls <code>U::from(self)</code>.\nInterrupt Force for dormant_wake\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_HIGH</code> writer -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_EDGE_LOW</code> writer -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> writer -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> writer -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> writer -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_EDGE_LOW</code> writer -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> writer -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> writer -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> writer -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_EDGE_LOW</code> writer -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> writer -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> writer -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> writer -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_EDGE_LOW</code> writer -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> writer -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> writer -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> writer -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_EDGE_LOW</code> writer -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> writer -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> writer -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> writer -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_EDGE_LOW</code> writer -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> writer -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> writer -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> writer -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_EDGE_LOW</code> writer -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> writer -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> writer -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> writer -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_EDGE_LOW</code> writer -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> writer -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> writer -\nRegister <code>DORMANT_WAKE_INTF%s</code> reader\nRegister <code>DORMANT_WAKE_INTF%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 27\nBit 27\nBit 26\nBit 26\nBit 25\nBit 25\nBit 24\nBit 24\nBit 31\nBit 31\nBit 30\nBit 30\nBit 29\nBit 29\nBit 28\nBit 28\nCalls <code>U::from(self)</code>.\nInterrupt status after masking &amp; forcing for dormant_wake\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nRegister <code>DORMANT_WAKE_INTS%s</code> reader\nReturns the argument unchanged.\nBit 3\nBit 2\nBit 1\nBit 0\nBit 7\nBit 6\nBit 5\nBit 4\nBit 11\nBit 10\nBit 9\nBit 8\nBit 15\nBit 14\nBit 13\nBit 12\nBit 19\nBit 18\nBit 17\nBit 16\nBit 23\nBit 22\nBit 21\nBit 20\nBit 27\nBit 26\nBit 25\nBit 24\nBit 31\nBit 30\nBit 29\nBit 28\nCalls <code>U::from(self)</code>.\nRegister block\nGPIO_CTRL (rw) register accessor: GPIO control including …\nGPIO_STATUS (r) register accessor: GPIO status\nReturns the argument unchanged.\nGPIO control including function select and overrides.\n0x04 - GPIO control including function select and …\nGPIO status\n0x00 - GPIO status\nCalls <code>U::from(self)</code>.\n8: Connect to Clock peripheral\n2: disable output\n3: enable output\n0-31 -&gt; selects pin function according to the GPIO table. …\nField <code>FUNCSEL</code> reader - 0-31 -&gt; selects pin function …\nField <code>FUNCSEL</code> writer - 0-31 -&gt; selects pin function …\nGPIO control including function select and overrides.\n3: drive output high\n3: drive peri input high\n3: drive interrupt high\n3: Connect to matching I2C peripheral\nValue on reset: 0\nField <code>INOVER</code> reader -\nField <code>INOVER</code> writer -\n1: drive output from inverse of peripheral signal selected …\n1: drive output enable from inverse of peripheral signal …\n1: invert the peri input\n1: invert the interrupt\nValue on reset: 0\nField <code>IRQOVER</code> reader -\nField <code>IRQOVER</code> writer -\n0: Connect to JTAG peripheral\n2: drive output low\n2: drive peri input low\n2: drive interrupt low\n0: drive output from peripheral signal selected by funcsel\n0: drive output enable from peripheral signal selected by …\n0: don’t invert the peri input\n0: don’t invert the interrupt\n31: Connect to nothing\nValue on reset: 0\nField <code>OEOVER</code> reader -\nField <code>OEOVER</code> writer -\nValue on reset: 0\nField <code>OUTOVER</code> reader -\nField <code>OUTOVER</code> writer -\n6: Connect to PIO0 peripheral\n7: Connect to PIO1 peripheral\n4: Connect to matching PWM peripheral\nRegister <code>GPIO_CTRL</code> reader\n5: Use as a GPIO pin (connect to SIO peripheral)\n1: Connect to matching SPI peripheral\n2: Connect to matching UART peripheral\n9: Connect to USB peripheral\nRegister <code>GPIO_CTRL</code> writer\nWrites raw bits to the register.\nConnect to Clock peripheral\ndisable output\nenable output\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBits 0:4 - 0-31 -&gt; selects pin function according to the …\nBits 0:4 - 0-31 -&gt; selects pin function according to the …\ndrive output high\ndrive peri input high\ndrive interrupt high\nConnect to matching I2C peripheral\nBits 16:17\nBits 16:17\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\ndrive output from inverse of peripheral signal selected by …\ndrive output enable from inverse of peripheral signal …\ninvert the peri input\ninvert the interrupt\nBits 28:29\nBits 28:29\nConnect to Clock peripheral\ndisable output\nenable output\ndrive output high\ndrive peri input high\ndrive interrupt high\nConnect to matching I2C peripheral\ndrive output from inverse of peripheral signal selected by …\ndrive output enable from inverse of peripheral signal …\ninvert the peri input\ninvert the interrupt\nConnect to JTAG peripheral\ndrive output low\ndrive peri input low\ndrive interrupt low\ndrive output from peripheral signal selected by funcsel\ndrive output enable from peripheral signal selected by …\ndon’t invert the peri input\ndon’t invert the interrupt\nConnect to nothing\nConnect to PIO0 peripheral\nConnect to PIO1 peripheral\nConnect to matching PWM peripheral\nUse as a GPIO pin (connect to SIO peripheral)\nConnect to matching SPI peripheral\nConnect to matching UART peripheral\nConnect to USB peripheral\nConnect to JTAG peripheral\ndrive output low\ndrive peri input low\ndrive interrupt low\ndrive output from peripheral signal selected by funcsel\ndrive output enable from peripheral signal selected by …\ndon’t invert the peri input\ndon’t invert the interrupt\nConnect to nothing\nBits 12:13\nBits 12:13\nBits 8:9\nBits 8:9\nConnect to PIO0 peripheral\nConnect to PIO1 peripheral\nConnect to matching PWM peripheral\nUse as a GPIO pin (connect to SIO peripheral)\nConnect to matching SPI peripheral\nConnect to matching UART peripheral\nConnect to USB peripheral\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGet enumerated values variant\nGPIO status\nField <code>INFROMPAD</code> reader - input signal from pad, before …\nField <code>INTOPERI</code> reader - input signal to peripheral, after …\nField <code>IRQFROMPAD</code> reader - interrupt from pad before …\nField <code>IRQTOPROC</code> reader - interrupt to processors, after …\nField <code>OEFROMPERI</code> reader - output enable from selected …\nField <code>OETOPAD</code> reader - output enable to pad after register …\nField <code>OUTFROMPERI</code> reader - output signal from selected …\nField <code>OUTTOPAD</code> reader - output signal to pad after …\nRegister <code>GPIO_STATUS</code> reader\nReturns the argument unchanged.\nBit 17 - input signal from pad, before override is applied\nCalls <code>U::from(self)</code>.\nBit 19 - input signal to peripheral, after override is …\nBit 24 - interrupt from pad before override is applied\nBit 26 - interrupt to processors, after override is applied\nBit 12 - output enable from selected peripheral, before …\nBit 13 - output enable to pad after register override is …\nBit 8 - output signal from selected peripheral, before …\nBit 9 - output signal to pad after register override is …\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_HIGH</code> writer -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_EDGE_LOW</code> writer -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> writer -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_EDGE_LOW</code> writer -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> writer -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_EDGE_LOW</code> writer -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> writer -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_EDGE_LOW</code> writer -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> writer -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_EDGE_LOW</code> writer -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> writer -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_EDGE_LOW</code> writer -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> writer -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_EDGE_LOW</code> writer -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> writer -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_EDGE_LOW</code> writer -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nRaw Interrupts\nRegister <code>INTR%s</code> reader\nRegister <code>INTR%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 0\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 4\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 20\nBit 27\nBit 27\nBit 26\nBit 26\nBit 25\nBit 24\nBit 31\nBit 31\nBit 30\nBit 30\nBit 29\nBit 28\nCalls <code>U::from(self)</code>.\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_HIGH</code> writer -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_EDGE_LOW</code> writer -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> writer -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> writer -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> writer -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_EDGE_LOW</code> writer -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> writer -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> writer -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> writer -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_EDGE_LOW</code> writer -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> writer -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> writer -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> writer -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_EDGE_LOW</code> writer -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> writer -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> writer -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> writer -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_EDGE_LOW</code> writer -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> writer -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> writer -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> writer -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_EDGE_LOW</code> writer -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> writer -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> writer -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> writer -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_EDGE_LOW</code> writer -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> writer -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> writer -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> writer -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_EDGE_LOW</code> writer -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> writer -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> writer -\nInterrupt Enable for proc0\nRegister <code>PROC0_INTE%s</code> reader\nRegister <code>PROC0_INTE%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 27\nBit 27\nBit 26\nBit 26\nBit 25\nBit 25\nBit 24\nBit 24\nBit 31\nBit 31\nBit 30\nBit 30\nBit 29\nBit 29\nBit 28\nBit 28\nCalls <code>U::from(self)</code>.\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_HIGH</code> writer -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_EDGE_LOW</code> writer -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> writer -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> writer -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> writer -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_EDGE_LOW</code> writer -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> writer -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> writer -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> writer -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_EDGE_LOW</code> writer -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> writer -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> writer -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> writer -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_EDGE_LOW</code> writer -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> writer -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> writer -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> writer -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_EDGE_LOW</code> writer -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> writer -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> writer -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> writer -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_EDGE_LOW</code> writer -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> writer -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> writer -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> writer -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_EDGE_LOW</code> writer -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> writer -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> writer -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> writer -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_EDGE_LOW</code> writer -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> writer -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> writer -\nInterrupt Force for proc0\nRegister <code>PROC0_INTF%s</code> reader\nRegister <code>PROC0_INTF%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 27\nBit 27\nBit 26\nBit 26\nBit 25\nBit 25\nBit 24\nBit 24\nBit 31\nBit 31\nBit 30\nBit 30\nBit 29\nBit 29\nBit 28\nBit 28\nCalls <code>U::from(self)</code>.\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nInterrupt status after masking &amp; forcing for proc0\nRegister <code>PROC0_INTS%s</code> reader\nReturns the argument unchanged.\nBit 3\nBit 2\nBit 1\nBit 0\nBit 7\nBit 6\nBit 5\nBit 4\nBit 11\nBit 10\nBit 9\nBit 8\nBit 15\nBit 14\nBit 13\nBit 12\nBit 19\nBit 18\nBit 17\nBit 16\nBit 23\nBit 22\nBit 21\nBit 20\nBit 27\nBit 26\nBit 25\nBit 24\nBit 31\nBit 30\nBit 29\nBit 28\nCalls <code>U::from(self)</code>.\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_HIGH</code> writer -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_EDGE_LOW</code> writer -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> writer -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> writer -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> writer -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_EDGE_LOW</code> writer -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> writer -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> writer -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> writer -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_EDGE_LOW</code> writer -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> writer -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> writer -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> writer -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_EDGE_LOW</code> writer -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> writer -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> writer -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> writer -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_EDGE_LOW</code> writer -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> writer -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> writer -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> writer -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_EDGE_LOW</code> writer -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> writer -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> writer -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> writer -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_EDGE_LOW</code> writer -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> writer -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> writer -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> writer -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_EDGE_LOW</code> writer -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> writer -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> writer -\nInterrupt Enable for proc1\nRegister <code>PROC1_INTE%s</code> reader\nRegister <code>PROC1_INTE%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 27\nBit 27\nBit 26\nBit 26\nBit 25\nBit 25\nBit 24\nBit 24\nBit 31\nBit 31\nBit 30\nBit 30\nBit 29\nBit 29\nBit 28\nBit 28\nCalls <code>U::from(self)</code>.\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_HIGH</code> writer -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_EDGE_LOW</code> writer -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> writer -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> writer -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> writer -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_EDGE_LOW</code> writer -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> writer -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> writer -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> writer -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_EDGE_LOW</code> writer -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> writer -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> writer -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> writer -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_EDGE_LOW</code> writer -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> writer -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> writer -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> writer -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_EDGE_LOW</code> writer -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> writer -\nField <code>GPIO4_LEVEL_LOW</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> writer -\nField <code>GPIO5_EDGE_HIGH</code> reader -\nField <code>GPIO5_EDGE_HIGH</code> writer -\nField <code>GPIO5_EDGE_LOW</code> reader -\nField <code>GPIO5_EDGE_LOW</code> writer -\nField <code>GPIO5_LEVEL_HIGH</code> reader -\nField <code>GPIO5_LEVEL_HIGH</code> writer -\nField <code>GPIO5_LEVEL_LOW</code> reader -\nField <code>GPIO5_LEVEL_LOW</code> writer -\nField <code>GPIO6_EDGE_HIGH</code> reader -\nField <code>GPIO6_EDGE_HIGH</code> writer -\nField <code>GPIO6_EDGE_LOW</code> reader -\nField <code>GPIO6_EDGE_LOW</code> writer -\nField <code>GPIO6_LEVEL_HIGH</code> reader -\nField <code>GPIO6_LEVEL_HIGH</code> writer -\nField <code>GPIO6_LEVEL_LOW</code> reader -\nField <code>GPIO6_LEVEL_LOW</code> writer -\nField <code>GPIO7_EDGE_HIGH</code> reader -\nField <code>GPIO7_EDGE_HIGH</code> writer -\nField <code>GPIO7_EDGE_LOW</code> reader -\nField <code>GPIO7_EDGE_LOW</code> writer -\nField <code>GPIO7_LEVEL_HIGH</code> reader -\nField <code>GPIO7_LEVEL_HIGH</code> writer -\nField <code>GPIO7_LEVEL_LOW</code> reader -\nField <code>GPIO7_LEVEL_LOW</code> writer -\nInterrupt Force for proc1\nRegister <code>PROC1_INTF%s</code> reader\nRegister <code>PROC1_INTF%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBit 3\nBit 3\nBit 2\nBit 2\nBit 1\nBit 1\nBit 0\nBit 0\nBit 7\nBit 7\nBit 6\nBit 6\nBit 5\nBit 5\nBit 4\nBit 4\nBit 11\nBit 11\nBit 10\nBit 10\nBit 9\nBit 9\nBit 8\nBit 8\nBit 15\nBit 15\nBit 14\nBit 14\nBit 13\nBit 13\nBit 12\nBit 12\nBit 19\nBit 19\nBit 18\nBit 18\nBit 17\nBit 17\nBit 16\nBit 16\nBit 23\nBit 23\nBit 22\nBit 22\nBit 21\nBit 21\nBit 20\nBit 20\nBit 27\nBit 27\nBit 26\nBit 26\nBit 25\nBit 25\nBit 24\nBit 24\nBit 31\nBit 31\nBit 30\nBit 30\nBit 29\nBit 29\nBit 28\nBit 28\nCalls <code>U::from(self)</code>.\nField <code>GPIO0_EDGE_HIGH</code> reader -\nField <code>GPIO0_EDGE_LOW</code> reader -\nField <code>GPIO0_LEVEL_HIGH</code> reader -\nField <code>GPIO0_LEVEL_LOW</code> reader -\nField <code>GPIO1_EDGE_HIGH</code> reader -\nField <code>GPIO1_EDGE_LOW</code> reader -\nField <code>GPIO1_LEVEL_HIGH</code> reader -\nField <code>GPIO1_LEVEL_LOW</code> reader -\nField <code>GPIO2_EDGE_HIGH</code> reader -\nField <code>GPIO2_EDGE_LOW</code> reader -\nField <code>GPIO2_LEVEL_HIGH</code> reader -\nField <code>GPIO2_LEVEL_LOW</code> reader -\nField <code>GPIO3_EDGE_HIGH</code> reader -\nField <code>GPIO3_EDGE_LOW</code> reader -\nField <code>GPIO3_LEVEL_HIGH</code> reader -\nField <code>GPIO3_LEVEL_LOW</code> reader -\nField <code>GPIO4_EDGE_HIGH</code> reader -\nField <code>GPIO4_EDGE_LOW</code> reader -\nField <code>GPIO4_LEVEL_HIGH</code> reader -\nField <code>GPIO4_LEVEL_LOW</code> reader -")