searchState.loadedDescShard("stm32_metapac", 2, "USB_OTG_HS peripheral clock enable during CSleep mode\nUSB_OTG_HS peripheral clock enable during CSleep mode\nUSB_OTG_HS block reset\nUSBOTG 1 and 2 kernel clock source selection\nVREF Autonomous mode enable\nVREF peripheral clock enable\nVREF peripheral clock enable\nVREF peripheral clock enable during CSleep mode\nVREF peripheral clock enable during CSleep mode\nVREF block reset\nWWDG1 reset scope control\nWWDG2 reset scope control\nWWDG1 Clock Enable\nWWDG1 Clock Enable\nWWDG1 Clock Enable During CSleep Mode\nWWDG1 Clock Enable During CSleep Mode\nWindow Watchdog reset flag\nWindow Watchdog reset flag\nWWDG2 peripheral clock enable\nWWDG2 peripheral clock enable\nWWDG2 peripheral Clocks Enable During CSleep Mode\nWWDG2 peripheral Clocks Enable During CSleep Mode\nAPB clock selected as peripheral clock\ncsi_ker selected as peripheral clock\nCSI selected as peripheral clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\nCSI selected for micro-controller clock output\nCSI selected as PLL clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\nCSI selected as wake up clock from system Stop\nCSI selected as system clock\ncsi_ker selected as peripheral clock\ncsi_ker selected as peripheral clock\nThe HRTIM prescaler clock source is the CPU clock (c_ck)\nTimer kernel clock equal to 2x pclk by default\nTimer kernel clock equal to 4x pclk by default\nNo clock sent to DIVMx dividers and PLLs\nNo clock\nDisable the kernel clock\nsys_ck not divided\nNo division\nDivide by 1\nrcc_hclk not divided\nDivide by 10\nDivide by 11\nDivide by 12\nsys_ck divided by 128\nDivide by 13\nDivide by 14\nDivide by 15\nsys_ck divided by 16\nrcc_hclk divided by 16\nsys_ck divided by 2\nDivision by 2\nDivide by 2\nrcc_hclk divided by 2\nsys_ck divided by 256\nDivide by 3\nsys_ck divided by 4\nDivision by 4\nDivide by 4\nrcc_hclk divided by 4\nDivide by 5\nsys_ck divided by 512\nDivide by 6\nsys_ck divided by 64\nDivide by 7\nsys_ck divided by 8\nDivision by 8\nDivide by 8\nrcc_hclk divided by 8\nDivide by 9\nAHB3 selected as peripheral clock\nHigh driving capability\nHSE selected as peripheral clock\nHSE selected as peripheral clock\nHSE selected for micro-controller clock output\nHSE selected for micro-controller clock output\nHSE selected as PLL clock\nHSE oscillator clock divided by a prescaler used as RTC …\nHSE selected as peripheral clock\nHSE selected as peripheral clock\nHSE selected as system clock\nHSI selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nHSI selected for micro-controller clock output\nHSI selected as PLL clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nHSI selected as wake up clock from system Stop\nHSI selected as system clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nhsi_ker selected as peripheral clock\nHSI48 selected for micro-controller clock output\nHSI48 selected as peripheral clock\nHSI48 selected as peripheral clock\ni2s_ckin selected as peripheral clock\nI2S_CKIN selected as peripheral clock\nLow driving capability\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSE selected for micro-controller clock output\nLSE selected as peripheral clock\nLSE oscillator clock used as RTC clock\nLSE selected as peripheral clock\nLSE selected as peripheral clock\nLSI selected as peripheral clock\nLSI selected as peripheral clock\nLSI selected as peripheral clock\nLSI selected for micro-controller clock output\nLSI selected as peripheral clock\nLSI oscillator clock used as RTC clock\nMedium high driving capability\nMedium low driving capability\nVCO frequency range 150 to 420 MHz\npclk selected as peripheral clock\nrcc_pclk1 selected as peripheral clock\nrcc_pclk1 selected as peripheral clock\nrcc_pclk1 selected as peripheral clock\nrcc_pclk2 selected as peripheral clock\nrcc_pclk2 selected as peripheral clock\nrcc_pclk_d3 selected as peripheral clock\nrcc_pclk4 selected as peripheral clock\nrcc_pclk4 selected as peripheral clock\nrcc_pclk4 selected as peripheral clock\nPER selected as peripheral clock\nPER selected as peripheral clock\nPER selected as peripheral clock\nPER selected as peripheral clock\nPER selected as peripheral clock\nPER selected as peripheral clock\npll1_p selected for micro-controller clock output\nPLL1 selected as system clock\npll1_q selected as peripheral clock\npll1_q selected as peripheral clock\npll1_q selected for micro-controller clock output\npll1_q selected as peripheral clock\npll1_q selected as peripheral clock\npll1_q selected as peripheral clock\npll1_q selected as peripheral clock\npll1_q selected as peripheral clock\npll1_q selected as peripheral clock\npll2_p selected as peripheral clock\npll2_p selected as peripheral clock\npll2_p selected as peripheral clock\npll2_p selected for micro-controller clock output\npll2_p selected as peripheral clock\npll2_p selected as peripheral clock\npll2_q selected as peripheral clock\npll2_q selected as peripheral clock\npll2_q selected as peripheral clock\npll2_q selected as peripheral clock\npll2_q selected as peripheral clock\npll2_q selected as peripheral clock\npll2_r selected as peripheral clock\npll2_r selected as peripheral clock\npll2_r selected as peripheral clock\npll3_p selected as peripheral clock\npll3_p selected as peripheral clock\npll3_q selected as peripheral clock\npll3_q selected as peripheral clock\npll3_q selected as peripheral clock\npll3_q selected as peripheral clock\npll3_q selected as peripheral clock\npll3_q selected as peripheral clock\npll3_r selected as peripheral clock\npll3_r selected as peripheral clock\npll3_r selected as peripheral clock\npll3_r selected as peripheral clock\npll3_r selected as peripheral clock\npll3_r selected as peripheral clock\nFrequency is between 1 and 2 MHz\nFrequency is between 2 and 4 MHz\nFrequency is between 4 and 8 MHz\nFrequency is between 8 and 16 MHz\nSystem clock selected as peripheral clock\nSystem clock selected for micro-controller clock output\nThe HRTIM prescaler clock source is the same as other …\nVCO frequency range 192 to 836 MHz\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nRandom number generator\ncontrol register\ndata register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nstatus register\ncontrol register\nstatus register\nClock error current status\nClock error detection\nClock error interrupt status\nData ready\nReturns the argument unchanged.\nReturns the argument unchanged.\nInterrupt enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nRandom number generator enable\nSeed error current status\nSeed error interrupt status\nClock error current status\nClock error detection\nClock error interrupt status\nData ready\nInterrupt enable\nRandom number generator enable\nSeed error current status\nSeed error interrupt status\nReal-time clock\nAlarm register\nAlarm sub second register\nBackup register\nCalibration register\nControl register\nDate register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nInitialization and status register\nOption register\nPrescaler register\nShift control register\nSub second register\nTamper configuration register\nTime register\nTimestamp date register\nTimestamp sub second register\nTimestamp time register\nWrite protection register\nWakeup timer register\nAlarm register\nAlarm sub second register\nBackup register\nCalibration register\nControl register\nDate register\nInitialization and status register\nOption register\nPrescaler register\nShift control register\nSub second register\nTamper configuration register\nTime register\nTimestamp date register\nTimestamp sub second register\nTimestamp time register\nWrite protection register\nWakeup timer register\nAdd 1 hour (summer time change)\nAdd one second\nAlarm enable\nAlarm flag\nAlarm interrupt enable\nAlarm write enabled\nBKP\nBackup\nBypass the shadow registers\nCalibration minus\nIncrease frequency of RTC by 488.5 ppm\nUse a 16-second calibration cycle period\nUse an 8-second calibration cycle period\nCalibration output enable\nCalibration output selection\nDate tens in BCD format\nDate tens in BCD format\nDate tens in BCD format\nDate units or day in BCD format\nDate units in BCD format\nDate units in BCD format\nHour format\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nHour tens in BCD format\nHour tens in BCD format\nHour tens in BCD format\nHour units in BCD format\nHour units in BCD format\nHour units in BCD format\nEnter Initialization mode\nInitialization flag\nInitialization status flag\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nTimestamp on internal event enable\nInternal time-stamp flag\nWrite protection key\nMask the most-significant bits starting at this bit\nMinute tens in BCD format\nMinute tens in BCD format\nMinute tens in BCD format\nMinute units in BCD format\nMinute units in BCD format\nMinute units in BCD format\nAlarm seconds mask\nAlarm minutes mask\nAlarm hours mask\nAlarm date mask\nMonth tens in BCD format\nMonth tens in BCD format\nMonth units in BCD format\nMonth units in BCD format\nOutput selection\nAM/PM notation\nAM/PM notation\nAM/PM notation\nOutput polarity\nAsynchronous prescaler factor\nSynchronous prescaler factor\nRecalibration pending flag\nReference clock detection enable (50 or 60 Hz)\nRegisters synchronization flag\nRTC_ALARM output type on PC13\nRTC_OUT remap\nAdd 1 hour (summer time change)\nAdd one second\nAlarm enable\nAlarm flag\nAlarm interrupt enable\nAlarm write enabled\nBKP\nBackup\nBypass the shadow registers\nCalibration minus\nIncrease frequency of RTC by 488.5 ppm\nUse a 16-second calibration cycle period\nUse an 8-second calibration cycle period\nCalibration output enable\nCalibration output selection\nDate tens in BCD format\nDate tens in BCD format\nDate tens in BCD format\nDate units or day in BCD format\nDate units in BCD format\nDate units in BCD format\nHour format\nHour tens in BCD format\nHour tens in BCD format\nHour tens in BCD format\nHour units in BCD format\nHour units in BCD format\nHour units in BCD format\nEnter Initialization mode\nInitialization flag\nInitialization status flag\nTimestamp on internal event enable\nInternal time-stamp flag\nWrite protection key\nMask the most-significant bits starting at this bit\nMinute tens in BCD format\nMinute tens in BCD format\nMinute tens in BCD format\nMinute units in BCD format\nMinute units in BCD format\nMinute units in BCD format\nAlarm seconds mask\nAlarm minutes mask\nAlarm hours mask\nAlarm date mask\nMonth tens in BCD format\nMonth tens in BCD format\nMonth units in BCD format\nMonth units in BCD format\nOutput selection\nAM/PM notation\nAM/PM notation\nAM/PM notation\nOutput polarity\nAsynchronous prescaler factor\nSynchronous prescaler factor\nRecalibration pending flag\nReference clock detection enable (50 or 60 Hz)\nRegisters synchronization flag\nRTC_ALARM output type on PC13\nRTC_OUT remap\nShift operation pending\nSub seconds value\nSub second value\nSub second value\nSecond tens in BCD format\nSecond tens in BCD format\nSecond tens in BCD format\nSecond units in BCD format\nSecond units in BCD format\nSecond units in BCD format\nSubtract 1 hour (winter time change)\nSubtract a fraction of a second\nTamper detection enable\nTamper detection flag\nTamper filter count\nTamper sampling frequency\nTamper interrupt enable\nTamper precharge duration\nTamper pull-up disable\nActive level for tamper\nActivate timestamp on tamper detection event\nTamper interrupt enable\nTamper mask flag\nTamper no erase\nTimestamp enable\nTimestamp event active edge\nTimestamp flag\nTimestamp interrupt enable\nTimestamp overflow flag\nWeek day selection\nWeek day units\nWeek day units\nWakeup clock selection\nWakeup auto-reload value bits\nWakeup timer enable\nWakeup timer flag\nWakeup timer interrupt enable\nWakeup timer write enabled\nYear tens in BCD format\nYear units in BCD format\nShift operation pending\nSub seconds value\nSub second value\nSub second value\nSecond tens in BCD format\nSecond tens in BCD format\nSecond tens in BCD format\nSecond units in BCD format\nSecond units in BCD format\nSecond units in BCD format\nSubtract 1 hour (winter time change)\nSubtract a fraction of a second\nTamper detection enable\nTamper detection flag\nTamper filter count\nTamper sampling frequency\nTamper interrupt enable\nTamper precharge duration\nTamper pull-up disable\nActive level for tamper\nActivate timestamp on tamper detection event\nTamper interrupt enable\nTamper mask flag\nTamper no erase\nTimestamp enable\nTimestamp event active edge\nTimestamp flag\nTimestamp interrupt enable\nTimestamp overflow flag\nWeek day selection\nWeek day units\nWeek day units\nWakeup clock selection\nWakeup auto-reload value bits\nWakeup timer enable\nWakeup timer flag\nWakeup timer interrupt enable\nWakeup timer write enabled\nYear tens in BCD format\nYear units in BCD format\nAlarm A output enabled\nAlarm B output enabled\nAM or 24-hour format\nAM or 24-hour format\nAM/PM hour format\nCalibration output is 1 Hz (with default prescaler setting)\nCalibration output is 512 Hz (with default prescaler …\nck_spre (usually 1 Hz) clock is selected\nck_spre (usually 1 Hz) clock is selected and 2^16 is added …\n1 RTCCLK cycle\n2 RTCCLK cycles\n4 RTCCLK cycles\n8 RTCCLK cycles\nDU[3:0] represents the date units\nOutput disabled\nDisable precharge of RTC_TAMPx pins\nRTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)\nRTC/16 clock is selected\nRTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)\nRTC/2 clock is selected\nRTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)\nRTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)\nRTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)\nRTC/4 clock is selected\nRTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)\nRTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)\nRTC/8 clock is selected\nRTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)\nWhen CALW8 is set to ‘1’, the 8-second calibration …\nPrecharge RTC_TAMPx pins before sampling (enable internal …\nIf TAMPFLT = 00: RTC_TAMPx input staying high triggers a …\nRTC_TS input falling edge generates a time-stamp event\nThe pin is high when ALRAF/ALRBF/WUTF is asserted …\nTamper event is activated on edge of RTC_TAMPx input …\nOne RTCCLK pulse is effectively inserted every 2^11 pulses …\nThe pin is low when ALRAF/ALRBF/WUTF is asserted …\nNo RTCCLK pulses are added\nDate/day don’t care in Alarm comparison\nThe RECALPF status flag is automatically set to 1 when …\nPM\nPM\nIf TAMPFLT = 00: RTC_TAMPx input rising edge triggers a …\nRTC_TS input rising edge generates a time-stamp event\nTamper event is activated after 2 consecutive samples at …\nTamper event is activated after 4 consecutive samples at …\nTamper event is activated after 8 consecutive samples at …\nWhen CALW16 is set to ‘1’, the 16-second calibration …\nAlarm set if the date/day match\n24 hour/day format\nWakeup output enabled\nDU[3:0] represents the week day. DT[1:0] is don’t care\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, …\nSerial audio interface\nCluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, …\nClear flag register\nConfiguration register 1\nConfiguration register 2\nData register\nThis register has no meaning in AC97 and SPDIF audio …\nReturns the argument unchanged.\nReturns the argument unchanged.\nGlobal configuration register\nInterrupt mask register 2\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nPDM control register\nPDM delay register\nThis register has no meaning in AC97 and SPDIF audio …\nStatus register\nClear flag register\nConfiguration register 1\nConfiguration register 2\nData register\nThis register has no meaning in AC97 and SPDIF audio …\nGlobal configuration register\nInterrupt mask register 2\nPDM control register\nPDM delay register\nThis register has no meaning in AC97 and SPDIF audio …\nStatus register\nAnticipated frame synchronization detection. This bit is …\nAnticipated frame synchronization detection interrupt …\nClear anticipated frame synchronization detection flag. …\nClear Codec not ready flag. This bit is write only. …\nClock enable of bitstream clock number 1\nClock enable of bitstream clock number 2\nClock enable of bitstream clock number 3\nClock enable of bitstream clock number 4\nClock strobing edge. This bit is set and cleared by …\nClear late frame synchronization detection flag. This bit …\nMute detection flag. This bit is write only. Programming …\nCodec not ready. This bit is read only. This bit is used …\nCodec not ready interrupt enable (AC97). This bit is set …\nCompanding mode. These bits are set and cleared by …\nClear overrun / underrun. This bit is write only. …\nComplement bit. This bit is set and cleared by software. …\nClear wrong clock configuration flag. This bit is write …\nData A write to this register loads the FIFO provided the …\nDelay line adjust for first microphone of pair 1\nDelay line adjust for second microphone of pair 1\nDelay line for first microphone of pair 2\nDelay line for second microphone of pair 2\nDelay line for first microphone of pair 3\nDelay line for second microphone of pair 3\nDelay line for first microphone of pair 4\nDelay line for second microphone of pair 4\nDMA enable. This bit is set and cleared by software. Note: …\nData size. These bits are set and cleared by software. …\nFirst bit offset These bits are set and cleared by …\nFIFO flush. This bit is set by software. It is always read …\nFIFO level threshold. This bit is read only. The FIFO …\nFIFO request. This bit is read only. The request depends …\nFIFO request interrupt enable. This bit is set and cleared …\nFrame length. These bits are set and cleared by software. …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nFrame synchronization active level length. These bits are …\nFrame synchronization definition. This bit is set and …\nFrame synchronization offset. This bit is set and cleared …\nFrame synchronization polarity. This bit is set and …\nFIFO threshold. This bit is set and cleared by software.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nLate frame synchronization detection. This bit is read …\nLate frame synchronization detection interrupt enable. …\nLeast significant bit first. This bit is set and cleared …\nMaster clock divider. These bits are set and cleared by …\nMaster clock generation enable\nNumber of microphones\nSAIx audio block mode immediately\nMono mode. This bit is set and cleared by software. It is …\nMute. This bit is set and cleared by software. It is …\nMute counter. These bits are set and cleared by software. …\nMute detection. This bit is read only. This flag is set if …\nMute detection interrupt enable. This bit is set and …\nMute value. This bit is set and cleared by software.It …\nNumber of slots in an audio frame. These bits are set and …\nNo fixed divider between MCLK and FS\nOversampling ratio for master clock\nOutput drive. This bit is set and cleared by software. …\nOverrun / underrun. This bit is read only. The overrun and …\nOverrun/underrun interrupt enable. This bit is set and …\nPDM enable\nProtocol configuration. These bits are set and cleared by …\nAudio block enable where x is A or B. This bit is set by …\nAnticipated frame synchronization detection. This bit is …\nAnticipated frame synchronization detection interrupt …\nClear anticipated frame synchronization detection flag. …\nClear Codec not ready flag. This bit is write only. …\nClock enable of bitstream clock number 1\nClock enable of bitstream clock number 2\nClock enable of bitstream clock number 3\nClock enable of bitstream clock number 4\nClock strobing edge. This bit is set and cleared by …\nClear late frame synchronization detection flag. This bit …\nMute detection flag. This bit is write only. Programming …\nCodec not ready. This bit is read only. This bit is used …\nCodec not ready interrupt enable (AC97). This bit is set …\nCompanding mode. These bits are set and cleared by …\nClear overrun / underrun. This bit is write only. …\nComplement bit. This bit is set and cleared by software. …\nClear wrong clock configuration flag. This bit is write …\nData A write to this register loads the FIFO provided the …\nDelay line adjust for first microphone of pair 1\nDelay line adjust for second microphone of pair 1\nDelay line for first microphone of pair 2\nDelay line for second microphone of pair 2\nDelay line for first microphone of pair 3\nDelay line for second microphone of pair 3\nDelay line for first microphone of pair 4\nDelay line for second microphone of pair 4\nDMA enable. This bit is set and cleared by software. Note: …\nData size. These bits are set and cleared by software. …\nFirst bit offset These bits are set and cleared by …\nFIFO flush. This bit is set by software. It is always read …\nFIFO level threshold. This bit is read only. The FIFO …\nFIFO request. This bit is read only. The request depends …\nFIFO request interrupt enable. This bit is set and cleared …\nFrame length. These bits are set and cleared by software. …\nFrame synchronization active level length. These bits are …\nFrame synchronization definition. This bit is set and …\nFrame synchronization offset. This bit is set and cleared …\nFrame synchronization polarity. This bit is set and …\nFIFO threshold. This bit is set and cleared by software.\nLate frame synchronization detection. This bit is read …\nLate frame synchronization detection interrupt enable. …\nLeast significant bit first. This bit is set and cleared …\nMaster clock divider. These bits are set and cleared by …\nMaster clock generation enable\nNumber of microphones\nSAIx audio block mode immediately\nMono mode. This bit is set and cleared by software. It is …\nMute. This bit is set and cleared by software. It is …\nMute counter. These bits are set and cleared by software. …\nMute detection. This bit is read only. This flag is set if …\nMute detection interrupt enable. This bit is set and …\nMute value. This bit is set and cleared by software.It …\nNumber of slots in an audio frame. These bits are set and …\nNo fixed divider between MCLK and FS\nOversampling ratio for master clock\nOutput drive. This bit is set and cleared by software. …\nOverrun / underrun. This bit is read only. The overrun and …\nOverrun/underrun interrupt enable. This bit is set and …\nPDM enable\nProtocol configuration. These bits are set and cleared by …\nAudio block enable where x is A or B. This bit is set by …\nSlot enable. These bits are set and cleared by software. …\nSlot size This bits is set and cleared by software. The …\nSynchronization enable. These bits are set and cleared by …\nSynchronization inputs\nSynchronization outputs These bits are set and cleared by …\nTristate management on data line. This bit is set and …\nWrong clock configuration flag. This bit is read only. …\nWrong clock configuration interrupt enable. This bit is …\nSlot enable. These bits are set and cleared by software. …\nSlot size This bits is set and cleared by software. The …\nSynchronization enable. These bits are set and cleared by …\nSynchronization inputs\nSynchronization outputs These bits are set and cleared by …\nTristate management on data line. This bit is set and …\nWrong clock configuration flag. This bit is read only. …\nWrong clock configuration interrupt enable. This bit is …\nAC’97 protocol\nActive slot\nA-Law algorithm\naudio sub-block in asynchronous mode\nFS is asserted one bit before the first bit of the slot 0\n10 bits\n16 bits\n16-bit\n20 bits\n24 bits\n32 bits\n32-bit\n8 bits\nClock configuration is correct\nThe slot size is equivalent to the data size (specified in …\nFIFO empty\nFIFO empty\naudio sub-block is synchronous with an external SAI …\nData strobing edge is falling edge of SCK\nFS is active low (falling edge)\nFree protocol. Free protocol allows to use the powerful …\nFIFO full\nFIFO full\nAudio block output driven immediately after the setting of …\nInactive slot\naudio sub-block is synchronous with the other internal …\nData are transferred with LSB first\nMCLK output is enabled. Forces the ratio between FS and …\nMaster receiver\nMaster transmitter\nMono mode\nData are transferred with MSB first\nμ-Law algorithm\nNo companding algorithm\nMCLK output enable set by the MCKEN bit (where present, …\nExternal AC’97 Codec is not ready\n1’s complement representation\nFS is asserted on the first bit of the slot 0\nAudio block output driven when SAIEN is set\nFIFO &lt;= 1⁄4 but not empty\n1⁄4 FIFO\n1⁄4 &lt; FIFO &lt;= 1⁄2\n1⁄2 FIFO\n1⁄2 &lt; FIFO &lt;= 3⁄4\n3⁄4 FIFO\n3⁄4 &lt; FIFO but not full\nExternal AC’97 Codec is ready\nData strobing edge is rising edge of SCK\nFS is active high (rising edge)\nLast values are sent during the mute mode\nBit value 0 is sent during the mute mode\nSlave receiver\nSlave transmitter\nSPDIF protocol\nStereo mode\n2’s complement representation\nClock configuration does not respect the rule concerning …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSDMMC\nThe SDMMC_ACKTIMER register contains the acknowledgment …\nThe SDMMC_ARGR register contains a 32-bit command …\nThe SDMMC_CLKCR register controls the SDMMC_CK output …\nThe SDMMC_CMDR register contains the command index and …\nThe SDMMC_DCNTR register loads the value from the data …\nThe SDMMC_DCTRL register control the data path state …\nThe SDMMC_DLENR register contains the number of data bytes …\nThe SDMMC_DTIMER register contains the data timeout …\nThe receive and transmit FIFOs can be only read or written …\nReturns the argument unchanged.\nThe SDMMC_ICR register is a write-only register. Writing a …\nSDMMC IP identification register\nThe SDMMC_IDMABASE0R register contains the memory buffer …\nThe SDMMC_IDMABASE1R register contains the double buffer …\nThe SDMMC_IDMABSIZER register contains the buffers size …\nThe receive and transmit FIFOs can be read or written as …\nCalls <code>U::from(self)</code>.\nThe interrupt mask register determines which status flags …\nSDMMC power control register\nSDMMC command response register\nThe SDMMC_RESP1/2/3/4R registers contain the status of a …\nThe SDMMC_STAR register is a read-only register. It …\nSDMMC IP version register\nThe SDMMC_ACKTIMER register contains the acknowledgment …\nThe SDMMC_ARGR register contains a 32-bit command …\nThe SDMMC_CLKCR register controls the SDMMC_CK output …\nThe SDMMC_CMDR register contains the command index and …\nThe SDMMC_DCNTR register loads the value from the data …\nThe SDMMC_DCTRL register control the data path state …\nThe SDMMC_DLENR register contains the number of data bytes …\nThe SDMMC_DTIMER register contains the data timeout …\nThe receive and transmit FIFOs can be only read or written …\nThe SDMMC_ICR register is a write-only register. Writing a …\nSDMMC IP identification register\nThe SDMMC_IDMABASE0R register contains the memory buffer …\nThe SDMMC_IDMABASE1R register contains the double buffer …\nThe SDMMC_IDMABSIZER register contains the buffers size …\nThe receive and transmit FIFOs can be read or written as …\nThe interrupt mask register determines which status flags …\nSDMMC power control register\nSDMMC command response register\nThe SDMMC_RESP1/2/3/4R registers contain the status of a …\nThe SDMMC_STAR register is a read-only register. It …\nSDMMC IP version register\nBoot acknowledgment received (boot acknowledgment check …\nACKFAIL flag clear bit Set by software to clear the …\nAcknowledgment Fail interrupt enable Set and cleared by …\nBoot acknowledgment timeout period This bit can only be …\nBoot acknowledgment timeout. Interrupt flag is cleared by …\nACKTIMEOUT flag clear bit Set by software to clear the …\nAcknowledgment timeout interrupt enable Set and cleared by …\nEnable the reception of the boot acknowledgment. This bit …\nEnable boot mode procedure.\nSelect the boot mode procedure to be used. This bit can …\nBus speed mode selection between DS, HS, SDR12, SDR25 and …\nInverted value of SDMMC_D0 line (Busy), sampled at the end …\nend of SDMMC_D0 Busy following a CMD response detected. …\nBUSYD0END flag clear bit Set by software to clear the …\nBUSYD0END interrupt enable Set and cleared by software to …\nsee Table 432\nCommand response received (CRC check failed). Interrupt …\nCCRCFAIL flag clear bit Set by software to clear the …\nCommand CRC fail interrupt enable Set and cleared by …\nSDMMC_CK stopped in Voltage switch procedure. Interrupt …\nCKSTOP flag clear bit Set by software to clear the CKSTOP …\nVoltage Switch clock stopped interrupt enable Set and …\nClock divide factor This bit can only be written when the …\nCommand argument. These bits can only be written by …\nCommand index. This bit can only be written by firmware …\nCommand response received (CRC check passed, or no CRC). …\nCMDREND flag clear bit Set by software to clear the …\nCommand response received interrupt enable Set and cleared …\nCommand sent (no response required). Interrupt flag is …\nCMDSENT flag clear bit Set by software to clear the …\nCommand sent interrupt enable Set and cleared by software …\nThe CPSM treats the command as a Stop Transmission command …\nThe CPSM treats the command as a Suspend or Resume command …\nThe CPSM treats the command as a data transfer command, …\nCommand path state machine active, i.e. not in Idle state. …\nCommand path state machine (CPSM) Enable bit This bit is …\nCommand response timeout. Interrupt flag is cleared by …\nCTIMEOUT flag clear bit Set by software to clear the …\nCommand timeout interrupt enable Set and cleared by …\nData transfer aborted by CMD12. Interrupt flag is cleared …\nDABORT flag clear bit Set by software to clear the DABORT …\nData transfer aborted interrupt enable Set and cleared by …\nData count value When read, the number of remaining data …\nData transfer ended correctly. (data counter, DATACOUNT is …\nDATAEND flag clear bit Set by software to clear the …\nData end interrupt enable Set and cleared by software to …\nData length value This register can only be written by …\nData and R1b busy timeout period This bit can only be …\nData block sent/received. (CRC check passed) and DPSM …\nDBCKEND flag clear bit Set by software to clear the …\nData block end interrupt enable Set and cleared by …\nData block size This bit can only be written by firmware …\nData block sent/received (CRC check failed). Interrupt …\nDCRCFAIL flag clear bit Set by software to clear the …\nData CRC fail interrupt enable Set and cleared by software …\nData rate signaling selection This bit can only be written …\nData transfer Hold. Interrupt flag is cleared by writing …\nDHOLD flag clear bit Set by software to clear the DHOLD …\nData hold interrupt enable Set and cleared by software to …\nData and command direction signals polarity selection. …\nData path state machine active, i.e. not in Idle state. …\nData transfer direction selection This bit can only be …\nData transfer enable bit This bit can only be written by …\nHold new data block transmission and reception in the …\nData timeout. Interrupt flag is cleared by writing …\nDTIMEOUT flag clear bit Set by software to clear the …\nData timeout interrupt enable Set and cleared by software …\nData transfer mode selection. This bit can only be written …\nReceive and transmit FIFO data This register can only be …\nFIFO reset, will flush any remaining data. This bit can …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nHardware flow control enable This bit can only be written …\nDouble buffer mode active buffer indication This bit can …\nBuffer 0 memory base address bits [31:2], shall be word …\nBuffer 1 memory base address, shall be word aligned (bit …\nBuffer mode selection. This bit can only be written by …\nNumber of transfers per buffer. This 8-bit value shall be …\nIDMA buffer transfer complete. interrupt flag is cleared …\nIDMA buffer transfer complete clear bit Set by software to …\nIDMA buffer transfer complete interrupt enable Set and …\nIDMA enable This bit can only be written by firmware when …\nIDMA transfer error. Interrupt flag is cleared by writing …\nIDMA transfer error clear bit Set by software to clear the …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSDMMC IP identification.\nIP major revision number.\nIP minor revision number.\nSDMMC_CK dephasing selection bit for data and Command. …\nSDMMC state control bits. These bits can only be written …\nPower saving configuration bit This bit can only be …\nResponse command index\nRead wait mode. This bit can only be written by firmware …\nRead wait start. If this bit is set, read wait operation …\nRead wait stop This bit is written by firmware and auto …\nReceive FIFO empty This is a hardware status flag only, …\nReceive FIFO full This bit is cleared when one FIFO …\nRx FIFO full interrupt enable Set and cleared by software …\nReceive FIFO half full There are at least half the number …\nRx FIFO half full interrupt enable Set and cleared by …\nReceived FIFO overrun error or IDMA write transfer error. …\nRXOVERR flag clear bit Set by software to clear the …\nRx FIFO overrun error interrupt enable Set and cleared by …\nSD I/O interrupt enable functions This bit can only be …\nSDIO interrupt received. Interrupt flag is cleared by …\nSDIOIT flag clear bit Set by software to clear the SDIOIT …\nSDIO mode interrupt received interrupt enable Set and …\nReceive clock selection. These bits can only be written …\nBoot acknowledgment received (boot acknowledgment check …\nACKFAIL flag clear bit Set by software to clear the …\nAcknowledgment Fail interrupt enable Set and cleared by …\nBoot acknowledgment timeout period This bit can only be …\nBoot acknowledgment timeout. Interrupt flag is cleared by …\nACKTIMEOUT flag clear bit Set by software to clear the …\nAcknowledgment timeout interrupt enable Set and cleared by …\nEnable the reception of the boot acknowledgment. This bit …\nEnable boot mode procedure.\nSelect the boot mode procedure to be used. This bit can …\nBus speed mode selection between DS, HS, SDR12, SDR25 and …\nInverted value of SDMMC_D0 line (Busy), sampled at the end …\nend of SDMMC_D0 Busy following a CMD response detected. …\nBUSYD0END flag clear bit Set by software to clear the …\nBUSYD0END interrupt enable Set and cleared by software to …\nsee Table 432\nCommand response received (CRC check failed). Interrupt …\nCCRCFAIL flag clear bit Set by software to clear the …\nCommand CRC fail interrupt enable Set and cleared by …\nSDMMC_CK stopped in Voltage switch procedure. Interrupt …\nCKSTOP flag clear bit Set by software to clear the CKSTOP …\nVoltage Switch clock stopped interrupt enable Set and …\nClock divide factor This bit can only be written when the …\nCommand argument. These bits can only be written by …\nCommand index. This bit can only be written by firmware …\nCommand response received (CRC check passed, or no CRC). …\nCMDREND flag clear bit Set by software to clear the …\nCommand response received interrupt enable Set and cleared …\nCommand sent (no response required). Interrupt flag is …\nCMDSENT flag clear bit Set by software to clear the …\nCommand sent interrupt enable Set and cleared by software …\nThe CPSM treats the command as a Stop Transmission command …\nThe CPSM treats the command as a Suspend or Resume command …\nThe CPSM treats the command as a data transfer command, …\nCommand path state machine active, i.e. not in Idle state. …\nCommand path state machine (CPSM) Enable bit This bit is …\nCommand response timeout. Interrupt flag is cleared by …\nCTIMEOUT flag clear bit Set by software to clear the …\nCommand timeout interrupt enable Set and cleared by …\nData transfer aborted by CMD12. Interrupt flag is cleared …\nDABORT flag clear bit Set by software to clear the DABORT …\nData transfer aborted interrupt enable Set and cleared by …\nData count value When read, the number of remaining data …\nData transfer ended correctly. (data counter, DATACOUNT is …\nDATAEND flag clear bit Set by software to clear the …\nData end interrupt enable Set and cleared by software to …\nData length value This register can only be written by …\nData and R1b busy timeout period This bit can only be …\nData block sent/received. (CRC check passed) and DPSM …\nDBCKEND flag clear bit Set by software to clear the …\nData block end interrupt enable Set and cleared by …\nData block size This bit can only be written by firmware …\nData block sent/received (CRC check failed). Interrupt …\nDCRCFAIL flag clear bit Set by software to clear the …\nData CRC fail interrupt enable Set and cleared by software …\nData rate signaling selection This bit can only be written …\nData transfer Hold. Interrupt flag is cleared by writing …\nDHOLD flag clear bit Set by software to clear the DHOLD …\nData hold interrupt enable Set and cleared by software to …\nData and command direction signals polarity selection. …\nData path state machine active, i.e. not in Idle state. …\nData transfer direction selection This bit can only be …\nData transfer enable bit This bit can only be written by …\nHold new data block transmission and reception in the …\nData timeout. Interrupt flag is cleared by writing …\nDTIMEOUT flag clear bit Set by software to clear the …\nData timeout interrupt enable Set and cleared by software …\nData transfer mode selection. This bit can only be written …\nReceive and transmit FIFO data This register can only be …\nFIFO reset, will flush any remaining data. This bit can …\nHardware flow control enable This bit can only be written …\nDouble buffer mode active buffer indication This bit can …\nBuffer 0 memory base address bits [31:2], shall be word …\nBuffer 1 memory base address, shall be word aligned (bit …\nBuffer mode selection. This bit can only be written by …\nNumber of transfers per buffer. This 8-bit value shall be …\nIDMA buffer transfer complete. interrupt flag is cleared …\nIDMA buffer transfer complete clear bit Set by software to …\nIDMA buffer transfer complete interrupt enable Set and …\nIDMA enable This bit can only be written by firmware when …\nIDMA transfer error. Interrupt flag is cleared by writing …\nIDMA transfer error clear bit Set by software to clear the …\nSDMMC IP identification.\nIP major revision number.\nIP minor revision number.\nSDMMC_CK dephasing selection bit for data and Command. …\nSDMMC state control bits. These bits can only be written …\nPower saving configuration bit This bit can only be …\nResponse command index\nRead wait mode. This bit can only be written by firmware …\nRead wait start. If this bit is set, read wait operation …\nRead wait stop This bit is written by firmware and auto …\nReceive FIFO empty This is a hardware status flag only, …\nReceive FIFO full This bit is cleared when one FIFO …\nRx FIFO full interrupt enable Set and cleared by software …\nReceive FIFO half full There are at least half the number …\nRx FIFO half full interrupt enable Set and cleared by …\nReceived FIFO overrun error or IDMA write transfer error. …\nRXOVERR flag clear bit Set by software to clear the …\nRx FIFO overrun error interrupt enable Set and cleared by …\nSD I/O interrupt enable functions This bit can only be …\nSDIO interrupt received. Interrupt flag is cleared by …\nSDIOIT flag clear bit Set by software to clear the SDIOIT …\nSDIO mode interrupt received interrupt enable Set and …\nReceive clock selection. These bits can only be written …\nTransmit FIFO empty This bit is cleared when one FIFO …\nTx FIFO empty interrupt enable Set and cleared by software …\nTransmit FIFO full This is a hardware status flag only, …\nTransmit FIFO half empty At least half the number of words …\nTx FIFO half empty interrupt enable Set and cleared by …\nTransmit FIFO underrun error or IDMA read transfer error. …\nTXUNDERR flag clear bit Set by software to clear TXUNDERR …\nTx FIFO underrun error interrupt enable Set and cleared by …\nVoltage switch critical timing section completion. …\nVSWEND flag clear bit Set by software to clear the VSWEND …\nVoltage switch critical timing section completion …\nVoltage switch sequence start. This bit is used to start …\nVoltage switch procedure enable. This bit can only be …\nCPSM waits for interrupt request. If this bit is set, the …\nCPSM Waits for end of data transfer (CmdPend internal …\nWait for response bits. This bit can only be written by …\nWide bus mode enable bit This bit can only be written when …\nTransmit FIFO empty This bit is cleared when one FIFO …\nTx FIFO empty interrupt enable Set and cleared by software …\nTransmit FIFO full This is a hardware status flag only, …\nTransmit FIFO half empty At least half the number of words …\nTx FIFO half empty interrupt enable Set and cleared by …\nTransmit FIFO underrun error or IDMA read transfer error. …\nTXUNDERR flag clear bit Set by software to clear TXUNDERR …\nTx FIFO underrun error interrupt enable Set and cleared by …\nVoltage switch critical timing section completion. …\nVSWEND flag clear bit Set by software to clear the VSWEND …\nVoltage switch critical timing section completion …\nVoltage switch sequence start. This bit is used to start …\nVoltage switch procedure enable. This bit can only be …\nCPSM waits for interrupt request. If this bit is set, the …\nCPSM Waits for end of data transfer (CmdPend internal …\nWait for response bits. This bit can only be written by …\nWide bus mode enable bit This bit can only be written when …\nSerial peripheral interface\nconfiguration register 1\nconfiguration register 2\ncontrol register 1\ncontrol register 2\nPolynomial Register\nReturns the argument unchanged.\nInterrupt Enable Register\nInterrupt/Status Flags Clear Register\nCalls <code>U::from(self)</code>.\nReceiver CRC Register\nReceive Data Register\nStatus Register\nTransmitter CRC Register\nTransmit Data Register\nUnderrun Data Register\nconfiguration register 1\nconfiguration register 2\ncontrol register 1\ncontrol register 2\nPolynomial Register\nInterrupt Enable Register\nInterrupt/Status Flags Clear Register\nReceiver CRC Register\nReceive Data Register\nStatus Register\nTransmitter CRC Register\nTransmit Data Register\nUnderrun Data Register\nAlternate function always control GPIOs\nSPI Communication Mode\nClock phase\nClock polarity\nFull size (33-bit or 17-bit) CRC polynomial is used\nCRC Error\nCRC Error flag clear\nCRC Interrupt enable\nHardware CRC computation enable\nCRC polynomial register\nLength of CRC frame to be transacted and compared\nMaster transfer start\nMaster SUSPend request\nNumber of data frames remaining in current TSIZE session\nNumber of bits in at single SPI data frame\nDuplex Packet\nDXP interrupt enabled\nEnd Of Transfer\nEnd Of Transfer flag clear\nEOT, SUSP and TXC interrupt enable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nthreshold level\nRx/Tx direction at Half-duplex mode\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nLocking the AF configuration of associated IOs\nSwap functionality of MISO and MOSI pins\nData frame format\nMaster automatic SUSP in Receive mode\nSPI Master\nMaster baud rate\nMaster Inter-Data Idleness\nMode Fault\nMode Fault flag clear\nMode Fault interrupt enable\nMaster SS Idleness\nOverrun\nOverrun flag clear\nOVR interrupt enable\nCRC calculation initialization pattern control for receiver\nCRC register for receiver\nRx DMA stream enable\nReceive data register\nRx-Packet available\nRXP Interrupt Enable\nRxFIFO Packing LeVeL\nRxFIFO Word Not Empty\nAlternate function always control GPIOs\nSPI Communication Mode\nClock phase\nClock polarity\nFull size (33-bit or 17-bit) CRC polynomial is used\nCRC Error\nCRC Error flag clear\nCRC Interrupt enable\nHardware CRC computation enable\nCRC polynomial register\nLength of CRC frame to be transacted and compared\nMaster transfer start\nMaster SUSPend request\nNumber of data frames remaining in current TSIZE session\nNumber of bits in at single SPI data frame\nDuplex Packet\nDXP interrupt enabled\nEnd Of Transfer\nEnd Of Transfer flag clear\nEOT, SUSP and TXC interrupt enable\nthreshold level\nRx/Tx direction at Half-duplex mode\nLocking the AF configuration of associated IOs\nSwap functionality of MISO and MOSI pins\nData frame format\nMaster automatic SUSP in Receive mode\nSPI Master\nMaster baud rate\nMaster Inter-Data Idleness\nMode Fault\nMode Fault flag clear\nMode Fault interrupt enable\nMaster SS Idleness\nOverrun\nOverrun flag clear\nOVR interrupt enable\nCRC calculation initialization pattern control for receiver\nCRC register for receiver\nRx DMA stream enable\nReceive data register\nRx-Packet available\nRXP Interrupt Enable\nRxFIFO Packing LeVeL\nRxFIFO Word Not Empty\nSerial Protocol\nSerial Peripheral Enable\nInternal SS signal input level\nSS input/output polarity\nSoftware management of SS signal input\nSS output enable\nSS output management in master mode\nSUSPend\nSUSPend flag clear\nCRC calculation initialization pattern control for …\nTI frame format error\nTI frame format error flag clear\nTIFRE interrupt enable\nNumber of data transfer extension to be reload into TSIZE …\nAdditional number of SPI data to be transacted was reload\nTSERFC flag clear\nAdditional number of transactions reload interrupt enable\nNumber of data at current transfer\nTxFIFO transmission complete\nCRC register for transmitter\nTx DMA stream enable\nTransmit data register\nTx-Packet space available\nTXP interrupt enable\nTransmission Transfer Filled\nTransmission Transfer Filled flag clear\nTXTFIE interrupt enable\nUnderrun at slave transmission mode\nUnderrun flag clear\nBehavior of slave transmitter at underrun condition\nDetection of underrun condition at slave transmitter\nData at slave underrun condition\nUDR interrupt enable\nSerial Protocol\nSerial Peripheral Enable\nInternal SS signal input level\nSS input/output polarity\nSoftware management of SS signal input\nSS output enable\nSS output management in master mode\nSUSPend\nSUSPend flag clear\nCRC calculation initialization pattern control for …\nTI frame format error\nTI frame format error flag clear\nTIFRE interrupt enable\nNumber of data transfer extension to be reload into TSIZE …\nAdditional number of SPI data to be transacted was reload\nTSERFC flag clear\nAdditional number of transactions reload interrupt enable\nNumber of data at current transfer\nTxFIFO transmission complete\nCRC register for transmitter\nTx DMA stream enable\nTransmit data register\nTx-Packet space available\nTXP interrupt enable\nTransmission Transfer Filled\nTransmission Transfer Filled flag clear\nTXTFIE interrupt enable\nUnderrun at slave transmission mode\nUnderrun flag clear\nBehavior of slave transmitter at underrun condition\nDetection of underrun condition at slave transmitter\nData at slave underrun condition\nUDR interrupt enable\nHigh level is active for SS signal\nLow level is active for SS signal\nAll ones RX CRC initialization pattern\nAll ones TX CRC initialization pattern\nAll zeros RX CRC initialization pattern\nAll zeros TX CRC initialization pattern\nSS is asserted until data transfer complete\nAt least 32-bit data frame received\nSlave sends a constant underrun pattern\nf_spi_ker_ck / 128\nf_spi_ker_ck / 16\nf_spi_ker_ck / 2\nf_spi_ker_ck / 256\nf_spi_ker_ck / 32\nf_spi_ker_ck / 4\nf_spi_ker_ck / 64\nf_spi_ker_ck / 8\n8 frames\n11 frames\nUnderrun is detected at end of last data frame\n15 frames\nThe first clock transition is the first data capture edge\n5 frames\n4 frames\n14 frames\nFull duplex\nHalf duplex\nCK to 1 when idle\nCK to 0 when idle\nLess than 32-bit data frame received\nData is transmitted/received with the LSB first\nMaster configuration\nMotorola SPI protocol\nData is transmitted/received with the MSB first\n9 frames\nData frames interleaved with SS not asserted during MIDI\n1 frame\nOne frame beyond packing ratio available\nSimplex receiver only\nReceiver in half duplex mode\nSlave repeats last received data frame from master\nSlave repeats last transmitted data frame\nThe second clock transition is the first data capture edge\n7 frames\n6 frames\n16 frames\nSlave configuration\nUnderrun is detected at begin of data frame\nUnderrun is detected at begin of active SS signal\n10 frames\n13 frames\n3 frames\nThree frame beyond packing ratio available\nTI SPI protocol\nSimplex transmitter only\nTransmitter in half duplex mode\n12 frames\n2 frames\nTwo frame beyond packing ratio available\nZero frames beyond packing ratio available\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nSystem configuration controller\nSYSCFG compensation cell code register\ncompensation cell control/status register\nSYSCFG compensation cell value register\nexternal interrupt configuration register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nSYSCFG package register\nperipheral mode configuration register\nSYSCFG user register 0\nSYSCFG user register 10\nSYSCFG user register 11\nSYSCFG user register 12\nSYSCFG user register 13\nSYSCFG user register 14\nSYSCFG user register 15\nSYSCFG user register 16\nSYSCFG user register 17\nSYSCFG user register 2\nSYSCFG user register 3\nSYSCFG user register 4\nSYSCFG user register 5\nSYSCFG user register 6\nSYSCFG user register 7\nSYSCFG user register 8\nSYSCFG user register 9\nSYSCFG compensation cell code register\ncompensation cell control/status register\nSYSCFG compensation cell value register\nexternal interrupt configuration register 2\nSYSCFG package register\nperipheral mode configuration register\nSYSCFG user register 0\nSYSCFG user register 10\nSYSCFG user register 11\nSYSCFG user register 12\nSYSCFG user register 13\nSYSCFG user register 14\nSYSCFG user register 15\nSYSCFG user register 16\nSYSCFG user register 17\nSYSCFG user register 2\nSYSCFG user register 3\nSYSCFG user register 4\nSYSCFG user register 5\nSYSCFG user register 6\nSYSCFG user register 7\nSYSCFG user register 8\nSYSCFG user register 9\nBank Swap\nBooster Enable\nAnalog switch supply voltage selection\nBoot Address 0\nBoot Address 1\nBOR_LVL Brownout Reset Threshold Level\nCode selection\nD1 Standby reset\nD1 Stop Reset\nenable\nEthernet PHY Interface Selection\nEXTI x configuration (x = 4 to 7)\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nFreeze independent watchdog in Standby mode\nFreeze independent watchdog in Stop mode\nHigh-speed at low-voltage\nI2C1 Fm+\nI2C2 Fm+\nI2C3 Fm+\nI2C4 Fm+\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nI/O high speed / low voltage\nIndependent Watchdog 1 mode\nMass Erase Protected Area Disabled for bank 1\nMass erase protected area disabled for bank 2\nMass erase secured area disabled for bank 1\nMass erase secured area disabled for bank 2\nNMOS compensation code\nNMOS compensation value\nPA0 Switch Open\nPA1 Switch Open\nProtected area start address for bank 1\nProtected area start address for bank 2\nProtected area end address for bank 1\nProtected area end address for bank 2\nPB(6) Fm+\nPB(7) Fast Mode Plus\nPB(8) Fast Mode Plus\nPB(9) Fm+\nPC2 Switch Open\nPC3 Switch Open\nPMOS compensation code\nPMOS compensation value\nPackage\nPrivate key programmed\nReadout protection\nCompensation cell ready flag\nSecured area start address for bank 1\nSecured area start address for bank 2\nSecured area end address for bank 1\nSecured area end address for bank 2\nSecured DTCM RAM Size\nSecure mode\nBank Swap\nBooster Enable\nAnalog switch supply voltage selection\nBoot Address 0\nBoot Address 1\nBOR_LVL Brownout Reset Threshold Level\nCode selection\nD1 Standby reset\nD1 Stop Reset\nenable\nEthernet PHY Interface Selection\nEXTI x configuration (x = 4 to 7)\nFreeze independent watchdog in Standby mode\nFreeze independent watchdog in Stop mode\nHigh-speed at low-voltage\nI2C1 Fm+\nI2C2 Fm+\nI2C3 Fm+\nI2C4 Fm+\nI/O high speed / low voltage\nIndependent Watchdog 1 mode\nMass Erase Protected Area Disabled for bank 1\nMass erase protected area disabled for bank 2\nMass erase secured area disabled for bank 1\nMass erase secured area disabled for bank 2\nNMOS compensation code\nNMOS compensation value\nPA0 Switch Open\nPA1 Switch Open\nProtected area start address for bank 1\nProtected area start address for bank 2\nProtected area end address for bank 1\nProtected area end address for bank 2\nPB(6) Fm+\nPB(7) Fast Mode Plus\nPB(8) Fast Mode Plus\nPB(9) Fm+\nPC2 Switch Open\nPC3 Switch Open\nPMOS compensation code\nPMOS compensation value\nPackage\nPrivate key programmed\nReadout protection\nCompensation cell ready flag\nSecured area start address for bank 1\nSecured area start address for bank 2\nSecured area end address for bank 1\nSecured area end address for bank 2\nSecured DTCM RAM Size\nSecure mode\nWrite protection for flash bank 1\nWrite protection for flash bank 2\nWrite protection for flash bank 1\nWrite protection for flash bank 2\nAdvanced-timers\nBasic timer\nGeneral purpose 16-bit timer\nGeneral purpose 32-bit timer\nauto-reload register\nauto-reload register\nauto-reload register\nauto-reload register\nbreak and dead-time register\ncapture/compare enable register\ncapture/compare enable register\ncapture/compare enable register\ncapture/compare mode register 1 (input mode)\ncapture/compare mode register 1 (input mode)\ncapture/compare mode register 1 (input mode)\ncapture/compare mode register 1 (output mode)\ncapture/compare mode register 1 (output mode)\ncapture/compare mode register 1 (output mode)\ncapture/compare register\ncapture/compare register\ncapture/compare register\ncounter\ncounter\ncounter\ncounter\ncontrol register 1\ncontrol register 1\ncontrol register 1\ncontrol register 1\ncontrol register 2\ncontrol register 2\ncontrol register 2\ncontrol register 2\nDMA control register\nDMA control register\nDMA control register\nDMA/Interrupt enable register\nDMA/Interrupt enable register\nDMA/Interrupt enable register\nDMA/Interrupt enable register\nDMA address for full transfer\nDMA address for full transfer\nDMA address for full transfer\nevent generation register\nevent generation register\nevent generation register\nevent generation register\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nprescaler\nprescaler\nprescaler\nprescaler\nrepetition counter register\nslave mode control register\nslave mode control register\nslave mode control register\nstatus register\nstatus register\nstatus register\nstatus register\nauto-reload register\nauto-reload register\nbreak and dead-time register\ncapture/compare enable register\ncapture/compare enable register\ncapture/compare mode register 1 (input mode)\ncapture/compare mode register 2 (output mode)\ncapture/compare register 1\ncapture/compare register 1\ncounter\ncounter\ncontrol register 1\ncontrol register 1\ncontrol register 2\ncontrol register 2\ncontrol register 2\nDMA control register\nDMA/Interrupt enable register\nDMA/Interrupt enable register\nDMA/Interrupt enable register\nDMA address for full transfer\nevent generation register\nevent generation register\nevent generation register\nprescaler\nrepetition counter register\nslave mode control register\nstatus register\nstatus register\nstatus register\nAutomatic output enable\nAuto-reload preload enable\nAuto-reload preload enable\nAuto-reload value\nAuto-reload value\nBreak generation\nBreak generation\nBreak interrupt enable\nBreak interrupt flag\nBreak interrupt flag\nBreak enable\nBreak polarity\nCapture/Compare 1 DMA request enable\nCapture/Compare 1 DMA request enable\nCapture/compare DMA selection\nCapture/compare DMA selection\nCapture/Compare 1 output enable\nCapture/Compare 1 output enable\nCapture/compare 1 generation\nCapture/compare 1 generation\nCapture/Compare 1 interrupt enable\nCapture/Compare 1 interrupt enable\nCapture/compare 1 interrupt flag\nCapture/compare 1 interrupt flag\nCapture/Compare 1 complementary output enable\nCapture/Compare 1 output Polarity\nCapture/Compare 1 output Polarity\nCapture/Compare 1 overcapture flag\nCapture/Compare 1 overcapture flag\nCapture/Compare 1 output Polarity\nCapture/Compare 1 output Polarity\nCapture/compare preloaded control\nCapture/Compare 1 value\nCapture/Compare 1 value\nCapture/Compare 1 selection\nCapture/Compare 3 selection\nCapture/compare control update selection\nCounter enable\nCounter enable\nClock division\nCenter-aligned mode selection\ncounter value\ncounter value\nCOM DMA request enable\nCapture/Compare control update generation\nCapture/Compare control update generation\nCOM interrupt enable\nCOM interrupt flag\nCOM interrupt flag\nDMA base address\nDMA burst length\nDirection\nDMA register for burst accesses\nDead-time generator setup\nExternal clock mode 2 enable\nExternal trigger filter\nExternal trigger polarity\nExternal trigger prescaler\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nInput capture 1 filter\nInput capture 1 prescaler\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nLock configuration\nMaster mode selection\nMaster mode selection\nMaster mode selection\nMain output enable\nMaster/Slave mode\nOutput compare 3 clear enable\nOutput compare 3 fast enable\nOutput compare 3 mode\nOutput compare 3 preload enable\nOutput Idle state 1\nOutput Idle state 1\nOutput Idle state 2\nOutput Idle state 3\nOne-pulse mode enbaled\nOne-pulse mode enbaled\nOff-state selection for Idle mode\nOff-state selection for Run mode\nPrescaler value\nRepetition counter value\nAutomatic output enable\nAuto-reload preload enable\nAuto-reload preload enable\nAuto-reload value\nAuto-reload value\nBreak generation\nBreak generation\nBreak interrupt enable\nBreak interrupt flag\nBreak interrupt flag\nBreak enable\nBreak polarity\nCapture/Compare 1 DMA request enable\nCapture/Compare 1 DMA request enable\nCapture/compare DMA selection\nCapture/compare DMA selection\nCapture/Compare 1 output enable\nCapture/Compare 1 output enable\nCapture/compare 1 generation\nCapture/compare 1 generation\nCapture/Compare 1 interrupt enable\nCapture/Compare 1 interrupt enable\nCapture/compare 1 interrupt flag\nCapture/compare 1 interrupt flag\nCapture/Compare 1 complementary output enable\nCapture/Compare 1 output Polarity\nCapture/Compare 1 output Polarity\nCapture/Compare 1 overcapture flag\nCapture/Compare 1 overcapture flag\nCapture/Compare 1 output Polarity\nCapture/Compare 1 output Polarity\nCapture/compare preloaded control\nCapture/Compare 1 value\nCapture/Compare 1 value\nCapture/Compare 1 selection\nCapture/Compare 3 selection\nCapture/compare control update selection\nCounter enable\nCounter enable\nClock division\nCenter-aligned mode selection\ncounter value\ncounter value\nCOM DMA request enable\nCapture/Compare control update generation\nCapture/Compare control update generation\nCOM interrupt enable\nCOM interrupt flag\nCOM interrupt flag\nDMA base address\nDMA burst length\nDirection\nDMA register for burst accesses\nDead-time generator setup\nExternal clock mode 2 enable\nExternal trigger filter\nExternal trigger polarity\nExternal trigger prescaler\nInput capture 1 filter\nInput capture 1 prescaler\nLock configuration\nMaster mode selection\nMaster mode selection\nMaster mode selection\nMain output enable\nMaster/Slave mode\nOutput compare 3 clear enable\nOutput compare 3 fast enable\nOutput compare 3 mode\nOutput compare 3 preload enable\nOutput Idle state 1\nOutput Idle state 1\nOutput Idle state 2\nOutput Idle state 3\nOne-pulse mode enbaled\nOne-pulse mode enbaled\nOff-state selection for Idle mode\nOff-state selection for Run mode\nPrescaler value\nRepetition counter value\nSlave mode selection\nTrigger DMA request enable\nTrigger DMA request enable\nTrigger generation\nTrigger generation\nTI1 selection\nTI1 selection\nTrigger interrupt enable\nTrigger interrupt enable\nTrigger interrupt flag\nTrigger interrupt flag\nTrigger selection\nUpdate DMA request enable\nUpdate DMA request enable\nUpdate DMA request enable\nUpdate disable\nUpdate disable\nUpdate generation\nUpdate generation\nUpdate generation\nUpdate interrupt enable\nUpdate interrupt enable\nUpdate interrupt enable\nUpdate interrupt flag\nUpdate interrupt flag\nUpdate interrupt flag\nUpdate request source\nUpdate request source\nSlave mode selection\nTrigger DMA request enable\nTrigger DMA request enable\nTrigger generation\nTrigger generation\nTI1 selection\nTI1 selection\nTrigger interrupt enable\nTrigger interrupt enable\nTrigger interrupt flag\nTrigger interrupt flag\nTrigger selection\nUpdate DMA request enable\nUpdate DMA request enable\nUpdate DMA request enable\nUpdate disable\nUpdate disable\nUpdate generation\nUpdate generation\nUpdate generation\nUpdate interrupt enable\nUpdate interrupt enable\nUpdate interrupt enable\nUpdate interrupt flag\nUpdate interrupt flag\nUpdate interrupt flag\nUpdate request source\nUpdate request source\nSet channel to active level on match. OCyREF signal is …\nAny of counter overflow/underflow, setting UG, or update …\nThe counter counts up and down alternatively. Output …\nThe counter counts up and down alternatively. Output …\nThe counter counts up and down alternatively. Output …\nOC1REF signal is used as trigger output\nOC2REF signal is used as trigger output\nOC3REF signal is used as trigger output\nOC4REF signal is used as trigger output\nThe trigger output send a positive pulse when the CC1IF …\nOnly counter overflow/underflow generates an update …\nWhen inactive, OC/OCN outputs are disabled\nWhen inactive, OC/OCN outputs are disabled\nSlave mode disabled - if CEN = ‘1 then the prescaler is …\nt_DTS = t_CK_INT\nPrescaler OFF\nt_DTS = 2 × t_CK_INT\nETRP frequency divided by 2\nt_DTS = 4 × t_CK_INT\nETRP frequency divided by 4\nETRP frequency divided by 8\nCounter used as downcounter\nThe counter counts up or down depending on the direction …\nThe counter enable signal, CNT_EN, is used as trigger …\nEncoder mode 1 - Counter counts up/down on TI2FP1 edge …\nEncoder mode 2 - Counter counts up/down on TI1FP2 edge …\nEncoder mode 3 - Counter counts up/down on both TI1FP1 and …\nExternal Trigger input (ETRF)\nExternal Clock Mode 1 - Rising edges of the selected …\nfSAMPLING=fCK_INT, N=2\nfSAMPLING=fCK_INT, N=2\nfSAMPLING=fCK_INT, N=4\nfSAMPLING=fCK_INT, N=4\nfSAMPLING=fCK_INT, N=8\nfSAMPLING=fCK_INT, N=8\nfSAMPLING=fDTS/16, N=5\nfSAMPLING=fDTS/16, N=5\nfSAMPLING=fDTS/16, N=6\nfSAMPLING=fDTS/16, N=6\nfSAMPLING=fDTS/16, N=8\nfSAMPLING=fDTS/16, N=8\nfSAMPLING=fDTS/2, N=6\nfSAMPLING=fDTS/2, N=6\nfSAMPLING=fDTS/2, N=8\nfSAMPLING=fDTS/2, N=8\nfSAMPLING=fDTS/32, N=5\nfSAMPLING=fDTS/32, N=5\nfSAMPLING=fDTS/32, N=6\nfSAMPLING=fDTS/32, N=6\nfSAMPLING=fDTS/32, N=8\nfSAMPLING=fDTS/32, N=8\nfSAMPLING=fDTS/4, N=6\nfSAMPLING=fDTS/4, N=6\nfSAMPLING=fDTS/4, N=8\nfSAMPLING=fDTS/4, N=8\nfSAMPLING=fDTS/8, N=6\nfSAMPLING=fDTS/8, N=6\nfSAMPLING=fDTS/8, N=8\nfSAMPLING=fDTS/8, N=8\nOCyREF is forced high\nOCyREF is forced low\nThe comparison between the output compare register …\nGated Mode - The counter clock is enabled when the trigger …\nWhen inactive, OC/OCN outputs are forced to idle level\nWhen inactive, OC/OCN outputs are enabled with their …\nSet channel to inactive level on match. OCyREF signal is …\nETR is inverted, active at low level or falling edge\nInternal Trigger 0 (ITR0)\nInternal Trigger 1 (ITR1)\nInternal Trigger 2 (ITR2)\nInternal Trigger 3 (ITR3)\nNo filter, sampling is done at fDTS\nNo filter, sampling is done at fDTS\nThe TIMx_CH1 pin is connected to TI1 input\nNo action\nETR is noninverted, active at high level or rising edge\nCCx DMA request sent when CCx event occurs\nCCx DMA request sent when update event occurs\nCCx channel is configured as output\nIn upcounting, channel is active as long as TIMx_CNT&lt;…\nInversely to PwmMode1\nThe UG bit from the TIMx_EGR register is used as trigger …\nReset Mode - Rising edge of the selected trigger input …\nThe effect of an event on the trigger input (TRGI) is …\nFiltered Timer Input 1 (TI1FP1)\nTI1 Edge Detector (TI1F_ED)\nFiltered Timer Input 2 (TI2FP2)\nCCx channel is configured as input, alternate mapping …\nCCx channel is configured as input, normal mapping: ICx …\nOCyREF toggles when TIMx_CNT=TIMx_CCRy\nCCx channel is configured as input, ICx is mapped on TRC\nTrigger Mode - The counter starts at a rising edge of the …\nCounter used as upcounter\nThe update event is selected as trigger output\nThe TIMx_CH1, CH2, CH3 pins are connected to TI1 input\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nDevice Factory programmed 96-bit unique device identifier\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nFactory programmed 96-bit unique device identifier word 0\nLow-power Universal synchronous asynchronous receiver …\nUniversal synchronous asynchronous receiver transmitter\nBaud rate register\nBaud rate register\nControl register 1\nControl register 1\nControl register 2\nControl register 2\nControl register 3\nControl register 3\nReturns the argument unchanged.\nReturns the argument unchanged.\nGuard time and prescaler register\nInterrupt flag clear register\nInterrupt flag clear register\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nInterrupt &amp; status register\nInterrupt &amp; status register\nPrescaler register\nPrescaler register\nReceive data register\nReceive data register\nRequest register\nRequest register\nReceiver timeout register\nTransmit data register\nTransmit data register\nBaud rate register\nControl register 1\nControl register 2\nControl register 3\nData register\nGuard time and prescaler register\nInterrupt flag clear register\nInterrupt &amp; status register\nPrescaler register\nRequest register\nReceiver timeout register\nAuto baud rate error\nAuto baud rate enable\nAuto baud rate flag\nAuto baud rate mode\nAuto baud rate request. Resets the ABRF flag in the …\nAddress of the USART node\n7-bit Address Detection/4-bit Address Detection\nBlock Length\nUSARTDIV\nBusy flag\nClock enable\nCharacter match clear flag\ncharacter match flag\nCharacter match interrupt enable\nClock phase\nClock polarity\nCTS clear flag\nCTS flag\nCTS enable\nCTS interrupt enable\nCTS interrupt flag\nBinary data inversion\nDMA Disable on Reception Error\nDriver Enable assertion time\nDriver Enable deassertion time\nDriver enable mode\nDriver enable polarity selection\nDMA enable receiver\nDMA enable transmitter\nData value\nError interrupt enable\nEnd of block clear flag\nEnd of block flag\nEnd of Block interrupt enable\nFraming error clear flag\nFraming error\nFIFO mode enable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nGuard time value\nHalf-duplex selection\nIdle line detected clear flag\nIdle line detected\nIDLE interrupt enable\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nIrDA mode enable\nIrDA low-power\nLast bit clock pulse\nLIN break detection clear flag\nLIN break detection flag\nLIN break detection interrupt enable\nLine break detection length\nLIN mode enable\nWord length\nWord length\nMute mode enable\nMute mode request. Puts the USART in mute mode and sets …\nMost significant bit first\nSmartcard NACK enable\nNoise error clear flag\nNoise error flag\nOne sample bit method enable\nOverrun error clear flag\nOverrun error\nOversampling mode\nOverrun Disable\nParity control enable\nParity error clear flag\nParity error\nPE interrupt enable\nClock prescaler\nParity selection\nPrescaler value\nReceiver enable\nReceive enable acknowledge flag\nReceiver timeout value\nReceiver timeout enable\nReceiver timeout clear flag\nReceiver timeout\nReceiver timeout interrupt enable\nRTS enable\nReceiver wakeup from Mute mode\nRXFIFO Full\nRXFIFO Full interrupt enable\nReceive data flush request. Clears the RXNE flag. This …\nRXFIFO threshold flag\nReceive FIFO threshold configuration\nRXFIFO threshold interrupt enable\nRX pin active level inversion\nRead data register not empty\nRXNE interrupt enable\nSend break flag\nSend break request. Sets the SBKF flag and request to send …\nSmartcard auto-retry count\nSmartcard mode enable\nAuto baud rate error\nAuto baud rate enable\nAuto baud rate flag\nAuto baud rate mode\nAuto baud rate request. Resets the ABRF flag in the …\nAddress of the USART node\n7-bit Address Detection/4-bit Address Detection\nBlock Length\nUSARTDIV\nBusy flag\nClock enable\nCharacter match clear flag\ncharacter match flag\nCharacter match interrupt enable\nClock phase\nClock polarity\nCTS clear flag\nCTS flag\nCTS enable\nCTS interrupt enable\nCTS interrupt flag\nBinary data inversion\nDMA Disable on Reception Error\nDriver Enable assertion time\nDriver Enable deassertion time\nDriver enable mode\nDriver enable polarity selection\nDMA enable receiver\nDMA enable transmitter\nData value\nError interrupt enable\nEnd of block clear flag\nEnd of block flag\nEnd of Block interrupt enable\nFraming error clear flag\nFraming error\nFIFO mode enable\nGuard time value\nHalf-duplex selection\nIdle line detected clear flag\nIdle line detected\nIDLE interrupt enable\nIrDA mode enable\nIrDA low-power\nLast bit clock pulse\nLIN break detection clear flag\nLIN break detection flag\nLIN break detection interrupt enable\nLine break detection length\nLIN mode enable\nWord length\nWord length\nMute mode enable\nMute mode request. Puts the USART in mute mode and sets …\nMost significant bit first\nSmartcard NACK enable\nNoise error clear flag\nNoise error flag\nOne sample bit method enable\nOverrun error clear flag\nOverrun error\nOversampling mode\nOverrun Disable\nParity control enable\nParity error clear flag\nParity error\nPE interrupt enable\nClock prescaler\nParity selection\nPrescaler value\nReceiver enable\nReceive enable acknowledge flag\nReceiver timeout value\nReceiver timeout enable\nReceiver timeout clear flag\nReceiver timeout\nReceiver timeout interrupt enable\nRTS enable\nReceiver wakeup from Mute mode\nRXFIFO Full\nRXFIFO Full interrupt enable\nReceive data flush request. Clears the RXNE flag. This …\nRXFIFO threshold flag\nReceive FIFO threshold configuration\nRXFIFO threshold interrupt enable\nRX pin active level inversion\nRead data register not empty\nRXNE interrupt enable\nSend break flag\nSend break request. Sets the SBKF flag and request to send …\nSmartcard auto-retry count\nSmartcard mode enable\nSTOP bits\nSwap TX/RX pins\nTransmission complete clear flag\nTransmission complete\nTransmission complete interrupt enable\nTransmitter enable\nTransmit enable acknowledge flag\nTransmit data register empty\nTXE interrupt enable\nTXFIFO Empty\nTXFIFO empty interrupt enable\nTransmit data flush request. Sets the TXE flags. This …\nTXFIFO threshold flag\nTXFIFO threshold configuration\nTXFIFO threshold interrupt enable\nTX pin active level inversion\nUSART enable\nUSART enable in Stop mode\nReceiver wakeup method\nWakeup from Stop mode clear flag\nWakeup from Stop mode flag\nWakeup from Stop mode interrupt enable\nWakeup from Stop mode interrupt flag selection\nSTOP bits\nSwap TX/RX pins\nTransmission complete clear flag\nTransmission complete\nTransmission complete interrupt enable\nTransmitter enable\nTransmit enable acknowledge flag\nTransmit data register empty\nTXE interrupt enable\nTXFIFO Empty\nTXFIFO empty interrupt enable\nTransmit data flush request. Sets the TXE flags. This …\nTXFIFO threshold flag\nTXFIFO threshold configuration\nTXFIFO threshold interrupt enable\nTX pin active level inversion\nUSART enable\nUSART enable in Stop mode\nReceiver wakeup method\nWakeup from Stop mode clear flag\nWakeup from Stop mode flag\nWakeup from Stop mode interrupt enable\nWakeup from Stop mode interrupt flag selection\nReceiver in active mode\nWUF active on address match\nUSART wakeup on address mark\n10-bit break detection\n11-bit break detection\n4-bit address detection\n7-bit address detection\n1 start bit, 7 data bits, n stop bits\n1 start bit, 8 data bits, n stop bits\n1 start bit, 9 data bits, n stop bits\ninput clock not divided\ninput clock divided by 10\ninput clock divided by 12\ninput clock divided by 128\ninput clock divided by 16\ninput clock divided by 2\ninput clock divided by 256\ninput clock divided by 32\ninput clock divided by 4\ninput clock divided by 6\ninput clock divided by 64\ninput clock divided by 8\nFalling edge to falling edge measurement\nEven parity\nThe first clock transition is the first data capture edge\n0x55 frame detection\n0x7F frame detection\nSteady high value on CK pin outside transmission window\nDE signal is active high\nUSART wakeup on idle line\nSteady low value on CK pin outside transmission window\nDE signal is active low\nLow-power mode\ndata is transmitted/received with data bit 0 first, …\nUse M0 to set the data bits\ndata is transmitted/received with MSB (bit 7/8/9) first, …\nReceiver in mute mode\nNormal mode\nOdd parity\nOversampling by 16\nOversampling by 8\nWUF active on RXNE\nThe second clock transition is the first data capture edge\nMeasurement of the start bit is used to detect the baud …\nWuF active on Start bit detection\n0.5 stop bits\n1 stop bit\n1.5 stop bits\n2 stop bits\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nWindow watchdog\nConfiguration register\nControl register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nStatus register\nConfiguration register\nControl register\nStatus register\nEarly wakeup interrupt\nEarly wakeup interrupt flag\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nEarly wakeup interrupt\nEarly wakeup interrupt flag\n7-bit counter (MSB to LSB)\n7-bit window value\nActivation bit (true is enabled, false is disabled)\nTimer base\n7-bit counter (MSB to LSB)\n7-bit window value\nActivation bit (true is enabled, false is disabled)\nTimer base\nCounter clock (PCLK1 div 4096) div 1\nCounter clock (PCLK1 div 4096) div 128\nCounter clock (PCLK1 div 4096) div 16\nCounter clock (PCLK1 div 4096) div 2\nCounter clock (PCLK1 div 4096) div 32\nCounter clock (PCLK1 div 4096) div 4\nCounter clock (PCLK1 div 4096) div 64\nCounter clock (PCLK1 div 4096) div 8\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.")