searchState.loadedDescShard("stm32_metapac", 0, "18 - ADC\n127 - ADC3\n129 - BDMA_CHANNEL0\n130 - BDMA_CHANNEL1\n131 - BDMA_CHANNEL2\n132 - BDMA_CHANNEL3\n133 - BDMA_CHANNEL4\n134 - BDMA_CHANNEL5\n135 - BDMA_CHANNEL6\n136 - BDMA_CHANNEL7\n94 - CEC\n154 - CORDIC\n144 - CRS\n78 - DCMI_PSSI\n110 - DFSDM1_FLT0\n111 - DFSDM1_FLT1\n112 - DFSDM1_FLT2\n113 - DFSDM1_FLT3\n11 - DMA1_STREAM0\n12 - DMA1_STREAM1\n13 - DMA1_STREAM2\n14 - DMA1_STREAM3\n15 - DMA1_STREAM4\n16 - DMA1_STREAM5\n17 - DMA1_STREAM6\n47 - DMA1_STREAM7\n90 - DMA2D\n56 - DMA2_STREAM0\n57 - DMA2_STREAM1\n58 - DMA2_STREAM2\n59 - DMA2_STREAM3\n60 - DMA2_STREAM4\n68 - DMA2_STREAM5\n69 - DMA2_STREAM6\n70 - DMA2_STREAM7\n102 - DMAMUX1_OVR\n128 - DMAMUX2_OVR\n147 - DTS\n145 - ECC\n61 - ETH\n62 - ETH_WKUP\n6 - EXTI0\n7 - EXTI1\n40 - EXTI15_10\n8 - EXTI2\n9 - EXTI3\n10 - EXTI4\n23 - EXTI9_5\n19 - FDCAN1_IT0\n21 - FDCAN1_IT1\n20 - FDCAN2_IT0\n22 - FDCAN2_IT1\n159 - FDCAN3_IT0\n160 - FDCAN3_IT1\n63 - FDCAN_CAL\n4 - FLASH\n153 - FMAC\n48 - FMC\n81 - FPU\n125 - HSEM1\n32 - I2C1_ER\n31 - I2C1_EV\n34 - I2C2_ER\n33 - I2C2_EV\n73 - I2C3_ER\n72 - I2C3_EV\n96 - I2C4_ER\n95 - I2C4_EV\n158 - I2C5_ER\n157 - I2C5_EV\n93 - LPTIM1\n138 - LPTIM2\n139 - LPTIM3\n140 - LPTIM4\n141 - LPTIM5\n142 - LPUART1\n88 - LTDC\n89 - LTDC_ER\n120 - MDIOS\n119 - MDIOS_WKUP\n122 - MDMA\n92 - OCTOSPI1\n150 - OCTOSPI2\n77 - OTG_HS\n75 - OTG_HS_EP1_IN\n74 - OTG_HS_EP1_OUT\n76 - OTG_HS_WKUP\n1 - PVD_AVD\n5 - RCC\n80 - RNG\n41 - RTC_ALARM\n3 - RTC_WKUP\n87 - SAI1\n146 - SAI4\n49 - SDMMC1\n124 - SDMMC2\n97 - SPDIF_RX\n35 - SPI1\n36 - SPI2\n51 - SPI3\n84 - SPI4\n85 - SPI5\n86 - SPI6\n115 - SWPMI1\n2 - TAMP_STAMP\n116 - TIM15\n117 - TIM16\n118 - TIM17\n24 - TIM1_BRK\n27 - TIM1_CC\n26 - TIM1_TRG_COM\n25 - TIM1_UP\n28 - TIM2\n161 - TIM23\n162 - TIM24\n29 - TIM3\n30 - TIM4\n50 - TIM5\n54 - TIM6_DAC\n55 - TIM7\n43 - TIM8_BRK_TIM12\n46 - TIM8_CC\n45 - TIM8_TRG_COM_TIM14\n44 - TIM8_UP_TIM13\n52 - UART4\n53 - UART5\n82 - UART7\n83 - UART8\n155 - UART9\n37 - USART1\n156 - USART10\n38 - USART2\n39 - USART3\n71 - USART6\n149 - WAKEUP_PIN\n0 - WWDG\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nAnalog to Digital Converter\nanalog watchdog 2 configuration register\nanalog watchdog 3 configuration register\ncalibration factors register\nCalibration Factor register 2\nconfiguration register 1\nconfiguration register 2\ncontrol register\nchannel differential or single-ended mode selection …\ngroup regular conversion data register\nReturns the argument unchanged.\nanalog watchdog 2 threshold register\nwatchdog higher threshold register 2\nwatchdog higher threshold register 3\ninterrupt enable register\nCalls <code>U::from(self)</code>.\ninterrupt and status register\ngroup injected sequencer rank 1-4 register\ngroup injected sequencer register\nanalog watchdog 1 threshold register\nwatchdog lower threshold register 2\nwatchdog lower threshold register 3\noffset number 1-4 register\npre channel selection register\nsampling time register 1-2\ngroup regular sequencer ranks register 1\ngroup regular sequencer ranks register 2\ngroup regular sequencer ranks register 3\ngroup regular sequencer ranks register 4\nanalog watchdog 2 configuration register\nanalog watchdog 3 configuration register\ncalibration factors register\nCalibration Factor register 2\nconfiguration register 1\nconfiguration register 2\ncontrol register\nchannel differential or single-ended mode selection …\ngroup regular conversion data register\nanalog watchdog 2 threshold register\nwatchdog higher threshold register 2\nwatchdog higher threshold register 3\ninterrupt enable register\ninterrupt and status register\ngroup injected sequencer rank 1 register\ngroup injected sequencer register\nanalog watchdog 1 threshold register\nwatchdog lower threshold register 2\nwatchdog lower threshold register 3\noffset number x register\nchannel preselection register\nsampling time register n\ngroup regular sequencer ranks register 1\ngroup regular sequencer ranks register 2\ngroup regular sequencer ranks register 3\ngroup regular sequencer ranks register 4\ncalibration\ndifferential mode for calibration\nLinearity calibration\ndisable\nenable\nready flag\nready interrupt\ngroup regular conversion start\ngroup regular conversion stop\nvoltage regulator enable\nlow power auto wait\nanalog watchdog 1 flag\nanalog watchdog 1 monitored channel selection\nanalog watchdog 1 enable on scope group regular\nanalog watchdog 1 interrupt\nanalog watchdog 1 monitoring a single channel or all …\nanalog watchdog 2 flag\nanalog watchdog 2 monitored channel selection\nanalog watchdog 2 interrupt\nanalog watchdog 3 flag\nanalog watchdog 3 monitored channel selection\nanalog watchdog 3 interrupt\nBoost mode control\ncalibration factor in differential mode\ncalibration factor in single-ended mode\ngroup regular continuous conversion mode\ndeep power down enable\nchannel differential or single-ended mode for channel\ngroup regular sequencer discontinuous mode\ngroup regular sequencer discontinuous number of ranks\nDMA transfer enable\ngroup regular end of unitary conversion flag\ngroup regular end of unitary conversion interrupt\ngroup regular end of sequence conversions flag\ngroup regular end of sequence conversions interrupt\ngroup regular end of sampling flag\ngroup regular end of sampling interrupt\ngroup regular external trigger polarity\ngroup regular external trigger source\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nanalog watchdog 2 threshold low\nAnalog watchdog 2 higher threshold\nAnalog watchdog 3 higher threshold\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\ngroup injected conversion start\ngroup injected conversion stop\ngroup injected automatic trigger mode\nanalog watchdog 1 enable on scope group injected\ngroup injected sequencer rank 1 conversion data\ngroup injected sequencer discontinuous mode\ngroup injected end of unitary conversion flag\ngroup injected end of unitary conversion interrupt\ngroup injected end of sequence conversions flag\ngroup injected end of sequence conversions interrupt\ngroup injected external trigger polarity\ngroup injected external trigger source\ngroup injected sequencer scan length\noversampler enable on scope group injected\ngroup injected contexts queue disable\ngroup injected contexts queue mode\ngroup injected contexts queue overflow flag\ngroup injected contexts queue overflow interrupt\ngroup injected sequencer rank 1-4\nL3\nADC LDO output voltage ready (not always available)\nLinearity Calibration Factor\nLinearity calibration ready Word 1\nLinearity calibration ready Word 2\nLinearity calibration ready Word 3\nLinearity calibration ready Word 4\nLinearity calibration ready Word 5\nLinearity calibration ready Word 6\nLeft shift factor\nanalog watchdog 1 threshold low\nAnalog watchdog 2 lower threshold\nAnalog watchdog 3 lower threshold\noffset number x offset level\noffset number x channel selection\nOversampling ratio\ngroup regular overrun flag\ngroup regular overrun interrupt\ngroup regular overrun configuration\noversampling shift\nChannel x (VINP[i]) pre selection\ngroup regular conversion data\ndata resolution\noversampler enable on scope group regular\nRegular Oversampling mode\nRight-shift data after Offset 1 correction\nRight-shift data after Offset 2 correction\nRight-shift data after Offset 3 correction\nRight-shift data after Offset 4 correction\ncalibration\ndifferential mode for calibration\nLinearity calibration\ndisable\nenable\nready flag\nready interrupt\ngroup regular conversion start\ngroup regular conversion stop\nvoltage regulator enable\nlow power auto wait\nanalog watchdog 1 flag\nanalog watchdog 1 monitored channel selection\nanalog watchdog 1 enable on scope group regular\nanalog watchdog 1 interrupt\nanalog watchdog 1 monitoring a single channel or all …\nanalog watchdog 2 flag\nanalog watchdog 2 monitored channel selection\nanalog watchdog 2 interrupt\nanalog watchdog 3 flag\nanalog watchdog 3 monitored channel selection\nanalog watchdog 3 interrupt\nBoost mode control\ncalibration factor in differential mode\ncalibration factor in single-ended mode\ngroup regular continuous conversion mode\ndeep power down enable\nchannel differential or single-ended mode for channel\ngroup regular sequencer discontinuous mode\ngroup regular sequencer discontinuous number of ranks\nDMA transfer enable\ngroup regular end of unitary conversion flag\ngroup regular end of unitary conversion interrupt\ngroup regular end of sequence conversions flag\ngroup regular end of sequence conversions interrupt\ngroup regular end of sampling flag\ngroup regular end of sampling interrupt\ngroup regular external trigger polarity\ngroup regular external trigger source\nanalog watchdog 2 threshold low\nAnalog watchdog 2 higher threshold\nAnalog watchdog 3 higher threshold\ngroup injected conversion start\ngroup injected conversion stop\ngroup injected automatic trigger mode\nanalog watchdog 1 enable on scope group injected\ngroup injected sequencer rank 1 conversion data\ngroup injected sequencer discontinuous mode\ngroup injected end of unitary conversion flag\ngroup injected end of unitary conversion interrupt\ngroup injected end of sequence conversions flag\ngroup injected end of sequence conversions interrupt\ngroup injected external trigger polarity\ngroup injected external trigger source\ngroup injected sequencer scan length\noversampler enable on scope group injected\ngroup injected contexts queue disable\ngroup injected contexts queue mode\ngroup injected contexts queue overflow flag\ngroup injected contexts queue overflow interrupt\ngroup injected sequencer rank 1-4\nL3\nADC LDO output voltage ready (not always available)\nLinearity Calibration Factor\nLinearity calibration ready Word 1\nLinearity calibration ready Word 2\nLinearity calibration ready Word 3\nLinearity calibration ready Word 4\nLinearity calibration ready Word 5\nLinearity calibration ready Word 6\nLeft shift factor\nanalog watchdog 1 threshold low\nAnalog watchdog 2 lower threshold\nAnalog watchdog 3 lower threshold\noffset number x offset level\noffset number x channel selection\nOversampling ratio\ngroup regular overrun flag\ngroup regular overrun interrupt\ngroup regular overrun configuration\noversampling shift\nChannel x (VINP[i]) pre selection\ngroup regular conversion data\ndata resolution\noversampler enable on scope group regular\nRegular Oversampling mode\nRight-shift data after Offset 1 correction\nRight-shift data after Offset 2 correction\nRight-shift data after Offset 3 correction\nRight-shift data after Offset 4 correction\nchannel n * 10 + x sampling time\ngroup regular sequencer rank 1-4\ngroup regular sequencer rank 5-9\ngroup regular sequencer rank 10-14\ngroup regular sequencer rank 15-16\nSigned saturation enable\noversampling discontinuous mode (triggered mode) for group …\nchannel n * 10 + x sampling time\ngroup regular sequencer rank 1-4\ngroup regular sequencer rank 5-9\ngroup regular sequencer rank 10-14\ngroup regular sequencer rank 15-16\nSigned saturation enable\noversampling discontinuous mode (triggered mode) for group …\nAnalog watchdog 1 enabled on all channels\nAll oversampled conversions for a channel are run …\nTrigger detection on both the rising and falling edges\nTrigger detection on both the rising and falling edges\nOversampling is temporary stopped and continued after …\n16.5 clock cycles\n1.5 clock cycles\n2.5 clock cycles\n32.5 clock cycles\n387.5 clock cycles\n64.5 clock cycles\n810.5 clock cycles\n8.5 clock cycles\nDFSDM mode selected\nCalibration for differential mode\nInput channel is configured in differential mode\nTrigger detection disabled\nTrigger detection disabled\nDMA Circular Mode selected\nDMA One Shot Mode selected\nStore output data in DR only\n8-bit resolution\nTrigger detection on the falling edge\nTrigger detection on the falling edge\n14-bit resolution in legacy mode (not optimized power …\n14-bit resolution\nBoost mode used when 6.25 MHz &lt; clock ≤ 12.5 MHz\nBoost mode used when 12.5 MHz &lt; clock ≤ 25.0 MHz\nBoost mode used when 25.0 MHz &lt; clock ≤ 50.0 MHz\nBoost mode used when clock ≤ 6.25 MHz\nJSQR Mode 0: Queue maintains the last written …\nJSQR Mode 1: An empty queue disables software and hardware …\nInput channel x is not pre-selected\nOverwrite DR register when an overrun is detected\nPre-select input channel x\nPreserve DR register when an overrun is detected\nOversampling is aborted and resumed from start after …\nTrigger detection on the rising edge\nTrigger detection on the rising edge\nAnalog watchdog 1 enabled on single channel selected in …\nCalibration for single-ended mode\nInput channel is configured in single-ended mode\n16-bit resolution\nStop conversion of channel\n10-bit resolution\nEach oversampled conversion for a channel needs a new …\n12-bit resolution in legacy mode (not optimized power …\n12-bit resolution\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nAnalog-to-Digital Converter\nADC common control register\nADC common regular data register for dual and triple modes\nADC x common regular data register for 32-bit dual mode\nADC Common status register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nADC common control register\nADC common regular data register for dual and triple modes\nADC x common regular data register for 32-bit dual mode\nADC Common status register\nMaster ADC ready\nSlave ADC ready\nAnalog watchdog flag of the master ADC\nAnalog watchdog flag of the slave ADC\nADC clock mode\nDual ADC Mode Data Format\nDelay between 2 sampling phases\nDual ADC mode selection\nEnd of regular conversion of the master ADC\nEnd of regular conversion of the slave ADC\nEnd of regular sequence flag of the master ADC\nEnd of regular sequence flag of the slave ADC\nEnd of Sampling phase flag of the master ADC\nEnd of Sampling phase flag of the slave ADC\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nEnd of injected conversion flag of the master ADC\nEnd of injected conversion flag of the slave ADC\nEnd of injected sequence flag of the master ADC\nEnd of injected sequence flag of the slave ADC\nInjected Context Queue Overflow flag of the master ADC\nInjected Context Queue Overflow flag of the slave ADC\nOverrun flag of the master ADC\nOverrun flag of the slave ADC\nADC prescaler\nRegular data of the master/slave alternated ADCs\nRegular data of the master ADC\nRegular data of the slave ADC\nMaster ADC ready\nSlave ADC ready\nAnalog watchdog flag of the master ADC\nAnalog watchdog flag of the slave ADC\nADC clock mode\nDual ADC Mode Data Format\nDelay between 2 sampling phases\nDual ADC mode selection\nEnd of regular conversion of the master ADC\nEnd of regular conversion of the slave ADC\nEnd of regular sequence flag of the master ADC\nEnd of regular sequence flag of the slave ADC\nEnd of Sampling phase flag of the master ADC\nEnd of Sampling phase flag of the slave ADC\nEnd of injected conversion flag of the master ADC\nEnd of injected conversion flag of the slave ADC\nEnd of injected sequence flag of the master ADC\nEnd of injected sequence flag of the slave ADC\nInjected Context Queue Overflow flag of the master ADC\nInjected Context Queue Overflow flag of the slave ADC\nOverrun flag of the master ADC\nOverrun flag of the slave ADC\nADC prescaler\nRegular data of the master/slave alternated ADCs\nRegular data of the master ADC\nRegular data of the slave ADC\nVBAT enable\nVREFINT enable\nTemperature sensor enable\nVBAT enable\nVREFINT enable\nTemperature sensor enable\nUse Kernel Clock adc_ker_ck_input divided by PRESC. …\nadc_ker_ck_input not divided\nadc_ker_ck_input divided by 10\nadc_ker_ck_input divided by 12\nadc_ker_ck_input divided by 128\nadc_ker_ck_input divided by 16\nadc_ker_ck_input divided by 2\nadc_ker_ck_input divided by 256\nadc_ker_ck_input divided by 32\nadc_ker_ck_input divided by 4\nadc_ker_ck_input divided by 6\nadc_ker_ck_input divided by 64\nadc_ker_ck_input divided by 8\nDual, alternate trigger mode only\nDual, interleaved mode only\nDual, combined interleaved mode + injected simultaneous …\nDual, injected simultaneous mode only\nDual, regular simultaneous mode only\nDual, combined regular simultaneous + alternate trigger …\nDual, combined regular simultaneous + injected …\nCDR formatted for 32-bit down to 10-bit resolution\nCDR formatted for 8-bit resolution\nIndependent mode\nWithout data packing, CDR/CDR2 not used\nUse AHB clock rcc_hclk3. In this case rcc_hclk must equal …\nUse AHB clock rcc_hclk3 divided by 2\nUse AHB clock rcc_hclk3 divided by 4\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nChannel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers\nDMA controller\nChannel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers\nDMA channel configuration register (DMA_CCR)\nReturns the argument unchanged.\nReturns the argument unchanged.\nDMA interrupt flag clear register (DMA_IFCR)\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nDMA interrupt status register (DMA_ISR)\nDMA channel 1 memory address register\nDMA channel 1 number of data register\nDMA channel 1 peripheral address register\nDMA channel configuration register (DMA_CCR)\nDMA interrupt status register (DMA_ISR)\nDMA channel 1 number of data register\nCircular mode enabled\nData transfer direction\nChannel enable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nChannel 1 Global interrupt flag\nHalf Transfer interrupt enable\nChannel 1 Half Transfer Complete flag\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nMemory to memory mode enabled\nMemory increment mode enabled\nMemory size\nNumber of data to transfer\nPeripheral increment mode enabled\nChannel Priority level\nPeripheral size\nCircular mode enabled\nData transfer direction\nChannel enable\nChannel 1 Global interrupt flag\nHalf Transfer interrupt enable\nChannel 1 Half Transfer Complete flag\nMemory to memory mode enabled\nMemory increment mode enabled\nMemory size\nNumber of data to transfer\nPeripheral increment mode enabled\nChannel Priority level\nPeripheral size\nTransfer complete interrupt enable\nChannel 1 Transfer Complete flag\nTransfer error interrupt enable\nChannel 1 Transfer Error flag\nTransfer complete interrupt enable\nChannel 1 Transfer Complete flag\nTransfer error interrupt enable\nChannel 1 Transfer Error flag\n16-bit size\n32-bit size\n8-bit size\nRead from memory\nRead from peripheral\nHigh priority\nLow priority\nMedium priority\nVery high priority\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nController area network with flexible data rate (FD)\nFDCAN CC Control Register\nFDCAN Core Release Register\nFDCAN Data Bit Timing and Prescaler Register\nFDCAN Error Counter Register\nFDCAN Core Release Register\nReturns the argument unchanged.\nFDCAN Global Filter Configuration Register\nFDCAN High Priority Message Status Register\nFDCAN Interrupt Enable Register\nFDCAN Interrupt Line Enable Register\nFDCAN Interrupt Line Select Register\nCalls <code>U::from(self)</code>.\nFDCAN Interrupt Register\nFDCAN Nominal Bit Timing and Prescaler Register\nFDCAN New Data 1 Register\nFDCAN New Data 2 Register\nFDCAN Protocol Status Register\nFDCAN RAM Watchdog Register\nFDCAN Rx Buffer Configuration Register\nFDCAN Rx Buffer Element Size Configuration Register\nCAN Rx FIFO X Acknowledge Register\nFDCAN Rx FIFO X Configuration Register\nFDCAN Rx FIFO X Status Register\nFDCAN Standard ID Filter Configuration Register\nFDCAN Transmitter Delay Compensation Register\nFDCAN Test Register\nFDCAN Timeout Counter Configuration Register\nFDCAN Timeout Counter Value Register\nFDCAN Timestamp Counter Configuration Register\nFDCAN Timestamp Counter Value Register\nFDCAN TT Capture Time Register\nFDCAN TT Cycle Sync Mark Register\nFDCAN TT Cycle Time and Count Register\nFDCAN TT Global Time Preset Register\nFDCAN TT Interrupt Enable Register\nFDCAN TT Interrupt Line Select Register\nFDCAN TT Interrupt Register\nFDCAN TT Local and Global Time Register\nFDCAN TT Matrix Limits Register\nFDCAN TT Operation Configuration Register\nFDCAN TT Operation Control Register\nFDCAN TT Operation Status Register\nFDCAN TT Reference Message Configuration Register\nFDCAN TT Trigger Memory Configuration Register\nFDCAN TT Time Mark Register\nFDCAN TT Trigger Select Register\nFDCAN TUR Configuration Register\nFDCAN TUR Numerator Actual Register\nFDCAN Tx Buffer Add Request Register\nFDCAN Tx Buffer Configuration Register\nFDCAN Tx Buffer Cancellation Finished Register\nFDCAN Tx Buffer Cancellation Finished Interrupt Enable …\nFDCAN Tx Buffer Cancellation Request Register\nFDCAN Tx Buffer Request Pending Register\nFDCAN Tx Buffer Transmission Interrupt Enable Register\nFDCAN Tx Buffer Transmission Occurred Register\nFDCAN Tx Event FIFO Acknowledge Register\nFDCAN Tx Event FIFO Configuration Register\nFDCAN Tx Event FIFO Status Register\nFDCAN Tx Buffer Element Size Configuration Register\nFDCAN Tx FIFO/Queue Status Register\nFDCAN Extended ID and Mask Register\nFDCAN Extended ID Filter Configuration Register\nFDCAN CC Control Register\nFDCAN Core Release Register\nFDCAN Data Bit Timing and Prescaler Register\nFDCAN Error Counter Register\nFDCAN Core Release Register\nFDCAN Global Filter Configuration Register\nFDCAN High Priority Message Status Register\nFDCAN Interrupt Enable Register\nFDCAN Interrupt Line Enable Register\nFDCAN Interrupt Line Select Register\nFDCAN Interrupt Register\nFDCAN Nominal Bit Timing and Prescaler Register\nFDCAN New Data 1 Register\nFDCAN New Data 2 Register\nFDCAN Protocol Status Register\nFDCAN RAM Watchdog Register\nFDCAN Rx Buffer Configuration Register\nFDCAN Rx Buffer Element Size Configuration Register\nCAN Rx FIFO X Acknowledge Register\nFDCAN Rx FIFO X Configuration Register\nFDCAN Rx FIFO X Status Register\nFDCAN Standard ID Filter Configuration Register\nFDCAN Transmitter Delay Compensation Register\nFDCAN Test Register\nFDCAN Timeout Counter Configuration Register\nFDCAN Timeout Counter Value Register\nFDCAN Timestamp Counter Configuration Register\nFDCAN Timestamp Counter Value Register\nFDCAN TT Capture Time Register\nFDCAN TT Cycle Sync Mark Register\nFDCAN TT Cycle Time and Count Register\nFDCAN TT Global Time Preset Register\nFDCAN TT Interrupt Enable Register\nFDCAN TT Interrupt Line Select Register\nFDCAN TT Interrupt Register\nFDCAN TT Local and Global Time Register\nFDCAN TT Matrix Limits Register\nFDCAN TT Operation Configuration Register\nFDCAN TT Operation Control Register\nFDCAN TT Operation Status Register\nFDCAN TT Reference Message Configuration Register\nFDCAN TT Trigger Memory Configuration Register\nFDCAN TT Time Mark Register\nFDCAN TT Trigger Select Register\nFDCAN TUR Configuration Register\nFDCAN TUR Numerator Actual Register\nFDCAN Tx Buffer Add Request Register\nFDCAN Tx Buffer Configuration Register\nFDCAN Tx Buffer Cancellation Finished Register\nFDCAN Tx Buffer Cancellation Finished Interrupt Enable …\nFDCAN Tx Buffer Cancellation Request Register\nFDCAN Tx Buffer Request Pending Register\nFDCAN Tx Buffer Transmission Interrupt Enable Register\nFDCAN Tx Buffer Transmission Occurred Register\nFDCAN Tx Event FIFO Acknowledge Register\nFDCAN Tx Event FIFO Configuration Register\nFDCAN Tx Event FIFO Status Register\nFDCAN Tx Buffer Element Size Configuration Register\nFDCAN Tx FIFO/Queue Status Register\nFDCAN Extended ID and Mask Register\nFDCAN Extended ID Filter Configuration Register\nActivity\nAccept Non-matching Frames Extended\nAccept Non-matching Frames Standard\nAdd Request\nAccess to Reserved Address\nAccess to Reserved Address Enable\nAccess to Reserved Address Line\nASM Restricted Operation Mode\nApplication Watchdog\nApplication Watchdog Interrupt Enable\nApplication Watchdog Event\nApplication Watchdog Interrupt Line\nApplication Watchdog Limit\nBit Error Corrected Interrupt Enable\nBit Error Corrected Interrupt Line\nBit Error Uncorrected Interrupt Enable\nBit Error Uncorrected Interrupt Line\nBuffer Index\nBus_Off Status\nBus_Off Status\nBus_Off Status Enable\nBus_Off Status\nFDCAN Bit Rate Switching\nCycle Count\nConfiguration Change Enable\nCycle Count Max\nCycle Count Value\nAN Error Logging\nConfiguration Error\nConfiguration Error Interrupt Enable\nConfiguration Error Interrupt Line\nCancellation Finished\nCancellation Finished Interrupt Enable\nCancellation Request\nClock Stop Acknowledge\nCycle Sync Mark\nChange of Synchronization Mode\nChange of Synchronization Mode Interrupt Enable\nChange of Synchronization Mode Interrupt Line\nClock Stop Request\nCycle Start Synchronization\nCycle Time\nCycle Time Target Phase\nDisable Automatic Retransmission\nTimestamp Day\nData BIt Rate Prescaler\nDenominator Configuration\nData Last Error Code\nMessage stored to Dedicated Rx Buffer\nMessage stored to Dedicated Rx Buffer Enable\nMessage stored to Dedicated Rx Buffer Interrupt Line\nSynchronization Jump Width\nData time segment after sample point\nData time segment after sample point\nEnable Clock Calibration\nExternal Clock Synchronization\nEnable External Clock Synchronization\nEvent FIFO Acknowledge Index\nEdge Filtering during Bus Integration\nEvent FIFO Full\nEvent FIFO Fill Level\nEvent FIFO Get Index\nEvent FIFO put index\nEvent FIFO Size\nEvent FIFO Start Address\nEvent FIFO Watermark\nEnable Global Time Filtering\nExtended ID Mask\nEnable Interrupt Line 0\nEnable Interrupt Line 1\nError Level\nError Level Changed\nChange Error Level Interrupt Enable\nChange Error Level Interrupt Line\nError Logging Overflow\nError Logging Overflow Enable\nError Logging Overflow Interrupt Line\nEnable Local Time\nExpected Number of Tx Triggers\nError Passive\nError Passive\nError Passive Enable\nError Passive Interrupt Line\nExternal Synchronization Control\nEnable Timeout Counter\nEndiannes Test Value\nEvent Trigger Polarity\nEvent trigger input selection\nWarning Status\nWarning Status\nWarning Status Enable\nWarning Status Interrupt Line\nRx FIFO X Acknowledge Index\nFD Operation Enable\nRx FIFO X Data Field Size\nRx FIFO X Full\nRx FIFO X Fill Level\nRx FIFO X Get Index\nFinish Gap\nFilter Index\nFilter List Standard Start Address\nFilter List Standard Start Address\nFilter List\nFIFO X operation mode\nRx FIFO X Put Index\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nRx FIFO X Size\nRx FIFO X Start Address\nFIFO X Watermark\nGap Control Select\nGap Enable\nGap Finished Indicator\nGap Started Indicator\nGlobal Time\nGlobal Time Discontinuity\nGlobal Time Discontinuity Interrupt Enable\nGlobal Time Discontinuity Interrupt Line\nGlobal Time Error\nGlobal Time Error Interrupt Enable\nGlobal Time Error Interrupt Line\nGlobal Time Wrap\nGlobal Time Wrap Interrupt Enable\nGlobal Time Wrap Interrupt Line\nHigh Priority Message\nHigh Priority Message Enable\nHigh Priority Message Interrupt Line\nInitialization\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nInitial Reference Trigger Offset\nInitialization Watch Trigger\nInitialization Watch Trigger Interrupt Enable\nInitialization Watch Trigger Interrupt Line\nLoop Back mode\nTT Operation Control Register Locked\nTT Time Mark Register Locked\nLD of Synchronization Deviation Limit\nLast Error Code\nList Size Extended\nList Size Standard\nLocal Time\nBus Monitoring Mode\nTimestamp Month\nMessage RAM Access Failure\nMessage RAM Access Failure Enable\nMessage RAM Access Failure Interrupt Line\nMaster State\nMessage Storage Indicator\nNumerator Actual Value\nBit Rate Prescaler\nTime Preset\nNumerator Configuration Low\nNew data (buffers 0 - 31)\nNew data (buffers 32 - 63)\nNumber of Dedicated Transmit Buffers\nNext is Gap\nNon ISO Operation\nNSJW: Nominal (Re)Synchronization Jump Width.\nNominal Time segment before sample point\nNominal Time segment after sample point\nOperation Mode\nProtocol Error in Arbitration Phase (Nominal Bit Time is …\nProtocol Error in Arbitration Phase Enable\nProtocol Error in Arbitration Phase Line\nProtocol Error in Data Phase (Data Bit Time is used)\nProtocol Error in Data Phase Enable\nProtocol Error in Data Phase Line\nProtocol Exception Event\nProtocol Exception Handling Disable\nQuality of Clock Speed\nQuality of Global Time Phase\nRx Buffer Data Field Size\nBRS flag of last received FDCAN Message\nRx Buffer Start Address\nReceive Error Counter\nReceived FDCAN Message\nCore release\nESI flag of last received FDCAN Message\nRx FIFO X Full\nRx FIFO X Full Enable\nRx FIFO X Full Interrupt Line\nRx FIFO X Message Lost\nRx FIFO X Message Lost\nRx FIFO X Message Lost Enable\nRx FIFO X Message Lost Interrupt Line\nRx FIFO X New Message\nRx FIFO X New Message Enable\nRx FIFO X New Message Interrupt Line\nRx FIFO X Watermark Reached\nRx FIFO X Watermark Reached Enable\nRx FIFO X Watermark Reached Interrupt Line\nReference Identifier\nReference Message Payload Select\nReceive Error Passive\nReject Remote Frames Extended\nReject Remote Frames Standard\nRegister Time Mark Interrupt Pulse Enable\nRegister Time Mark Interrupt\nRegister Time Mark Interrupt Enable\nRegister Time Mark Interrupt Line\nReference Trigger Offset\nControl of Transmit Pin\nStart of Basic Cycle\nStart of Basic Cycle Interrupt Enable\nStart of Basic Cycle Interrupt Line\nScheduling Error 1\nScheduling Error 1 Interrupt Enable\nScheduling Error 1 Interrupt Line\nScheduling Error 2\nScheduling Error 2 Interrupt Enable\nScheduling Error 2 Interrupt Line\nActivity\nAccept Non-matching Frames Extended\nAccept Non-matching Frames Standard\nAdd Request\nAccess to Reserved Address\nAccess to Reserved Address Enable\nAccess to Reserved Address Line\nASM Restricted Operation Mode\nApplication Watchdog\nApplication Watchdog Interrupt Enable\nApplication Watchdog Event\nApplication Watchdog Interrupt Line\nApplication Watchdog Limit\nBit Error Corrected Interrupt Enable\nBit Error Corrected Interrupt Line\nBit Error Uncorrected Interrupt Enable\nBit Error Uncorrected Interrupt Line\nBuffer Index\nBus_Off Status\nBus_Off Status\nBus_Off Status Enable\nBus_Off Status\nFDCAN Bit Rate Switching\nCycle Count\nConfiguration Change Enable\nCycle Count Max\nCycle Count Value\nAN Error Logging\nConfiguration Error\nConfiguration Error Interrupt Enable\nConfiguration Error Interrupt Line\nCancellation Finished\nCancellation Finished Interrupt Enable\nCancellation Request\nClock Stop Acknowledge\nCycle Sync Mark\nChange of Synchronization Mode\nChange of Synchronization Mode Interrupt Enable\nChange of Synchronization Mode Interrupt Line\nClock Stop Request\nCycle Start Synchronization\nCycle Time\nCycle Time Target Phase\nDisable Automatic Retransmission\nTimestamp Day\nData BIt Rate Prescaler\nDenominator Configuration\nData Last Error Code\nMessage stored to Dedicated Rx Buffer\nMessage stored to Dedicated Rx Buffer Enable\nMessage stored to Dedicated Rx Buffer Interrupt Line\nSynchronization Jump Width\nData time segment after sample point\nData time segment after sample point\nEnable Clock Calibration\nExternal Clock Synchronization\nEnable External Clock Synchronization\nEvent FIFO Acknowledge Index\nEdge Filtering during Bus Integration\nEvent FIFO Full\nEvent FIFO Fill Level\nEvent FIFO Get Index\nEvent FIFO put index\nEvent FIFO Size\nEvent FIFO Start Address\nEvent FIFO Watermark\nEnable Global Time Filtering\nExtended ID Mask\nEnable Interrupt Line 0\nEnable Interrupt Line 1\nError Level\nError Level Changed\nChange Error Level Interrupt Enable\nChange Error Level Interrupt Line\nError Logging Overflow\nError Logging Overflow Enable\nError Logging Overflow Interrupt Line\nEnable Local Time\nExpected Number of Tx Triggers\nError Passive\nError Passive\nError Passive Enable\nError Passive Interrupt Line\nExternal Synchronization Control\nEnable Timeout Counter\nEndiannes Test Value\nEvent Trigger Polarity\nEvent trigger input selection\nWarning Status\nWarning Status\nWarning Status Enable\nWarning Status Interrupt Line\nRx FIFO X Acknowledge Index\nFD Operation Enable\nRx FIFO X Data Field Size\nRx FIFO X Full\nRx FIFO X Fill Level\nRx FIFO X Get Index\nFinish Gap\nFilter Index\nFilter List Standard Start Address\nFilter List Standard Start Address\nFilter List\nFIFO X operation mode\nRx FIFO X Put Index\nRx FIFO X Size\nRx FIFO X Start Address\nFIFO X Watermark\nGap Control Select\nGap Enable\nGap Finished Indicator\nGap Started Indicator\nGlobal Time\nGlobal Time Discontinuity\nGlobal Time Discontinuity Interrupt Enable\nGlobal Time Discontinuity Interrupt Line\nGlobal Time Error\nGlobal Time Error Interrupt Enable\nGlobal Time Error Interrupt Line\nGlobal Time Wrap\nGlobal Time Wrap Interrupt Enable\nGlobal Time Wrap Interrupt Line\nHigh Priority Message\nHigh Priority Message Enable\nHigh Priority Message Interrupt Line\nInitialization\nInitial Reference Trigger Offset\nInitialization Watch Trigger\nInitialization Watch Trigger Interrupt Enable\nInitialization Watch Trigger Interrupt Line\nLoop Back mode\nTT Operation Control Register Locked\nTT Time Mark Register Locked\nLD of Synchronization Deviation Limit\nLast Error Code\nList Size Extended\nList Size Standard\nLocal Time\nBus Monitoring Mode\nTimestamp Month\nMessage RAM Access Failure\nMessage RAM Access Failure Enable\nMessage RAM Access Failure Interrupt Line\nMaster State\nMessage Storage Indicator\nNumerator Actual Value\nBit Rate Prescaler\nTime Preset\nNumerator Configuration Low\nNew data (buffers 0 - 31)\nNew data (buffers 32 - 63)\nNumber of Dedicated Transmit Buffers\nNext is Gap\nNon ISO Operation\nNSJW: Nominal (Re)Synchronization Jump Width.\nNominal Time segment before sample point\nNominal Time segment after sample point\nOperation Mode\nProtocol Error in Arbitration Phase (Nominal Bit Time is …\nProtocol Error in Arbitration Phase Enable\nProtocol Error in Arbitration Phase Line\nProtocol Error in Data Phase (Data Bit Time is used)\nProtocol Error in Data Phase Enable\nProtocol Error in Data Phase Line\nProtocol Exception Event\nProtocol Exception Handling Disable\nQuality of Clock Speed\nQuality of Global Time Phase\nRx Buffer Data Field Size\nBRS flag of last received FDCAN Message\nRx Buffer Start Address\nReceive Error Counter\nReceived FDCAN Message\nCore release\nESI flag of last received FDCAN Message\nRx FIFO X Full\nRx FIFO X Full Enable\nRx FIFO X Full Interrupt Line\nRx FIFO X Message Lost\nRx FIFO X Message Lost\nRx FIFO X Message Lost Enable\nRx FIFO X Message Lost Interrupt Line\nRx FIFO X New Message\nRx FIFO X New Message Enable\nRx FIFO X New Message Interrupt Line\nRx FIFO X Watermark Reached\nRx FIFO X Watermark Reached Enable\nRx FIFO X Watermark Reached Interrupt Line\nReference Identifier\nReference Message Payload Select\nReceive Error Passive\nReject Remote Frames Extended\nReject Remote Frames Standard\nRegister Time Mark Interrupt Pulse Enable\nRegister Time Mark Interrupt\nRegister Time Mark Interrupt Enable\nRegister Time Mark Interrupt Line\nReference Trigger Offset\nControl of Transmit Pin\nStart of Basic Cycle\nStart of Basic Cycle Interrupt Enable\nStart of Basic Cycle Interrupt Line\nScheduling Error 1\nScheduling Error 1 Interrupt Enable\nScheduling Error 1 Interrupt Line\nScheduling Error 2\nScheduling Error 2 Interrupt Enable\nScheduling Error 2 Interrupt Line\nSet Global time\nStart of Matrix Cycle\nStart of Matrix Cycle Interrupt Enable\nStart of Matrix Cycle Interrupt Line\nStart of Gap\nStart of Gap Interrupt Enable\nStart of Gap Interrupt Line\nSchedule Phase Lock\nStep of Core release\nSub-step of Core release\nStop Watch Event\nStop Watch Event Interrupt Enable\nStop Watch Event Interrupt Line\nStop Watch Polarity\nStop Watch Source\nStop watch trigger input selection\nStop Watch Value\nSynchronization State\nTx Buffer Data Field Size\nTx Buffers Start Address\nTransmission Completed\nTransmission Completed Enable\nTransmission Cancellation Finished\nTransmission Cancellation Finished Enable\nTransmission Cancellation Finished Interrupt Line\nTransmission Completed Interrupt Line\nTimestamp Counter Prescaler\nTransceiver Delay Compensation\nTransmitter Delay Compensation Filter Window Length\nTransmitter Delay Compensation Offset\nTransmitter Delay Compensation Value\nTransmit Error Counter\nTx FIFO Empty\nTx FIFO Empty Enable\nTx Event FIFO Full\nTx Event FIFO Full Enable\nTx Event FIFO Full Interrupt Line\nTx FIFO Empty Interrupt Line\nTx Event FIFO Element Lost\nTx Event FIFO Element Lost\nTx Event FIFO Element Lost Enable\nTx Event FIFO Element Lost Interrupt Line\nTx Event FIFO New Entry\nTx Event FIFO New Entry Enable\nTx Event FIFO New Entry Interrupt Line\nTx Event FIFO Watermark Reached\nTx Event FIFO Watermark Reached Enable\nTx Event FIFO Watermark Reached Interrupt Line\nTest Mode Enable\nTx FIFO Free Level\nTFGI\nTx FIFO/Queue Full\nTx FIFO/Queue Mode\nTx FIFO/Queue Put Index\nTransmit FIFO/Queue Size\nTime Mark Cycle Code\nTransmission Interrupt Enable\nTime Master\nTime Mark\nRegister Time Mark Compare\nTrigger Memory Elements\nTime Mark Gap\nTime Master Priority\nTrigger Memory Start Address\nTransmission Occurred\nTimeout Counter\nTimeout Occurred\nTimeout Occurred Enable\nTimeout Occurred Interrupt Line\nTimeout Period\nTimeout Select\nTransmission Request Pending\nTimestamp Counter\nTimestamp Select\nTimestamp Wraparound\nTimestamp Wraparound Enable\nTimestamp Wraparound Interrupt Line\nTrigger Time Mark Interrupt Pulse Enable\nTrigger Time Mark Event Internal\nTrigger Time Mark Event Internal Interrupt Enable\nTrigger Time Mark Event Internal Interrupt Line\nLoop Back mode\nTx Enable Window\nTx Count Overflow\nTx Count Overflow Interrupt Enable\nTx Count Overflow Interrupt Line\nTXP\nTx Count Underflow\nTx Count Underflow Interrupt Enable\nTx Count Underflow Interrupt Line\nWatchdog configuration\nWatchdog Interrupt\nWatchdog Interrupt Enable\nWatchdog Interrupt Line\nWatchdog value\nWait for External Clock Synchronization\nWait for Event\nWait for Global Time Discontinuity\nWatch Trigger\nWatch Trigger Interrupt Enable\nWatch Trigger Interrupt Line\nExtended Identifier\nTimestamp Year\nSet Global time\nStart of Matrix Cycle\nStart of Matrix Cycle Interrupt Enable\nStart of Matrix Cycle Interrupt Line\nStart of Gap\nStart of Gap Interrupt Enable\nStart of Gap Interrupt Line\nSchedule Phase Lock\nStep of Core release\nSub-step of Core release\nStop Watch Event\nStop Watch Event Interrupt Enable\nStop Watch Event Interrupt Line\nStop Watch Polarity\nStop Watch Source\nStop watch trigger input selection\nStop Watch Value\nSynchronization State\nTx Buffer Data Field Size\nTx Buffers Start Address\nTransmission Completed\nTransmission Completed Enable\nTransmission Cancellation Finished\nTransmission Cancellation Finished Enable\nTransmission Cancellation Finished Interrupt Line\nTransmission Completed Interrupt Line\nTimestamp Counter Prescaler\nTransceiver Delay Compensation\nTransmitter Delay Compensation Filter Window Length\nTransmitter Delay Compensation Offset\nTransmitter Delay Compensation Value\nTransmit Error Counter\nTx FIFO Empty\nTx FIFO Empty Enable\nTx Event FIFO Full\nTx Event FIFO Full Enable\nTx Event FIFO Full Interrupt Line\nTx FIFO Empty Interrupt Line\nTx Event FIFO Element Lost\nTx Event FIFO Element Lost\nTx Event FIFO Element Lost Enable\nTx Event FIFO Element Lost Interrupt Line\nTx Event FIFO New Entry\nTx Event FIFO New Entry Enable\nTx Event FIFO New Entry Interrupt Line\nTx Event FIFO Watermark Reached\nTx Event FIFO Watermark Reached Enable\nTx Event FIFO Watermark Reached Interrupt Line\nTest Mode Enable\nTx FIFO Free Level\nTFGI\nTx FIFO/Queue Full\nTx FIFO/Queue Mode\nTx FIFO/Queue Put Index\nTransmit FIFO/Queue Size\nTime Mark Cycle Code\nTransmission Interrupt Enable\nTime Master\nTime Mark\nRegister Time Mark Compare\nTrigger Memory Elements\nTime Mark Gap\nTime Master Priority\nTrigger Memory Start Address\nTransmission Occurred\nTimeout Counter\nTimeout Occurred\nTimeout Occurred Enable\nTimeout Occurred Interrupt Line\nTimeout Period\nTimeout Select\nTransmission Request Pending\nTimestamp Counter\nTimestamp Select\nTimestamp Wraparound\nTimestamp Wraparound Enable\nTimestamp Wraparound Interrupt Line\nTrigger Time Mark Interrupt Pulse Enable\nTrigger Time Mark Event Internal\nTrigger Time Mark Event Internal Interrupt Enable\nTrigger Time Mark Event Internal Interrupt Line\nLoop Back mode\nTx Enable Window\nTx Count Overflow\nTx Count Overflow Interrupt Enable\nTx Count Overflow Interrupt Line\nTXP\nTx Count Underflow\nTx Count Underflow Interrupt Enable\nTx Count Underflow Interrupt Line\nWatchdog configuration\nWatchdog Interrupt\nWatchdog Interrupt Enable\nWatchdog Interrupt Line\nWatchdog value\nWait for External Clock Synchronization\nWait for Event\nWait for Global Time Discontinuity\nWatch Trigger\nWatch Trigger Interrupt Enable\nWatch Trigger Interrupt Line\nExtended Identifier\nTimestamp Year\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCORDIC co-processor.\nControl and status register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nResult register.\nArgument register.\nControl and status register.\nWidth of input data.\nEnable DMA wread channel.\nEnable DMA write channel.\nReturns the argument unchanged.\nFunction.\nEnable interrupt.\nCalls <code>U::from(self)</code>.\nNumber of arguments expected by the WDATA register.\nNumber of results in the RDATA register.\nPrecision required (number of iterations/cycles), where …\nWidth of output data.\nResult ready flag.\nScaling factor (2^-n for arguments, 2^n for results).\nWidth of input data.\nEnable DMA wread channel.\nEnable DMA write channel.\nFunction.\nEnable interrupt.\nNumber of arguments expected by the WDATA register.\nNumber of results in the RDATA register.\nPrecision required (number of iterations/cycles), where …\nWidth of output data.\nResult ready flag.\nScaling factor (2^-n for arguments, 2^n for results).\nArctangent function.\nArctanh function.\nUse 16 bit input values.\nUse 16 bit output values.\nUse 32 bit input values.\nUse 32 bit output values.\nCosine function.\nHyperbolic Cosine function.\nHyperbolic Sine function.\n12 iterations.\n16 iterations.\n20 iterations.\n24 iterations.\n28 iterations.\n32 iterations.\n36 iterations.\n4 iterations.\n40 iterations.\n44 iterations.\n48 iterations.\n52 iterations.\n56 iterations.\n60 iterations.\n8 iterations.\nModulus function.\nNatural Logarithm function.\nOnly single argument write is needed for next calculation.\nOnly single result value will be returned. After a single …\nTwo argument writes need to be performed for next …\nTwo return reads need to be performed. After two reads …\nPhase function.\nSine function.\nSquare Root function.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCyclic Redundancy Check calculation unit\nControl register\nData register\nData register - half-word sized\nData register - byte sized\nReturns the argument unchanged.\nIndependent Data register\nInitial CRC value\nCalls <code>U::from(self)</code>.\nCRC polynomial\nControl register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nPolynomial size\nRESET bit\nReverse input data\nReverse output data\nPolynomial size\nRESET bit\nReverse input data\nReverse output data\nBit reversal done by byte\nBit reversal done by half-word\nBit order not affected\nBit order not affected\n16-bit polynomial\n32-bit polynomial\n7-bit polynomial\n8-bit polynomial\nBit reversed output\nBit reversal done by word\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nClock recovery system\nconfiguration register\ncontrol register\nReturns the argument unchanged.\ninterrupt flag clear register\nCalls <code>U::from(self)</code>.\ninterrupt and status register\nconfiguration register\ncontrol register\ninterrupt flag clear register\ninterrupt and status register\nAutomatic trimming enable\nFrequency error counter enable\nError clear flag\nError flag\nSynchronization or trimming error interrupt enable\nExpected SYNC clear flag\nExpected SYNC flag\nExpected SYNC interrupt enable\nFrequency error capture\nFrequency error direction\nFrequency error limit\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCounter reload value\nAutomatic trimming enable\nFrequency error counter enable\nError clear flag\nError flag\nSynchronization or trimming error interrupt enable\nExpected SYNC clear flag\nExpected SYNC flag\nExpected SYNC interrupt enable\nFrequency error capture\nFrequency error direction\nFrequency error limit\nCounter reload value\nGenerate software SYNC event\nSYNC divider\nSYNC error\nSYNC missed\nSYNC event OK clear flag\nSYNC event OK flag\nSYNC event OK interrupt enable\nSYNC polarity selection\nSYNC signal source selection\nSYNC warning clear flag\nSYNC warning flag\nSYNC warning interrupt enable\nHSI48 oscillator smooth trimming\nTrimming overflow or underflow\nGenerate software SYNC event\nSYNC divider\nSYNC error\nSYNC missed\nSYNC event OK clear flag\nSYNC event OK flag\nSYNC event OK interrupt enable\nSYNC polarity selection\nSYNC signal source selection\nSYNC warning clear flag\nSYNC warning flag\nSYNC warning interrupt enable\nHSI48 oscillator smooth trimming\nTrimming overflow or underflow\nGPIO selected as SYNC signal source\nLSE selected as SYNC signal source\nUSB SOF selected as SYNC signal source\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDigital-to-analog converter\ncalibration control register\ncontrol register\nchannel 12-bit left-aligned data holding register\ndual 12-bit left aligned data holding register\nchannel 12-bit right-aligned data holding register\ndual 12-bit right-aligned data holding register\nchannel 8-bit right-aligned data holding register\ndual 8-bit right aligned data holding register\nchannel data output register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nmode control register\nsample and hold hold time register\nsample and hold refresh time register\nsample and hold sample time register\nstatus register\nsoftware trigger register\ncalibration control register\ncontrol register\nchannel 12-bit left-aligned data holding register\ndual 12-bit left aligned data holding register\nchannel 12-bit right-aligned data holding register\ndual 12-bit right-aligned data holding register\nchannel 8-bit right-aligned data holding register\ndual 8-bit right aligned data holding register\nchannel data output register\nmode control register\nsample and hold hold time register\nsample and hold refresh time register\nsample and hold sample time register\nstatus register\nsoftware trigger register\nchannel busy writing sample time flag\nchannel calibration offset status\nDAC channel calibration enable\nchannel 12-bit left-aligned data\nchannel 12-bit left-aligned data\nchannel 12-bit right-aligned data\nchannel 12-bit right-aligned data\nchannel 8-bit right-aligned data\nchannel 8-bit right-aligned data\nchannel DMA enable\nchannel DMA underrun flag\nchannel DMA Underrun Interrupt enable\nchannel data output\nchannel enable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nchannel mask/amplitude selector\nDAC channel mode\nchannel offset trimming value\nchannel busy writing sample time flag\nchannel calibration offset status\nDAC channel calibration enable\nchannel 12-bit left-aligned data\nchannel 12-bit left-aligned data\nchannel 12-bit right-aligned data\nchannel 12-bit right-aligned data\nchannel 8-bit right-aligned data\nchannel 8-bit right-aligned data\nchannel DMA enable\nchannel DMA underrun flag\nchannel DMA Underrun Interrupt enable\nchannel data output\nchannel enable\nchannel mask/amplitude selector\nDAC channel mode\nchannel offset trimming value\nchannel software trigger\nchannel trigger enable\nchannel hold time\nchannel refresh time\nchannel sample time\nchannel trigger selection\nchannel noise/triangle wave generation enable\nchannel software trigger\nchannel trigger enable\nchannel hold time\nchannel refresh time\nchannel sample time\nchannel trigger selection\nchannel noise/triangle wave generation enable\nWave generation disabled\nNoise wave generation enabled\nNormal mode, external pin only, buffer disabled\nNormal mode, external pin only, buffer enabled\nNormal mode, external pin and internal peripherals, buffer …\nNormal mode, internal peripherals only, buffer disabled\nSample and hold mode, external pin only, buffer enabled\nSample and hold mode, external pin and internal …\nSample and hold mode, external pin and internal …\nSample and hold mode, internal peripherals only, buffer …\nTriangle wave generation enabled\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nDebug support\nAPB1L peripheral freeze register\nAPB2 peripheral freeze register\nAPB3 peripheral freeze register\nAPB4 peripheral freeze register\nConfiguration register\nReturns the argument unchanged.\nIdentity code\nCalls <code>U::from(self)</code>.\nAPB1L peripheral freeze register\nAPB2 peripheral freeze register\nAPB3 peripheral freeze register\nAPB4 peripheral freeze register\nConfiguration register\nIdentity code\nD1 debug clock enable enable\nD3 debug clock enable enable\nAllow debug in D1 Sleep mode\nAllow debug in D1 Standby mode\nAllow debug in D1 Stop mode\nDevice ID\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nHRTIM stop in debug mode\nI2C1 SMBUS timeout stop in debug mode\nI2C2 SMBUS timeout stop in debug mode\nI2C3 SMBUS timeout stop in debug mode\nI2C4 SMBUS timeout stop in debug mode\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nIndependent watchdog for D1 stop in debug mode\nLPTIM1 stop in debug mode\nLPTIM2 stop in debug mode\nLPTIM3 stop in debug mode\nLPTIM4 stop in debug mode\nLPTIM5 stop in debug mode\nRevision ID\nRTC stop in debug mode\nD1 debug clock enable enable\nD3 debug clock enable enable\nAllow debug in D1 Sleep mode\nAllow debug in D1 Standby mode\nAllow debug in D1 Stop mode\nDevice ID\nHRTIM stop in debug mode\nI2C1 SMBUS timeout stop in debug mode\nI2C2 SMBUS timeout stop in debug mode\nI2C3 SMBUS timeout stop in debug mode\nI2C4 SMBUS timeout stop in debug mode\nIndependent watchdog for D1 stop in debug mode\nLPTIM1 stop in debug mode\nLPTIM2 stop in debug mode\nLPTIM3 stop in debug mode\nLPTIM4 stop in debug mode\nLPTIM5 stop in debug mode\nRevision ID\nRTC stop in debug mode\nTIM1 stop in debug mode\nTIM12 stop in debug mode\nTIM13 stop in debug mode\nTIM14 stop in debug mode\nTIM15 stop in debug mode\nTIM16 stop in debug mode\nTIM17 stop in debug mode\nTIM2 stop in debug mode\nTIM3 stop in debug mode\nTIM4 stop in debug mode\nTIM5 stop in debug mode\nTIM6 stop in debug mode\nTIM7 stop in debug mode\nTIM8 stop in debug mode\nTrace clock enable enable\nExternal trigger output enable\nWWDG1 stop in debug mode\nTIM1 stop in debug mode\nTIM12 stop in debug mode\nTIM13 stop in debug mode\nTIM14 stop in debug mode\nTIM15 stop in debug mode\nTIM16 stop in debug mode\nTIM17 stop in debug mode\nTIM2 stop in debug mode\nTIM3 stop in debug mode\nTIM4 stop in debug mode\nTIM5 stop in debug mode\nTIM6 stop in debug mode\nTIM7 stop in debug mode\nTIM8 stop in debug mode\nTrace clock enable enable\nExternal trigger output enable\nWWDG1 stop in debug mode\nDigital camera interface\ncontrol register 1\ncrop window size\ncrop window start\ndata register\nembedded synchronization code register\nembedded synchronization unmask register\nReturns the argument unchanged.\ninterrupt clear register\ninterrupt enable register\nCalls <code>U::from(self)</code>.\nmasked interrupt status register\nraw interrupt status register\nstatus register\ncontrol register 1\ncrop window size\ncrop window start\ndata register\nembedded synchronization code register\nembedded synchronization unmask register\ninterrupt clear register\ninterrupt enable register\nmasked interrupt status register\nraw interrupt status register\nstatus register\nData byte 0\nData byte 1\nData byte 2\nData byte 3\nCapture count\nCapture enable\nCapture mode\nCrop feature\nExtended data mode\nDCMI enable\nSynchronization error interrupt enable\nSynchronization error interrupt status clear\nSynchronization error masked interrupt status\nSynchronization error raw interrupt status\nEmbedded synchronization select\nFrame capture rate control\nFrame end delimiter code\nFrame end delimiter unmask\nFIFO not empty\nCapture complete interrupt enable\nCapture complete interrupt status clear\nCapture complete masked interrupt status\nCapture complete raw interrupt status\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nFrame start delimiter code\nFrame start delimiter unmask\nHorizontal offset count\nHorizontal synchronization polarity\nHSYNC\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nJPEG format\nLine end delimiter code\nLine end delimiter unmask\nLine interrupt enable\nline interrupt status clear\nLine masked interrupt status\nLine raw interrupt status\nLine start delimiter code\nLine start delimiter unmask\nOverrun interrupt enable\nOverrun interrupt status clear\nOverrun masked interrupt status\nOverrun raw interrupt status\nPixel clock polarity\nData byte 0\nData byte 1\nData byte 2\nData byte 3\nCapture count\nCapture enable\nCapture mode\nCrop feature\nExtended data mode\nDCMI enable\nSynchronization error interrupt enable\nSynchronization error interrupt status clear\nSynchronization error masked interrupt status\nSynchronization error raw interrupt status\nEmbedded synchronization select\nFrame capture rate control\nFrame end delimiter code\nFrame end delimiter unmask\nFIFO not empty\nCapture complete interrupt enable\nCapture complete interrupt status clear\nCapture complete masked interrupt status\nCapture complete raw interrupt status\nFrame start delimiter code\nFrame start delimiter unmask\nHorizontal offset count\nHorizontal synchronization polarity\nHSYNC\nJPEG format\nLine end delimiter code\nLine end delimiter unmask\nLine interrupt enable\nline interrupt status clear\nLine masked interrupt status\nLine raw interrupt status\nLine start delimiter code\nLine start delimiter unmask\nOverrun interrupt enable\nOverrun interrupt status clear\nOverrun masked interrupt status\nOverrun raw interrupt status\nPixel clock polarity\nVertical line count\nVertical synchronization polarity\nVertical start line count\nVSYNC\nVSYNC interrupt enable\nVertical synch interrupt status clear\nVSYNC masked interrupt status\nVSYNC raw interrupt status\nVertical line count\nVertical synchronization polarity\nVertical start line count\nVSYNC\nVSYNC interrupt enable\nVertical synch interrupt status clear\nVSYNC masked interrupt status\nVSYNC raw interrupt status\nDMA controller\nStream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR …\nstream x configuration register\nstream x FIFO control register\nReturns the argument unchanged.\nReturns the argument unchanged.\nlow interrupt flag clear register\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nlow interrupt status register\nstream x memory 0 address register\nstream x memory 1 address register\nstream x number of data register\nstream x peripheral address register\nStream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR …\nDMA2D\nDMA2D AXI master timer configuration register\nDMA2D background CLUT memory address register\nDMA2D background color register\nDMA2D background memory address register\nDMA2D background offset register\nDMA2D background PFC control register\nDMA2D control register\nDMA2D foreground CLUT memory address register\nDMA2D foreground color register\nDMA2D foreground memory address register\nDMA2D foreground offset register\nDMA2D foreground PFC control register\nReturns the argument unchanged.\nDMA2D interrupt flag clear register\nCalls <code>U::from(self)</code>.\nDMA2D Interrupt Status Register\nDMA2D line watermark register\nDMA2D number of line register\nDMA2D output color register\nDMA2D output memory address register\nDMA2D output offset register\nDMA2D output PFC control register\nDMA2D AXI master timer configuration register\nDMA2D background CLUT memory address register\nDMA2D background color register\nDMA2D background memory address register\nDMA2D background offset register\nDMA2D background PFC control register\nDMA2D control register\nDMA2D foreground CLUT memory address register\nDMA2D foreground color register\nDMA2D foreground memory address register\nDMA2D foreground offset register\nDMA2D foreground PFC control register\nDMA2D interrupt flag clear register\nDMA2D Interrupt Status Register\nDMA2D line watermark register\nDMA2D number of line register\nDMA2D output color register\nDMA2D output memory address register\nDMA2D output offset register\nDMA2D output PFC control register\nAbort This bit can be used to abort the current transfer. …\nAlpha Inverted This bit inverts the alpha value. Once the …\nAlpha Inverted This bit inverts the alpha value. Once the …\nAlpha Inverted This bit inverts the alpha value. Once the …\nAlpha value These bits define a fixed alpha channel value …\nAlpha value These bits define a fixed alpha channel value …\nAlpha Channel Value These bits define the alpha channel of …\nAlpha mode These bits define which alpha channel value to …\nAlpha mode These bits select the alpha channel value to be …\nBlue Value These bits define the blue value for the A4 or …\nBlue Value These bits defines the blue value for the A4 or …\nBlue Value These bits define the blue value of the output …\nClear CLUT access error interrupt flag Programming this …\nCLUT access error interrupt enable This bit is set and …\nCLUT access error interrupt flag This bit is set when the …\nClear configuration error interrupt flag Programming this …\nCLUT Color mode These bits define the color format of the …\nCLUT color mode This bit defines the color format of the …\nClear CLUT transfer complete interrupt flag Programming …\nConfiguration Error Interrupt Enable This bit is set and …\nConfiguration error interrupt flag This bit is set when …\nColor mode These bits define the color format of the …\nColor mode These bits defines the color format of the …\nColor mode These bits define the color format of the …\nCLUT size These bits define the size of the CLUT used for …\nCLUT size These bits define the size of the CLUT used for …\nChroma Sub-Sampling These bits define the chroma …\nCLUT transfer complete interrupt enable This bit is set …\nClear transfer complete interrupt flag Programming this …\nCLUT transfer complete interrupt flag This bit is set when …\nClear Transfer error interrupt flag Programming this bit …\nClear transfer watermark interrupt flag Programming this …\nDead Time Dead time value in the AXI clock cycle inserted …\nEnable Enables the dead time functionality.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nGreen Value These bits define the green value for the A4 …\nGreen Value These bits defines the green value for the A4 …\nGreen Value These bits define the green value of the …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nLine offset Line offset used for the background image …\nLine offset Line offset used for the foreground expressed …\nLine Offset Line offset used for the output (expressed in …\nLine watermark These bits allow to configure the line …\nMemory address Address of the data used for the CLUT …\nMemory address Address of the data used for the background …\nMemory Address Address of the data used for the CLUT …\nMemory address Address of the data used for the foreground …\nMemory Address Address of the data used for the output …\nDMA2D mode This bit is set and cleared by software. It …\nNumber of lines Number of lines of the area to be …\nPixel per lines Number of pixels per lines of the area to …\nRed Blue Swap This bit allows to swap the R &amp; B to support …\nRed Blue Swap This bit allows to swap the R &amp; B to support …\nRed Blue Swap This bit allows to swap the R &amp; B to support …\nRed Value These bits define the red value for the A4 or A8 …\nRed Value These bits defines the red value for the A4 or …\nRed Value These bits define the red value of the output …\nSwap Bytes\nAbort This bit can be used to abort the current transfer. …\nAlpha Inverted This bit inverts the alpha value. Once the …\nAlpha Inverted This bit inverts the alpha value. Once the …\nAlpha Inverted This bit inverts the alpha value. Once the …\nAlpha value These bits define a fixed alpha channel value …\nAlpha value These bits define a fixed alpha channel value …\nAlpha Channel Value These bits define the alpha channel of …\nAlpha mode These bits define which alpha channel value to …\nAlpha mode These bits select the alpha channel value to be …\nBlue Value These bits define the blue value for the A4 or …\nBlue Value These bits defines the blue value for the A4 or …\nBlue Value These bits define the blue value of the output …\nClear CLUT access error interrupt flag Programming this …\nCLUT access error interrupt enable This bit is set and …\nCLUT access error interrupt flag This bit is set when the …\nClear configuration error interrupt flag Programming this …\nCLUT Color mode These bits define the color format of the …\nCLUT color mode This bit defines the color format of the …\nClear CLUT transfer complete interrupt flag Programming …\nConfiguration Error Interrupt Enable This bit is set and …\nConfiguration error interrupt flag This bit is set when …\nColor mode These bits define the color format of the …\nColor mode These bits defines the color format of the …\nColor mode These bits define the color format of the …\nCLUT size These bits define the size of the CLUT used for …\nCLUT size These bits define the size of the CLUT used for …\nChroma Sub-Sampling These bits define the chroma …\nCLUT transfer complete interrupt enable This bit is set …\nClear transfer complete interrupt flag Programming this …\nCLUT transfer complete interrupt flag This bit is set when …\nClear Transfer error interrupt flag Programming this bit …\nClear transfer watermark interrupt flag Programming this …\nDead Time Dead time value in the AXI clock cycle inserted …\nEnable Enables the dead time functionality.\nGreen Value These bits define the green value for the A4 …\nGreen Value These bits defines the green value for the A4 …\nGreen Value These bits define the green value of the …\nLine offset Line offset used for the background image …\nLine offset Line offset used for the foreground expressed …\nLine Offset Line offset used for the output (expressed in …\nLine watermark These bits allow to configure the line …\nMemory address Address of the data used for the CLUT …\nMemory address Address of the data used for the background …\nMemory Address Address of the data used for the CLUT …\nMemory address Address of the data used for the foreground …\nMemory Address Address of the data used for the output …\nDMA2D mode This bit is set and cleared by software. It …\nNumber of lines Number of lines of the area to be …\nPixel per lines Number of pixels per lines of the area to …\nRed Blue Swap This bit allows to swap the R &amp; B to support …\nRed Blue Swap This bit allows to swap the R &amp; B to support …\nRed Blue Swap This bit allows to swap the R &amp; B to support …\nRed Value These bits define the red value for the A4 or A8 …\nRed Value These bits defines the red value for the A4 or …\nRed Value These bits define the red value of the output …\nSwap Bytes\nStart This bit is set to start the automatic loading of …\nStart This bit can be used to launch the DMA2D according …\nStart This bit can be set to start the automatic loading …\nSuspend This bit can be used to suspend the current …\nTransfer complete interrupt enable This bit is set and …\nTransfer complete interrupt flag This bit is set when a …\nTransfer error interrupt enable This bit is set and …\nTransfer error interrupt flag This bit is set when an …\nTransfer watermark interrupt enable This bit is set and …\nTransfer watermark interrupt flag This bit is set when the …\nStart This bit is set to start the automatic loading of …\nStart This bit can be used to launch the DMA2D according …\nStart This bit can be set to start the automatic loading …\nSuspend This bit can be used to suspend the current …\nTransfer complete interrupt enable This bit is set and …\nTransfer complete interrupt flag This bit is set when a …\nTransfer error interrupt enable This bit is set and …\nTransfer error interrupt flag This bit is set when an …\nTransfer watermark interrupt enable This bit is set and …\nTransfer watermark interrupt flag This bit is set when the …\nColor mode A4\nColor mode A4\nColor mode A8\nColor mode A8\nTransfer abort requested\nColor mode AL44\nColor mode AL44\nColor mode AL88\nColor mode AL88\nColor mode ARGB1555\nColor mode ARGB1555\nARGB1555\nColor mode ARGB4444\nColor mode ARGB4444\nARGB4444\nCLUT color format ARGB8888\nColor mode ARGB8888\nCLUT color format ARGB8888\nColor mode ARGB8888\nARGB8888\nClear the CAEIF flag in the ISR register\nClear the CEIF flag in the ISR register\nClear the CTCIF flag in the ISR register\nClear the TCIF flag in the ISR register\nClear the TEIF flag in the ISR register\nClear the TWIF flag in the ISR register\nInverted alpha\nInverted alpha\nInverted alpha\nColor mode L4\nColor mode L4\nColor mode L8\nColor mode L8\nMemory-to-memory (FG fetch only)\nMemory-to-memory with PFC (FG fetch only with FG PFC …\nMemory-to-memory with blending (FG and BG fetch with PFC …\nMultiply with value in ALPHA[7:0]\nMultiply with value in ALPHA[7:0]\nNo modification of alpha channel\nNo modification of alpha channel\nRegister-to-memory\nNo Red Blue Swap (RGB or ARGB)\nNo Red Blue Swap (RGB or ARGB)\nNo Red Blue Swap (RGB or ARGB)\nRegular byte order\nRegular alpha\nRegular alpha\nRegular alpha\nReplace with value in ALPHA[7:0]\nReplace with value in ALPHA[7:0]\nColor mode RGB565\nColor mode RGB565\nRGB565\nCLUT color format RGB888\nColor mode RGB888\nCLUT color format RGB888\nColor mode RGB888\nRGB888\nStart the automatic loading of the CLUT\nLaunch the DMA2D\nStart the automatic loading of the CLUT\nRed Blue Swap (BGR or ABGR)\nRed Blue Swap (BGR or ABGR)\nRed Blue Swap (BGR or ABGR)\nBytes are swapped two by two\nColor mode YCbCr\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nstream x configuration register\nstream x FIFO control register\ninterrupt register\nstream x number of data register\nCircular mode enabled\nCurrent target (only in double buffer mode)\nDouble buffer mode enabled\nData transfer direction\nDirect mode disable\nDirect mode error interrupt enable\nStream x direct mode error interrupt flag (x=3..0)\nStream enable / flag stream ready when read low\nFIFO error interrupt enable\nStream x FIFO error interrupt flag (x=3..0)\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nFIFO status\nFIFO threshold selection\nHalf transfer interrupt enable\nStream x half transfer interrupt flag (x=3..0)\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nMemory burst transfer configuration\nMemory increment mode enabled\nMemory data size\nNumber of data items to transfer\nPeripheral burst transfer configuration\nPeripheral flow controller\nPeripheral increment mode enabled\nPeripheral increment offset size\nPriority level\nPeripheral data size\nCircular mode enabled\nCurrent target (only in double buffer mode)\nDouble buffer mode enabled\nData transfer direction\nDirect mode disable\nDirect mode error interrupt enable\nStream x direct mode error interrupt flag (x=3..0)\nStream enable / flag stream ready when read low\nFIFO error interrupt enable\nStream x FIFO error interrupt flag (x=3..0)\nFIFO status\nFIFO threshold selection\nHalf transfer interrupt enable\nStream x half transfer interrupt flag (x=3..0)\nMemory burst transfer configuration\nMemory increment mode enabled\nMemory data size\nNumber of data items to transfer\nPeripheral burst transfer configuration\nPeripheral flow controller\nPeripheral increment mode enabled\nPeripheral increment offset size\nPriority level\nPeripheral data size\nTransfer complete interrupt enable\nStream x transfer complete interrupt flag (x = 3..0)\nTransfer error interrupt enable\nStream x transfer error interrupt flag (x=3..0)\nEnable bufferable transfers\nTransfer complete interrupt enable\nStream x transfer complete interrupt flag (x = 3..0)\nTransfer error interrupt enable\nStream x transfer error interrupt flag (x=3..0)\nEnable bufferable transfers\nHalf-word (16-bit)\nWord (32-bit)\nByte (8-bit)\nDirect mode is disabled\nThe DMA is the flow controller\nFIFO is empty\nDirect mode is enabled\nThe offset size for the peripheral address calculation is …\nFIFO is full\nFull FIFO\n1/2 full FIFO\nHigh\nIncremental burst of 16 beats\nIncremental burst of 4 beats\nIncremental burst of 8 beats\nLow\nMedium\nThe current target memory is Memory 0\nThe current target memory is Memory 1\nMemory-to-memory\nMemory-to-peripheral\nThe peripheral is the flow controller\nPeripheral-to-memory\nThe offset size for the peripheral address calculation is …\n1/4 full FIFO\n0 &lt; fifo_level &lt; 1/4\n1/4 &lt;= fifo_level &lt; 1/2\n1/2 &lt;= fifo_level &lt; 3/4\n3/4 &lt;= fifo_level &lt; full\nSingle transfer\n3/4 full FIFO\nVery high\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nDMAMUX\nDMAMux - DMA request line multiplexer channel x control …\nDMAMUX request line multiplexer interrupt clear flag …\nDMAMUX request line multiplexer interrupt channel status …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDMAMux - DMA request generator clear flag register\nDMAMux - DMA request generator channel x control register\nDMAMux - DMA request generator status register\nDMAMux - DMA request line multiplexer channel x control …\nDMAMUX request line multiplexer interrupt channel status …\nDMAMux - DMA request generator channel x control register\nDMAMux - DMA request generator status register\nInput DMA request line selected\nEvent generation enable/disable\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nDMA request generator channel enable/disable\nNumber of DMA requests to generate Defines the number of …\nDMA request generator trigger event type selection Defines …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nNumber of DMA requests to forward Defines the number of …\nTrigger event overrun flag The flag is set when a trigger …\nInterrupt enable at trigger event overrun\nSynchronous operating mode enable/disable\nInput DMA request line selected\nEvent generation enable/disable\nDMA request generator channel enable/disable\nNumber of DMA requests to generate Defines the number of …\nDMA request generator trigger event type selection Defines …\nNumber of DMA requests to forward Defines the number of …\nTrigger event overrun flag The flag is set when a trigger …\nInterrupt enable at trigger event overrun\nSynchronous operating mode enable/disable\nDMA request trigger input selected\nSynchronization overrun event flag\nInterrupt enable at synchronization event overrun\nSynchronization event type selector Defines the …\nSynchronization input selected\nDMA request trigger input selected\nSynchronization overrun event flag\nInterrupt enable at synchronization event overrun\nSynchronization event type selector Defines the …\nSynchronization input selected\nRising and falling edges\nFalling edge\nNo event, i.e. no synchronization nor detection\nRising edge\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nEthernet Peripheral\nEthernet: DMA mode register (DMA)\nEthernet: media access control (MAC)\nEthernet: MTL mode register (MTL)\nChannel current application receive buffer register\nChannel current application receive descriptor register\nChannel current application transmit buffer register\nChannel current application transmit descriptor register\nChannel control register\nChannel interrupt enable register\nChannel missed frame count register\nChannel receive control register\nChannel Rx descriptor list address register\nChannel Rx descriptor tail pointer register\nChannel Rx interrupt watchdog timer register\nChannel Rx descriptor ring length register\nChannel status register\nChannel transmit control register\nChannel Tx descriptor list address register\nChannel Tx descriptor tail pointer register\nChannel Tx descriptor ring length register\nDebug status register\nInterrupt status register\nDMA mode register\nSystem bus mode register\nEthernet: DMA mode register (DMA)\nEthernet: media access control (MAC)\nEthernet: MTL mode register (MTL)\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n1-microsecond-tick counter register\nAddress 0 high register\nAddress 0 low register\nAuxiliary control register\nAddress 1/2/3 high register\nAddress 1/2/3 low register\nARP address register\nAuxiliary timestamp nanoseconds register\nAuxiliary timestamp seconds register\nOperating mode configuration register\nDebug register\nExtended operating mode configuration register\nHash Table 0/1 register\nHW feature 1 register\nHW feature 2 register\nInterrupt enable register\nInterrupt status register\nInner VLAN inclusion register\nMACL3A00R\nLayer3 address 0 filter 1 Register\nLayer3 address 1 filter 0 register\nLayer3 address 1 filter 1 register\nLayer3 Address 2 filter 0 register\nLayer3 address 2 filter 1 Register\nLayer3 Address 3 filter 0 register\nLayer3 address 3 filter 1 register\nL3 and L4 control 0 register\nL3 and L4 control 1 register\nLayer4 address filter 0 register\nLayer 4 address filter 1 register\nLPI control status register\nLPI entry timer register\nLog message interval register\nLPI timers control register\nMDIO address register\nMDIO data register\nPMT control status register\nPacket filtering control register\nPTP Offload control register\nPPS control register\nPPS interval register\nPPS target time nanoseconds register\nPPS target time seconds register\nPPS width register\nTx Queue flow control register\nRemove wakeup packet filter register\nRx flow control register\nRx Tx status register\nPTP Source Port Identity 0 Register\nPTP Source port identity 1 register\nPTP Source port identity 2 register\nSub-second increment register\nSystem time nanoseconds register\nSystem time nanoseconds update register\nSystem time seconds register\nSystem time seconds update register\nTimestamp addend register\nTimestamp control Register\nTimestamp Egress asymmetric correction register\nTimestamp Egress correction nanosecond register\nTimestamp Ingress asymmetric correction register\nTimestamp Ingress correction nanosecond register\nTimestamp status register\nTx timestamp status nanoseconds register\nTx timestamp status seconds register\nVLAN Hash table register\nVLAN inclusion register\nVersion register\nVLAN tag register\nWatchdog timeout register\nMMC control register\nMMC Rx interrupt register\nMMC Rx interrupt mask register\nMMC Tx interrupt register\nMMC Tx interrupt mask register\nInterrupt status Register\nOperating mode Register\nQueue interrupt control status Register\nRx queue debug register\nRx queue missed packet and overflow counter register\nRx queue operating mode register\nTx queue debug Register\nTx queue operating mode Register\nTx queue underflow register\nRx alignment error packets register\nRx CRC error packets register\nRx LPI transition counter register\nRx LPI microsecond counter register\nRx unicast packets good register\nTx LPI transition counter register\nTx LPI microsecond timer register\nTx multiple collision good packets register\nTx packet count good register\nTx single collision good packets register\nChannel current application receive buffer register\nChannel current application receive descriptor register\nChannel current application transmit buffer register\nChannel current application transmit descriptor register\nChannel control register\nChannel interrupt enable register\nChannel missed frame count register\nChannel receive control register\nChannel Rx descriptor list address register\nChannel Rx descriptor tail pointer register\nChannel Rx interrupt watchdog timer register\nChannel Rx descriptor ring length register\nChannel status register\nChannel transmit control register\nChannel Tx descriptor list address register\nChannel Tx descriptor tail pointer register\nChannel Tx descriptor ring length register\nDebug status register\nInterrupt status register\nDMA mode register\nSystem bus mode register\n1-microsecond-tick counter register\nAddress 0 high register\nAddress 0 low register\nAuxiliary control register\nAddress 1/2/3 high register\nAddress 1/2/3 low register\nARP address register\nAuxiliary timestamp nanoseconds register\nAuxiliary timestamp seconds register\nOperating mode configuration register\nDebug register\nExtended operating mode configuration register\nHash Table 0/1 register\nHW feature 1 register\nHW feature 2 register\nInterrupt enable register\nInterrupt status register\nInner VLAN inclusion register\nMACL3A00R\nLayer3 address 0 filter 1 Register\nLayer3 address 1 filter 0 register\nLayer3 address 1 filter 1 register\nLayer3 Address 2 filter 0 register\nLayer3 address 2 filter 1 Register\nLayer3 Address 3 filter 0 register\nLayer3 address 3 filter 1 register\nL3 and L4 control 0 register\nL3 and L4 control 1 register\nLayer4 address filter 0 register\nLayer 4 address filter 1 register\nLPI control status register\nLPI entry timer register\nLog message interval register\nLPI timers control register\nMDIO address register\nMDIO data register\nPMT control status register\nPacket filtering control register\nPTP Offload control register\nPPS control register\nPPS interval register\nPPS target time nanoseconds register\nPPS target time seconds register\nPPS width register\nTx Queue flow control register\nRemove wakeup packet filter register\nRx flow control register\nRx Tx status register\nPTP Source Port Identity 0 Register\nPTP Source port identity 1 register\nPTP Source port identity 2 register\nSub-second increment register\nSystem time nanoseconds register\nSystem time nanoseconds update register\nSystem time seconds register\nSystem time seconds update register\nTimestamp addend register\nTimestamp control Register\nTimestamp Egress asymmetric correction register\nTimestamp Egress correction nanosecond register\nTimestamp Ingress asymmetric correction register\nTimestamp Ingress correction nanosecond register\nTimestamp status register\nTx timestamp status nanoseconds register\nTx timestamp status seconds register\nVLAN Hash table register\nVLAN inclusion register\nVersion register\nVLAN tag register\nWatchdog timeout register\nMMC control register\nMMC Rx interrupt register\nMMC Rx interrupt mask register\nMMC Tx interrupt register\nMMC Tx interrupt mask register\nInterrupt status Register\nOperating mode Register\nQueue interrupt control status Register\nRx queue debug register\nRx queue missed packet and overflow counter register\nRx queue operating mode register\nTx queue debug Register\nTx queue operating mode Register\nTx queue underflow register\nRx alignment error packets register\nRx CRC error packets register\nRx LPI transition counter register\nRx LPI microsecond counter register\nRx unicast packets good register\nTx LPI transition counter register\nTx LPI microsecond timer register\nTx multiple collision good packets register\nTx packet count good register\nTx single collision good packets register\nAddress-Aligned Beats\nAutomatic Pad or CRC Stripping\nAddress width\nMAC Address0[47:32]\nMAC Address 1/2/3 [47:32]\nMAC Address 0 [31:0]\nMAC Address 1/2/3 [31:0]\nAdd or Subtract Time\nIEEE 1588 High Word Register Enable\nAddress Enable\nAddress Enable\nAbnormal Interrupt Summary Enable\nAbnormal Interrupt Summary\nAutomatic PTP Pdelay_Req message Enable\nAutomatic PTP Pdelay_Req message Trigger\nARP Offload Enable\nARP Protocol Address\nAutomatic PTP SYNC message Enable\nAutomatic PTP SYNC message Trigger\nAuxiliary Snapshot 0-3 Enable\nAuxiliary Snapshot FIFO Clear\nNumber of Auxiliary Timestamp Snapshots\nAuxiliary Timestamp Snapshot Trigger Missed\nAuxiliary Timestamp Snapshot Trigger Identifier\nNumber of Auxiliary Snapshot Inputs\nAuxiliary Timestamp\nAuxiliary Timestamp\nAuxiliary Timestamp Trigger Snapshot\nAV Feature Enable\nAHB Master Write Channel\nBack-Off Limit\nBack to Back transactions\nClause 45 PHY Enable\nContext Descriptor Error\nContext Descriptor Error Enable\nCounters Reset\nMMC Counter Freeze\nCounters Preset\nCounters Preset\nFull-Half Preset\nCounters Reset\nCounter Stop Rollover\nCSR Clock Range\nEnable checksum correction during OST for PTP over …\nCRC stripping for Type packets\nC-VLAN or S-VLAN\nC-VLAN or S-VLAN\nApplication Receive Buffer Address Pointer\nApplication Receive Descriptor Address Pointer\nApplication Transmit Buffer Address Pointer\nApplication Transmit Descriptor Address Pointer\nDMA Tx or Rx Arbitration Scheme\nDA Inverse Filtering\nDisable Broadcast Packets\nDMA Debug Registers Enable\nDeferral Check\nDMA Channel Interrupt Status\nDCB Feature Enable\nDisable CRC Checking for Received Packets\nDisable Carrier Sense During Transmission\nDisable Dropping of TCP/IP Checksum Error Packets\nDuplex Mode\nDomain Number\nDrop Non-TCP/UDP over IP Packets\nDisable Receive Own\nDisable VLAN Type Check\nDisable Retry\nDisable PTO Delay Request/Response response generation\nDelay_Req to SYNC Ratio\nDescriptor Skip Length\nDrop Transmit Status\nDisable Zero-Quanta Pause\nEnable Carrier Sense Before Transmission in Full-Duplex …\nEnable Double VLAN Processing\nEnable Hardware Flow Control\nExtended Inter-Packet Gap\nExtended Inter-Packet Gap Enable\nEnable Inner VLAN Tag in Rx Status\nEnable Inner VLAN Tag Stripping on Receive\nEarly Receive Interrupt\nEarly Receive Interrupt Enable\nEnable Inner VLAN Tag\nEnable Receive S-VLAN Match\nEnable S-VLAN\nEarly Transmit Interrupt\nEarly Transmit Interrupt Enable\nEnable 12-Bit VLAN Tag Comparison\nEnable VLAN Tag in Rx status\nEnable VLAN Tag Stripping on Receive\nExcessive Collisions\nExcessive Deferral\nFixed Burst Length\nFatal Bus Error\nFatal Bus Error Enable\nFlow Control Busy or Backpressure Activate\nForward Error Packets\nMAC Speed\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nFlush Transmit Queue\nForward Undersized Good Packets\nGlobal Unicast\nMII Operation Command\nGiant Packet Size Limit\nGiant Packet Size Limit Control Enable\nHash Table Size\nHash Multicast\nHash or Perfect Filter\nMAC Hash Table 32 Bits\nHash Unicast\nInterrupt Mode\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nChecksum Offload\nLayer 3 and Layer 4 Filter Enable\nInter-Packet Gap\nJabber Disable\nJumbo Packet Enable\nLayer 3 Address 0 Field\nLayer 3 Address 0 Field\nLayer 3 Address 1 Field\nLayer 3 Address 1 Field\nLayer 3 Address 2 Field\nLayer 3 Address 2 Field\nLayer 3 Address 3 Field\nLayer 3 Address 3 Field\nLayer 3 IP DA Inverse Match Enable\nLayer 3 IP DA Inverse Match Enable\nLayer 3 IP DA Match Enable\nLayer 3 IP DA Match Enable\nLayer 3 IP DA Higher Bits Match\nLayer 3 IP DA Higher Bits Match\nLayer 3 IP SA Higher Bits Match\nLayer 3 IP SA Higher Bits Match\nTotal number of L3 or L4 Filters\nLayer 3 Protocol Enable\nLayer 3 Protocol Enable\nLayer 3 IP SA Inverse Match Enable\nLayer 3 IP SA Inverse Match Enable\nLayer 3 IP SA Match Enable\nLayer 3 IP SA Match Enable\nLayer 4 Destination Port Number Field\nLayer 4 Destination Port Number Field\nLayer 4 Destination Port Inverse Match Enable\nLayer 4 Destination Port Inverse Match Enable\nLayer 4 Destination Port Match Enable\nLayer 4 Destination Port Match Enable\nLayer 4 Protocol Enable\nLayer 4 Protocol Enable\nLayer 4 Source Port Number Field\nLayer 4 Source Port Number Field\nLayer 4 Source Port Inverse Match Enable\nLayer 4 Source Port Inverse Match Enable\nLayer 4 Source Port Match Enable\nLayer 4 Source Port Match Enable\nLoss of Carrier\nLate Collision\nLoopback Mode\nLog Min Pdelay_Req Interval\nLPI Enable\nLPI Entry Timer\nLPI Interrupt Enable\nLPI Interrupt Status\nLPI Timer Enable\nLPI Tx Automate\nLog Sync Interval\nLPI LS Timer\nMAC Interrupt Status\nRemote wakeup packet filter\nMixed Burst\nMII Busy\nMask Byte Control\nMII Data\nDropped Packet Counters\nOverflow status of the MFC Counter\nMagic Packet Enable\nMagic Packet Received\nMissed Packet Counter Overflow Bit\nMissed Packet Counter\nMMC Interrupt Status\nMMC Receive Interrupt Status\nMMC Transmit Interrupt Status\nMaximum Segment Size\nMTL Interrupt Status\nNo Carrier\nNormal Interrupt Summary Enable\nNormal Interrupt Summary\nNumber of Training Clocks\nOperate on Second Packet\nOne-Step Timestamp Egress Asymmetry Correction\nOne-Step Timestamping Enable\nOne-Step Timestamp Ingress Asymmetry Correction\nOverflow Counter Overflow Bit\nOverflow Packet Counter\nPhysical Layer Address\n8xPBL mode\nPass Control Packets\nPHY Interrupt Enable\nPHY Interrupt\nPHY Link Status\nPHY Link Status Enable\nPause Low Threshold\nPass All Multicast\nPMT Interrupt Enable\nPMT Interrupt Status\nFlexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS …\nFlexible PPS Output Mode Enable\nPPS Output Signal Interval\nNumber of PPS Outputs\nPPS Output Signal Width\nPriority ratio\nPromiscuous Mode\nPreamble Length for Transmit Packets\nNumber of Packets in Receive Queue\nPreamble Suppression Enable\nPause Time\nPTP Offload Enable\nPTP Offload Enable\nNumber of Packets in the Transmit Queue\nProgrammable Watchdog Enable\nPower Down\nQueue interrupt status\nRegister Address\nReceive All\nRebuild INCRx Burst\nReceive Buffer size\nReceive Buffer Unavailable\nReceive Buffer Unavailable Enable\nRegister/Device Address\nStart of Receive List\nReceive Descriptor Ring Length\nReceive Descriptor Tail Pointer\nReceiver Enable\nRx DMA Error Bits\nThreshold for Activating Flow Control (in half-duplex and …\nMAC Receive Packet Controller FIFO Status\nThreshold for Deactivating Flow Control (in half-duplex …\nReceive Flow Control Enable\nReceive Interrupt\nReceive Interrupt Enable\nReceive LPI Entry\nReceive LPI Exit\nReceive LPI State\nMAC MII Receive Protocol Engine Status\nDMA Rx Channel Packet Flush\nReceive Process Stopped\nDMA Channel Receive Process State\nReceive Queue Size\nMTL Rx Queue Read Controller State\nReceive Stopped Enable\nReceive Queue Store and Forward\nReset on Read\nReceive Queue Threshold Control\nMTL Rx Queue Write Controller Active Status\nRemote wakeup Packet Filter Register Pointer Reset\nRemote wakeup Packet Forwarding Enable\nRemote wakeup Packet Enable\nRemote wakeup Packet Received\nRemote wakeup FIFO Pointer\nReceive Interrupt Watchdog Timer Count\nReceive Watchdog Timeout\nReceive Watchdog Timeout\nReceive Watchdog Timeout Enable\nMMC Receive Alignment Error Packet Counter Interrupt Mask\nMMC Receive Alignment Error Packet Counter Interrupt Status\nRx Alignment Error Packets\nNumber of DMA Receive Channels\nMMC Receive CRC Error Packet Counter Interrupt Mask\nMMC Receive CRC Error Packet Counter Interrupt Status\nRx CRC Error Packets\nMTL Receive FIFO Size\nRx LPI Transition counter\nMMC Receive LPI transition counter interrupt Mask\nMMC Receive LPI transition counter interrupt status\nRx LPI Microseconds Counter\nMMC Receive LPI microsecond counter interrupt Mask\nMMC Receive LPI microsecond counter interrupt status\nReceive Queue Overflow Interrupt Enable\nReceive Queue Overflow Interrupt Status\nRXPBL\nNumber of MTL Receive Queues\nMTL Rx Queue Fill-Level Status\nReceive Status Interrupt Enable\nReceive Status Interrupt\nRx Unicast Packets Good\nMMC Receive Unicast Good Packet Counter Interrupt Mask\nMMC Receive Unicast Good Packet Counter Interrupt Status\nIEEE 802.3as Support for 2K Packets\nSource Address\nSource Address Filter Enable\nSA Inverse Filtering\nSource Address Insertion or Replacement Control\nAddress-Aligned Beats\nAutomatic Pad or CRC Stripping\nAddress width\nMAC Address0[47:32]\nMAC Address 1/2/3 [47:32]\nMAC Address 0 [31:0]\nMAC Address 1/2/3 [31:0]\nAdd or Subtract Time\nIEEE 1588 High Word Register Enable\nAddress Enable\nAddress Enable\nAbnormal Interrupt Summary Enable\nAbnormal Interrupt Summary\nAutomatic PTP Pdelay_Req message Enable\nAutomatic PTP Pdelay_Req message Trigger\nARP Offload Enable\nARP Protocol Address\nAutomatic PTP SYNC message Enable\nAutomatic PTP SYNC message Trigger\nAuxiliary Snapshot 0-3 Enable\nAuxiliary Snapshot FIFO Clear\nNumber of Auxiliary Timestamp Snapshots\nAuxiliary Timestamp Snapshot Trigger Missed\nAuxiliary Timestamp Snapshot Trigger Identifier\nNumber of Auxiliary Snapshot Inputs\nAuxiliary Timestamp\nAuxiliary Timestamp\nAuxiliary Timestamp Trigger Snapshot\nAV Feature Enable\nAHB Master Write Channel\nBack-Off Limit\nBack to Back transactions\nClause 45 PHY Enable\nContext Descriptor Error\nContext Descriptor Error Enable\nCounters Reset\nMMC Counter Freeze\nCounters Preset\nCounters Preset\nFull-Half Preset\nCounters Reset\nCounter Stop Rollover\nCSR Clock Range\nEnable checksum correction during OST for PTP over …\nCRC stripping for Type packets\nC-VLAN or S-VLAN\nC-VLAN or S-VLAN\nApplication Receive Buffer Address Pointer\nApplication Receive Descriptor Address Pointer\nApplication Transmit Buffer Address Pointer\nApplication Transmit Descriptor Address Pointer\nDMA Tx or Rx Arbitration Scheme\nDA Inverse Filtering\nDisable Broadcast Packets\nDMA Debug Registers Enable\nDeferral Check\nDMA Channel Interrupt Status\nDCB Feature Enable\nDisable CRC Checking for Received Packets\nDisable Carrier Sense During Transmission\nDisable Dropping of TCP/IP Checksum Error Packets\nDuplex Mode\nDomain Number\nDrop Non-TCP/UDP over IP Packets\nDisable Receive Own\nDisable VLAN Type Check\nDisable Retry\nDisable PTO Delay Request/Response response generation\nDelay_Req to SYNC Ratio\nDescriptor Skip Length\nDrop Transmit Status\nDisable Zero-Quanta Pause\nEnable Carrier Sense Before Transmission in Full-Duplex …\nEnable Double VLAN Processing\nEnable Hardware Flow Control\nExtended Inter-Packet Gap\nExtended Inter-Packet Gap Enable\nEnable Inner VLAN Tag in Rx Status\nEnable Inner VLAN Tag Stripping on Receive\nEarly Receive Interrupt\nEarly Receive Interrupt Enable\nEnable Inner VLAN Tag\nEnable Receive S-VLAN Match\nEnable S-VLAN\nEarly Transmit Interrupt\nEarly Transmit Interrupt Enable\nEnable 12-Bit VLAN Tag Comparison\nEnable VLAN Tag in Rx status\nEnable VLAN Tag Stripping on Receive\nExcessive Collisions\nExcessive Deferral\nFixed Burst Length\nFatal Bus Error\nFatal Bus Error Enable\nFlow Control Busy or Backpressure Activate\nForward Error Packets\nMAC Speed\nFlush Transmit Queue\nForward Undersized Good Packets\nGlobal Unicast\nMII Operation Command\nGiant Packet Size Limit\nGiant Packet Size Limit Control Enable\nHash Table Size\nHash Multicast\nHash or Perfect Filter\nMAC Hash Table 32 Bits\nHash Unicast\nInterrupt Mode\nChecksum Offload\nLayer 3 and Layer 4 Filter Enable\nInter-Packet Gap\nJabber Disable\nJumbo Packet Enable\nLayer 3 Address 0 Field\nLayer 3 Address 0 Field\nLayer 3 Address 1 Field\nLayer 3 Address 1 Field\nLayer 3 Address 2 Field\nLayer 3 Address 2 Field\nLayer 3 Address 3 Field\nLayer 3 Address 3 Field\nLayer 3 IP DA Inverse Match Enable\nLayer 3 IP DA Inverse Match Enable\nLayer 3 IP DA Match Enable\nLayer 3 IP DA Match Enable\nLayer 3 IP DA Higher Bits Match\nLayer 3 IP DA Higher Bits Match\nLayer 3 IP SA Higher Bits Match\nLayer 3 IP SA Higher Bits Match\nTotal number of L3 or L4 Filters\nLayer 3 Protocol Enable\nLayer 3 Protocol Enable\nLayer 3 IP SA Inverse Match Enable\nLayer 3 IP SA Inverse Match Enable\nLayer 3 IP SA Match Enable\nLayer 3 IP SA Match Enable\nLayer 4 Destination Port Number Field\nLayer 4 Destination Port Number Field\nLayer 4 Destination Port Inverse Match Enable\nLayer 4 Destination Port Inverse Match Enable\nLayer 4 Destination Port Match Enable\nLayer 4 Destination Port Match Enable\nLayer 4 Protocol Enable\nLayer 4 Protocol Enable\nLayer 4 Source Port Number Field\nLayer 4 Source Port Number Field\nLayer 4 Source Port Inverse Match Enable\nLayer 4 Source Port Inverse Match Enable\nLayer 4 Source Port Match Enable\nLayer 4 Source Port Match Enable\nLoss of Carrier\nLate Collision\nLoopback Mode\nLog Min Pdelay_Req Interval\nLPI Enable\nLPI Entry Timer\nLPI Interrupt Enable\nLPI Interrupt Status\nLPI Timer Enable\nLPI Tx Automate\nLog Sync Interval\nLPI LS Timer\nMAC Interrupt Status\nRemote wakeup packet filter\nMixed Burst\nMII Busy\nMask Byte Control\nMII Data\nDropped Packet Counters\nOverflow status of the MFC Counter\nMagic Packet Enable\nMagic Packet Received\nMissed Packet Counter Overflow Bit\nMissed Packet Counter\nMMC Interrupt Status\nMMC Receive Interrupt Status\nMMC Transmit Interrupt Status\nMaximum Segment Size\nMTL Interrupt Status\nNo Carrier\nNormal Interrupt Summary Enable\nNormal Interrupt Summary\nNumber of Training Clocks\nOperate on Second Packet\nOne-Step Timestamp Egress Asymmetry Correction\nOne-Step Timestamping Enable\nOne-Step Timestamp Ingress Asymmetry Correction\nOverflow Counter Overflow Bit\nOverflow Packet Counter\nPhysical Layer Address\n8xPBL mode\nPass Control Packets\nPHY Interrupt Enable\nPHY Interrupt\nPHY Link Status\nPHY Link Status Enable\nPause Low Threshold\nPass All Multicast\nPMT Interrupt Enable\nPMT Interrupt Status\nFlexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS …\nFlexible PPS Output Mode Enable\nPPS Output Signal Interval\nNumber of PPS Outputs\nPPS Output Signal Width\nPriority ratio\nPromiscuous Mode\nPreamble Length for Transmit Packets\nNumber of Packets in Receive Queue\nPreamble Suppression Enable\nPause Time\nPTP Offload Enable\nPTP Offload Enable\nNumber of Packets in the Transmit Queue\nProgrammable Watchdog Enable\nPower Down\nQueue interrupt status\nRegister Address\nReceive All\nRebuild INCRx Burst\nReceive Buffer size\nReceive Buffer Unavailable\nReceive Buffer Unavailable Enable\nRegister/Device Address\nStart of Receive List\nReceive Descriptor Ring Length\nReceive Descriptor Tail Pointer\nReceiver Enable\nRx DMA Error Bits\nThreshold for Activating Flow Control (in half-duplex and …\nMAC Receive Packet Controller FIFO Status\nThreshold for Deactivating Flow Control (in half-duplex …\nReceive Flow Control Enable\nReceive Interrupt\nReceive Interrupt Enable\nReceive LPI Entry\nReceive LPI Exit\nReceive LPI State\nMAC MII Receive Protocol Engine Status\nDMA Rx Channel Packet Flush\nReceive Process Stopped\nDMA Channel Receive Process State\nReceive Queue Size\nMTL Rx Queue Read Controller State\nReceive Stopped Enable\nReceive Queue Store and Forward\nReset on Read\nReceive Queue Threshold Control\nMTL Rx Queue Write Controller Active Status\nRemote wakeup Packet Filter Register Pointer Reset\nRemote wakeup Packet Forwarding Enable\nRemote wakeup Packet Enable\nRemote wakeup Packet Received\nRemote wakeup FIFO Pointer\nReceive Interrupt Watchdog Timer Count\nReceive Watchdog Timeout\nReceive Watchdog Timeout\nReceive Watchdog Timeout Enable\nMMC Receive Alignment Error Packet Counter Interrupt Mask\nMMC Receive Alignment Error Packet Counter Interrupt Status\nRx Alignment Error Packets\nNumber of DMA Receive Channels\nMMC Receive CRC Error Packet Counter Interrupt Mask\nMMC Receive CRC Error Packet Counter Interrupt Status\nRx CRC Error Packets\nMTL Receive FIFO Size\nRx LPI Transition counter\nMMC Receive LPI transition counter interrupt Mask\nMMC Receive LPI transition counter interrupt status\nRx LPI Microseconds Counter\nMMC Receive LPI microsecond counter interrupt Mask\nMMC Receive LPI microsecond counter interrupt status\nReceive Queue Overflow Interrupt Enable\nReceive Queue Overflow Interrupt Status\nRXPBL\nNumber of MTL Receive Queues\nMTL Rx Queue Fill-Level Status\nReceive Status Interrupt Enable\nReceive Status Interrupt\nRx Unicast Packets Good\nMMC Receive Unicast Good Packet Counter Interrupt Mask\nMMC Receive Unicast Good Packet Counter Interrupt Status\nIEEE 802.3as Support for 2K Packets\nSource Address\nSource Address Filter Enable\nSA Inverse Filtering\nSource Address Insertion or Replacement Control\nSkip Address Packet\nSelect PTP packets for Taking Snapshots\nIP version\nSub-nanosecond Increment Value\nSlow Protocol Detection Enable\nSplit Header Feature Enable\nSource Port Identity 0\nSource Port Identity 1\nSource Port Identity 2\nStart or Stop Receive Command\nSub-second Increment Value\nStart or Stop Transmission Command\nNumber of Status Words in Tx Status FIFO of Queue\nSoftware Reset\nTransmit Buffer Unavailable\nTransmit Buffer Unavailable Enable\nStart of Transmit List\nTransmit Descriptor Ring Length\nTransmit Descriptor Tail Pointer\nTransmitter Enable\nTx DMA Error Bits\nMAC Transmit Packet Controller Status\nTransmit Flow Control Enable\nTransmit Interrupt\n1 µs tick Counter\nTransmit Interrupt Enable\nTransmit Jabber Timeout\nTransmit LPI Entry\nTransmit LPI Exit\nTransmit LPI State\nMAC MII Transmit Protocol Engine Status\nTransmit Process Stopped\nDMA Channel Transmit Process State\nTransmit Queue Size\nMTL Tx Queue Read Controller Status\nPPS Target Time Register Busy\nTarget Time Register Mode for PPS Output\nUpdate Addend Register\nTimestamp Addend Register\nFine or Coarse Timestamp Update\nTimestamp Digital or Binary Rollover Control\nTCP Segmentation Enabled\nTimestamp Egress Correction\nEnable Timestamp\nEnable Timestamp for All Packets\nEnable MAC Address for PTP Packet Filtering\nEnable Timestamp Snapshot for Event Messages\nTransmit Store and Forward\nTimestamp Ingress Correction\nTimestamp Interrupt Enable\nInitialize Timestamp\nEnable Processing of PTP over Ethernet Packets\nEnable Processing of PTP Packets Sent over IPv4-UDP\nEnable Processing of PTP Packets Sent over IPv6-UDP\nTimestamp Interrupt Status\nEnable Snapshot for Messages Relevant to Master\nTCP Segmentation Offload Enable\nTimestamp Second\nTimestamp Seconds\nTimestamp Seconds Overflow\nTimestamp Sub-seconds\nTimestamp Sub-seconds\nTimestamp Target Time Reached\nTimestamp Target Time Error\nPPS Target Time Seconds Register\nUpdate Timestamp\nEnable PTP Packet Processing for Version 2 Format\nTransmit Threshold Control\nTarget Time Low for PPS Register\nMTL Tx Queue Write Controller Status\nLPI TW Timer\nNumber of DMA Transmit Channels\nMTL Transmit FIFO Size\nMMC Transmit Good Packet Counter Interrupt Mask\nMMC Transmit Good Packet Counter Interrupt Status\nTx LPI Transition counter\nMMC Transmit LPI transition counter interrupt Mask\nMMC Transmit LPI transition counter interrupt status\nTx LPI Microseconds Counter\nMMC Transmit LPI microsecond counter interrupt Mask\nMMC Transmit LPI microsecond counter interrupt status\nMMC Transmit Multiple Collision Good Packet Counter …\nMMC Transmit Multiple Collision Good Packet Counter …\nTx Multiple Collision Good Packets\nTransmit Programmable Burst Length\nTx Packet Count Good\nTransmit priority\nNumber of MTL Transmit Queues\nTransmit Queue Enable\nTransmit Queue in Pause\nMTL Tx Queue Not Empty Status\nMMC Transmit Single Collision Good Packet Counter …\nMMC Transmit Single Collision Good Packet Counter …\nTransmit Stopped Enable\nTx Single Collision Good Packets\nMTL Tx Status FIFO Full Status\nTransmit Status Interrupt Enable\nTransmit Status Interrupt\nTransmit Timestamp Status High\nTx Timestamp Status Interrupt Status\nTransmit Timestamp Status Low\nTransmit Timestamp Status Missed\nTransmit Timestamp Status Mode\nTransmit Queue Underflow Interrupt Enable\nTransmit Queue Underflow Interrupt Status\nUpdate MMC Counters for Dropped Broadcast Packets\nOverflow Bit for Underflow Packet Counter\nUnderflow Packet Counter\nUnicast Pause Packet Detect\nST-defined version\nUnicast Slow Protocol Packet Detect\nVLAN Tag Identifier for Receive Packets\nVLAN Tag Control in Transmit Packets\nVLAN Tag Control in Transmit Packets\nVLAN Hash Table\nVLAN Priority Control\nVLAN Priority Control\nVLAN Tag for Transmit Packets\nVLAN Tag for Transmit Packets\nVLAN Tag Input\nVLAN Tag Input\nVLAN Tag Filter Enable\nVLAN Tag Hash Table Match Enable\nVLAN Tag Inverse Match Enable\nWatchdog Disable\nWatchdog Timeout\nSkip Address Packet\nSelect PTP packets for Taking Snapshots\nIP version\nSub-nanosecond Increment Value\nSlow Protocol Detection Enable\nSplit Header Feature Enable\nSource Port Identity 0\nSource Port Identity 1\nSource Port Identity 2\nStart or Stop Receive Command\nSub-second Increment Value\nStart or Stop Transmission Command\nNumber of Status Words in Tx Status FIFO of Queue\nSoftware Reset\nTransmit Buffer Unavailable\nTransmit Buffer Unavailable Enable\nStart of Transmit List\nTransmit Descriptor Ring Length\nTransmit Descriptor Tail Pointer\nTransmitter Enable\nTx DMA Error Bits\nMAC Transmit Packet Controller Status\nTransmit Flow Control Enable\nTransmit Interrupt\n1 µs tick Counter\nTransmit Interrupt Enable\nTransmit Jabber Timeout\nTransmit LPI Entry\nTransmit LPI Exit\nTransmit LPI State\nMAC MII Transmit Protocol Engine Status\nTransmit Process Stopped\nDMA Channel Transmit Process State\nTransmit Queue Size\nMTL Tx Queue Read Controller Status\nPPS Target Time Register Busy\nTarget Time Register Mode for PPS Output\nUpdate Addend Register\nTimestamp Addend Register\nFine or Coarse Timestamp Update\nTimestamp Digital or Binary Rollover Control\nTCP Segmentation Enabled\nTimestamp Egress Correction\nEnable Timestamp\nEnable Timestamp for All Packets\nEnable MAC Address for PTP Packet Filtering\nEnable Timestamp Snapshot for Event Messages\nTransmit Store and Forward\nTimestamp Ingress Correction\nTimestamp Interrupt Enable\nInitialize Timestamp\nEnable Processing of PTP over Ethernet Packets\nEnable Processing of PTP Packets Sent over IPv4-UDP\nEnable Processing of PTP Packets Sent over IPv6-UDP\nTimestamp Interrupt Status\nEnable Snapshot for Messages Relevant to Master\nTCP Segmentation Offload Enable\nTimestamp Second\nTimestamp Seconds\nTimestamp Seconds Overflow\nTimestamp Sub-seconds\nTimestamp Sub-seconds\nTimestamp Target Time Reached\nTimestamp Target Time Error\nPPS Target Time Seconds Register\nUpdate Timestamp\nEnable PTP Packet Processing for Version 2 Format\nTransmit Threshold Control\nTarget Time Low for PPS Register\nMTL Tx Queue Write Controller Status\nLPI TW Timer\nNumber of DMA Transmit Channels\nMTL Transmit FIFO Size\nMMC Transmit Good Packet Counter Interrupt Mask\nMMC Transmit Good Packet Counter Interrupt Status\nTx LPI Transition counter\nMMC Transmit LPI transition counter interrupt Mask\nMMC Transmit LPI transition counter interrupt status\nTx LPI Microseconds Counter\nMMC Transmit LPI microsecond counter interrupt Mask\nMMC Transmit LPI microsecond counter interrupt status\nMMC Transmit Multiple Collision Good Packet Counter …\nMMC Transmit Multiple Collision Good Packet Counter …\nTx Multiple Collision Good Packets\nTransmit Programmable Burst Length\nTx Packet Count Good\nTransmit priority\nNumber of MTL Transmit Queues\nTransmit Queue Enable\nTransmit Queue in Pause\nMTL Tx Queue Not Empty Status\nMMC Transmit Single Collision Good Packet Counter …\nMMC Transmit Single Collision Good Packet Counter …\nTransmit Stopped Enable\nTx Single Collision Good Packets\nMTL Tx Status FIFO Full Status\nTransmit Status Interrupt Enable\nTransmit Status Interrupt\nTransmit Timestamp Status High\nTx Timestamp Status Interrupt Status\nTransmit Timestamp Status Low\nTransmit Timestamp Status Missed\nTransmit Timestamp Status Mode\nTransmit Queue Underflow Interrupt Enable\nTransmit Queue Underflow Interrupt Status\nUpdate MMC Counters for Dropped Broadcast Packets\nOverflow Bit for Underflow Packet Counter\nUnderflow Packet Counter\nUnicast Pause Packet Detect\nST-defined version\nUnicast Slow Protocol Packet Detect\nVLAN Tag Identifier for Receive Packets\nVLAN Tag Control in Transmit Packets\nVLAN Tag Control in Transmit Packets\nVLAN Hash Table\nVLAN Priority Control\nVLAN Priority Control\nVLAN Tag for Transmit Packets\nVLAN Tag for Transmit Packets\nVLAN Tag Input\nVLAN Tag Input\nVLAN Tag Filter Enable\nVLAN Tag Hash Table Match Enable\nVLAN Tag Inverse Match Enable\nWatchdog Disable\nWatchdog Timeout\nExternal interrupt/event controller\nEvent mask register\nReturns the argument unchanged.\nFalling Trigger selection register\nInterrupt mask register\nCalls <code>U::from(self)</code>.\nPending register\nRising Trigger selection register\nSoftware interrupt event register\nEXTI lines register, 1 bit per line\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nEXTI line\nEXTI line\nFDCAN Message RAM\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nFDCAN Message RAM\nCluster BANK%s, containing KEYR?, CR?, SR?, CCR?, …\nFlash\nAccess control register\nCluster BANK%s, containing KEYR?, CR?, SR?, CCR?, …\nFLASH register with boot address\nFLASH register with boot address\nFLASH clear control register for bank 1\nFLASH control register for bank 1\nFLASH CRC control register for bank 1\nFLASH CRC data register\nFLASH CRC end address register for bank 1\nFLASH CRC start address register for bank 1\nFLASH ECC fail address for bank 1\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nFLASH key register for bank 1\nFLASH option clear control register\nFLASH option control register\nFLASH option key register\nFLASH option status register\nFLASH option status register\nFLASH protection address for bank 1\nFLASH protection address for bank 1\nFLASH secure address for bank 1\nFLASH secure address for bank 1\nFLASH status register for bank 1\nFLASH write sector protection for bank 1\nFLASH write sector protection for bank 1\nAccess control register\nFLASH register with boot address\nFLASH register with boot address\nFLASH clear control register for bank 1\nFLASH control register for bank 1\nFLASH CRC control register for bank 1\nFLASH CRC data register\nFLASH CRC end address register for bank 1\nFLASH CRC start address register for bank 1\nFLASH ECC fail address for bank 1\nFLASH option clear control register\nFLASH option control register\nFLASH option status register\nFLASH option status register\nFLASH protection address for bank 1\nFLASH protection address for bank 1\nFLASH secure address for bank 1\nFLASH secure address for bank 1\nFLASH status register for bank 1\nFLASH write sector protection for bank 1\nFLASH write sector protection for bank 1\nBank 1 CRC sector select bit\nBank 1 CRC select bit\nBank 1 erase request\nBoot address 0\nBoot address 0\nBoot address 1\nBoot address 1\nBrownout level option status bit\nBOR reset level option configuration bits\nBank 1 ongoing program flag\nBank 1 CRC clear bit\nBank 1 CRC sector list clear bit\nBank 1 CRCEND1 flag clear bit\nBank 1 CRC read error clear bit\nBank 1 DBECCERR1 flag clear bit\nBank 1 EOP1 flag clear bit\nBank 1 INCERR1 flag clear bit\nBank 1 OPERR1 flag clear bit\nOPTCHANGEERR reset bit\nBank 1 PGSERR1 flag clear bi\nBank 1 RDPERR1 flag clear bit\nBank 1 RDSERR1 flag clear bit\nBank 1 SNECCERR1 flag clear bit\nBank 1 STRBERR1 flag clear bit\nBank 1 WRPERR1 flag clear bit\nBank 1 CRC burst size\nBank 1 CRC busy flag\nBank 1 CRC sector mode select bit\nCRC result\nBank 1 CRC control bit\nCRC end address on bank 1\nBank 1 CRC sector number\nCRC start address on bank 1\nBank 1 CRC-complete flag\nBank 1 end of CRC calculation interrupt enable bit\nBank 1 CRC read error flag\nBank 1 CRC read error interrupt enable bit\nBank 1 ECC double detection error flag\nBank 1 ECC double detection error interrupt enable bit\nBank 1 PCROP protected erase enable option status bit\nBank 1 PCROP protected erase enable option configuration …\nBank 1 secure protected erase enable option status bit\nBank 1 secure protected erase enable option configuration …\nBank 1 end-of-program flag\nBank 1 end-of-program interrupt control bit\nBank 1 ECC error address\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\nBank 1 write forcing control bit\nIWDG Standby mode freeze option status bit\nIWDG Standby mode freeze option configuration bit\nIWDG Stop mode freeze option status bit\nIWDG Stop mode freeze option configuration bit\nBank 1 inconsistency error flag\nBank 1 inconsistency error interrupt enable bit\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nI/O high-speed at low-voltage status bit …\nI/O high-speed at low-voltage (PRODUCT_BELOW_25V)\nIWDG1 control option status bit\nIWDG1 option configuration bit\nRead latency\nBank 1 configuration lock bit\nFlash mass erase enable bit\nD1 DStandby entry reset option status bit\nOption byte erase after D1 DStandby option configuration …\nD1 DStop entry reset option status bit\nOption byte erase after D1 DStop option configuration bit\nBank 1 write/erase error flag\nBank 1 write/erase error interrupt enable bit\nOption byte change ongoing flag\nOption byte change error flag\nOption byte change error interrupt enable bit\nFLASH_OPTCR lock option configuration bit\nOption byte start change option configuration bit\nDevice personalization status bit\nBank 1 program enable bit\nBank 1 programming sequence error flag\nBank 1 programming sequence error interrupt enable bit\nBank 1 highest PCROP protected address\nBank 1 highest PCROP protected address configuration\nBank 1 lowest PCROP protected address\nBank 1 lowest PCROP protected address configuration\nBank 1 program size\nBank 1 wait queue flag\nReadout protection level option status byte\nReadout protection level option configuration byte\nBank 1 read protection error flag\nBank 1 read protection error interrupt enable bit\nBank 1 secure error flag\nBank 1 secure error interrupt enable bit\nUser option bit 1\nUser option configuration bit 1\nUser option configuration bit 2\nBank 1 highest secure protected address\nBank 1 highest secure protected address configuration\nBank 1 lowest secure protected address\nBank 1 lowest secure protected address configuration\nSecurity enable option status bit\nSecurity option configuration bit\nBank 1 sector erase request\nBank 1 CRC sector select bit\nBank 1 CRC select bit\nBank 1 erase request\nBoot address 0\nBoot address 0\nBoot address 1\nBoot address 1\nBrownout level option status bit\nBOR reset level option configuration bits\nBank 1 ongoing program flag\nBank 1 CRC clear bit\nBank 1 CRC sector list clear bit\nBank 1 CRCEND1 flag clear bit\nBank 1 CRC read error clear bit\nBank 1 DBECCERR1 flag clear bit\nBank 1 EOP1 flag clear bit\nBank 1 INCERR1 flag clear bit\nBank 1 OPERR1 flag clear bit\nOPTCHANGEERR reset bit\nBank 1 PGSERR1 flag clear bi\nBank 1 RDPERR1 flag clear bit\nBank 1 RDSERR1 flag clear bit\nBank 1 SNECCERR1 flag clear bit\nBank 1 STRBERR1 flag clear bit\nBank 1 WRPERR1 flag clear bit\nBank 1 CRC burst size\nBank 1 CRC busy flag\nBank 1 CRC sector mode select bit\nCRC result\nBank 1 CRC control bit\nCRC end address on bank 1\nBank 1 CRC sector number\nCRC start address on bank 1\nBank 1 CRC-complete flag\nBank 1 end of CRC calculation interrupt enable bit\nBank 1 CRC read error flag\nBank 1 CRC read error interrupt enable bit\nBank 1 ECC double detection error flag\nBank 1 ECC double detection error interrupt enable bit\nBank 1 PCROP protected erase enable option status bit\nBank 1 PCROP protected erase enable option configuration …\nBank 1 secure protected erase enable option status bit\nBank 1 secure protected erase enable option configuration …\nBank 1 end-of-program flag\nBank 1 end-of-program interrupt control bit\nBank 1 ECC error address\nBank 1 write forcing control bit\nIWDG Standby mode freeze option status bit\nIWDG Standby mode freeze option configuration bit\nIWDG Stop mode freeze option status bit\nIWDG Stop mode freeze option configuration bit")