searchState.loadedDescShard("imxrt_ral", 2, "Returns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nARM CM7 platform AHB clock enable\nExclusive monitor response select of illegal command\nGlobal Interrupt\nSAI1 MCLK1 source select\nSAI1 MCLK2 source select\nSAI1 MCLK3 source select\nsai1.MCLK signal direction control\nSAI3 MCLK3 source select\nsai3.MCLK signal direction control\nARM invasive debug enable\nDCP Key selection bit.\nLock DBG_EN field for changes\nLock DCP Key OCOTP/Key MUX selection bit\nLock NIDEN field for changes\nLock OCRAM_TZ_ADDR field for changes\nLock OCRAM_TZ_EN field for changes\nLock SEC_ERR_RESP field for changes\nARM non-secure (non-invasive) debug enable\nOCRAM TrustZone (TZ) start address\nOCRAM TrustZone (TZ) enable.\nSecurity error response enable for all security gaskets …\nDebug turned off.\nDebug enabled (default).\nSelect key from SNVS Master Key.\nSelect key from OCOTP (SW_GP2).\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nField is not locked\nField is locked (read access only)\nDebug turned off.\nDebug enabled (default).\nThe TrustZone feature is disabled. Entire OCRAM space is …\nThe TrustZone feature is enabled. Access to address in the …\nOKEY response\nSLVError (default)\nLock M7_APC_AC_R0_CTRL field for changes\nLock M7_APC_AC_R1_CTRL field for changes\nLock M7_APC_AC_R2_CTRL field for changes\nLock M7_APC_AC_R3_CTRL field for changes\nAccess control of memory region-0\nAccess control of memory region-1\nAccess control of memory region-2\nAccess control of memory region-3\nNo access protection\nM7 debug protection enabled\nNo access protection\nM7 debug protection enabled\nNo access protection\nM7 debug protection enabled\nNo access protection\nM7 debug protection enabled\nFLEXIO1 ipg_doze mode\nFlexIO1 stop mode selection. Cannot change when ipg_stop …\nFLEXIO1 is not in doze mode\nFLEXIO1 is in doze mode\nFlexIO1 is functional in Stop mode.\nWhen this bit is equal to 1’b1 and ipg_stop is asserted, …\nUSB block cacheable attribute value of AXI transactions\nCacheable attribute is off for read/write transactions.\nCacheable attribute is on for read/write transactions.\nDTCM total size configuration\nITCM total size configuration\n0 KB (No DTCM)\n4 KB\n8 KB\n16 KB\n32 KB\n64 KB\n128 KB\n0 KB (No ITCM)\n4 KB\n8 KB\n16 KB\n32 KB\n64 KB\n128 KB\nVector table offset register out of reset\nFlexRAM bank config source select\nDTCM enable initialization out of reset\nITCM enable initialization out of reset\nLock CM7_INIT_VTOR field for changes\nuse fuse value to config\nuse FLEXRAM_BANK_CFG to config\nDTCM is disabled\nDTCM is enabled\nITCM is disabled\nITCM is enabled\nCM7_INIT_VTOR field is not locked.\nCM7_INIT_VTOR field is locked (read access only).\nFlexRAM bank config value\nlock M7_APC_AC_R0_BOT field for changes\nAPC end address of memory region-0\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nlock M7_APC_AC_R0_TOP field for changes\nAPC start address of memory region-0\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nAHB clock is not running (gated) when CM7 is sleeping and …\nAHB clock is running (enabled) when CM7 is sleeping and …\nOKAY response\nSLVError response\nGlobal interrupt request is not asserted.\nGlobal interrupt request is asserted.\nccm.ssi1_clk_root\nccm.ssi3_clk_root\niomux.sai1_ipg_clk_sai_mclk\niomux.sai3_ipg_clk_sai_mclk\nccm.ssi1_clk_root\nccm.ssi3_clk_root\niomux.sai1_ipg_clk_sai_mclk\niomux.sai3_ipg_clk_sai_mclk\nccm.spdif0_clk_root\nSPDIF_EXT_CLK\nspdif.spdif_srclk\nspdif.spdif_outclock\nsai1.MCLK is input signal\nsai1.MCLK is output signal\nccm.spdif0_clk_root\nSPDIF_EXT_CLK\nspdif.spdif_srclk\nspdif.spdif_outclock\nsai3.MCLK is input signal\nsai3.MCLK is output signal\nForce Round Robin in AXBS_P. This bit can override master …\nAXBS_P M0 master has higher priority.Do not set both M1 …\nAXBS_P M1 master has higher priority.Do not set both M1 …\nThis bit controls how memory (OCRAM) enters Deep Sleep …\nEnable power saving features on L2 memory\nDivider ratio control for mclk from hmclk\nMQS enable.\nMedium Quality Sound (MQS) Oversample\nMQS software reset\nAutomatically gate off RAM clock when RAM is not accessed.\nlock M7_APC_AC_R1_BOT field for changes\nAPC end address of memory region-1\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nlock M7_APC_AC_R1_TOP field for changes\nAPC start address of memory region-1\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nlock M7_APC_AC_R2_BOT field for changes\nAPC end address of memory region-2\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nlock M7_APC_AC_R2_TOP field for changes\nAPC start address of memory region-2\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nlock M7_APC_AC_R3_BOT field for changes\nAPC end address of memory region-3\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nlock M7_APC_AC_R3_TOP field for changes\nAPC start address of memory region-3\nRegister field [31:1] is not locked\nRegister field [31:1] is locked (read access only)\nSelect GPIO1 or GPIO2\nStart address of flexspi1\nEnd address of flexspi1\nOffset address of flexspi1\nAXBS_P masters are not arbitored in round robin, depending …\nAXBS_P masters are arbitored in round robin\nAXBS_P M0 master doesn’t have high priority\nAXBS_P M0 master has high priority\nAXBS_P M1 master does not have high priority\nAXBS_P M1 master has high priority\nNo force sleep control supported, memory deep sleep mode …\nForce memory into deep sleep mode (OCRAM in power saving …\nEnters power saving mode only when chip is in SUSPEND mode\nControlled by L2_MEM_DEEPSLEEP bitfield\nmclk frequency = hmclk frequency\nmclk frequency = 1/2 * hmclk frequency\nmclk frequency = 1/3 * hmclk frequency\nmclk frequency = 1/256 * hmclk frequency\nDisable MQS\nEnable MQS\n32\n64\nExit software reset for MQS\nEnable software reset for MQS\ndisable automatically gate off RAM clock\nenable automatically gate off RAM clock\nSelect 128-bit DCP key from 256-bit key from SNVS Master …\nSelect [127:0] from SNVS Master Key as DCP key\nSelect [255:128] from SNVS Master Key as DCP key\nEDMA stop acknowledge. This is a status (read-only) bit\nEDMA stop request.\nFLEXIO1 stop acknowledge\nFlexIO1 stop request.\nFLEXSPI stop acknowledge\nFlexSPI stop request.\nPIT stop acknowledge\nPIT stop request.\nSAI1 stop acknowledge\nSAI1 stop request.\nSAI3 stop acknowledge\nSAI3 stop request.\nTRNG stop acknowledge\nTRNG stop request.\nEDMA stop acknowledge is not asserted\nEDMA stop acknowledge is asserted (EDMA is in STOP mode).\nstop request off\nstop request on\nFLEXIO1 stop acknowledge is not asserted\nFLEXIO1 stop acknowledge is asserted\nstop request off\nstop request on\nFLEXSPI stop acknowledge is not asserted\nFLEXSPI stop acknowledge is asserted\nstop request off\nstop request on\nPIT stop acknowledge is not asserted\nPIT stop acknowledge is asserted\nstop request off\nstop request on\nSAI1 stop acknowledge is not asserted\nSAI1 stop acknowledge is asserted\nstop request off\nstop request on\nSAI3 stop acknowledge is not asserted\nSAI3 stop acknowledge is asserted\nstop request off\nstop request on\nTRNG stop acknowledge is not asserted\nTRNG stop acknowledge is asserted\nstop request off\nstop request on\nGPT1 1 MHz clock source select\nGPT2 1 MHz clock source select\nWDOG1 Timeout Mask\nWDOG2 Timeout Mask\nGPT1 ipg_clk_highfreq driven by IPG_PERCLK\nGPT1 ipg_clk_highfreq driven by anatop 1 MHz clock\nGPT2 ipg_clk_highfreq driven by IPG_PERCLK\nGPT2 ipg_clk_highfreq driven by anatop 1 MHz clock\nWDOG1 Timeout behaves normally\nWDOG1 Timeout is masked\nWDOG2 Timeout behaves normally\nWDOG2 Timeout is masked\nIOMUXC XBAR_INOUT2 function direction select\nIOMUXC XBAR_INOUT3 function direction select\nXBAR_INOUT as input\nXBAR_INOUT as output\nXBAR_INOUT as input\nXBAR_INOUT as output\nLPI2C1 stop acknowledge\nLPI2C1 stop request\nLPI2C2 stop acknowledge\nLPI2C2 stop request\nLPSPI1 stop acknowledge\nLPSPI1 stop request\nLPSPI2 stop acknowledge\nLPSPI2 stop request\nLPUART1 stop acknowledge\nLPUART1 stop request\nLPUART1 stop acknowledge\nLPUART1 stop request\nLPUART3 stop acknowledge\nLPUART3 stop request\nLPUART4 stop acknowledge\nLPUART4 stop request\nstop acknowledge is not asserted\nstop acknowledge is asserted (the module is in Stop mode)\nstop request off\nstop request on\nstop acknowledge is not asserted\nstop acknowledge is asserted\nstop request off\nstop request on\nstop acknowledge is not asserted\nstop acknowledge is asserted\nstop request off\nstop request on\nstop acknowledge is not asserted\nstop acknowledge is asserted\nstop request off\nstop request on\nstop acknowledge is not asserted\nstop acknowledge is asserted\nstop request off\nstop request on\nstop acknowledge is not asserted\nstop acknowledge is asserted\nstop request off\nstop request on\nstop acknowledge is not asserted\nstop acknowledge is asserted\nstop request off\nstop request on\nstop acknowledge is not asserted\nstop acknowledge is asserted\nstop request off\nstop request on\nLPI2C1 ipg_doze mode\nLPI2C1 stop mode selection, cannot change when ipg_stop is …\nLPI2C2 ipg_doze mode\nLPI2C2 stop mode selection, cannot change when ipg_stop is …\nLPSPI1 ipg_doze mode\nLPSPI1 stop mode selection, cannot change when ipg_stop is …\nLPSPI2 ipg_doze mode\nLPSPI2 stop mode selection, cannot change when ipg_stop is …\nLPUART1 ipg_doze mode\nLPUART1 stop mode selection, cannot change when ipg_stop …\nLPUART2 ipg_doze mode\nLPUART2 stop mode selection, cannot change when ipg_stop …\nLPUART3 ipg_doze mode\nLPUART3 stop mode selection, cannot change when ipg_stop …\nLPUART4 ipg_doze mode\nLPUART4 stop mode selection, cannot change when ipg_stop …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nnot in doze mode\nin doze mode\nthe module is functional in Stop mode\nthe module is NOT functional in Stop mode, when this bit …\nIOMUXC_SNVS\nIOMUXC_SNVS\nSW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register\nSW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register\nSW_PAD_CTL_PAD_ONOFF SW PAD Control Register\nSW_PAD_CTL_PAD_ONOFF SW PAD Control Register\nSW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register\nSW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register\nSW_PAD_CTL_PAD_POR_B SW PAD Control Register\nSW_PAD_CTL_PAD_POR_B SW PAD Control Register\nSW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register\nSW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nMUX Mode Select Field.\nSoftware Input On Field.\nSelect mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of …\nSelect mux mode: ALT5 mux port: GPIO5_IO00 of instance: …\nInput Path is determined by functionality\nForce input path of pad PMIC_ON_REQ\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nmedium(100MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nmedium(100MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nmedium(100MHz)\nSlow Slew Rate\nFast Slew Rate\nDrive Strength Field\nHyst. Enable Field\nOpen Drain Enable Field\nPull / Keep Enable Field\nPull / Keep Select Field\nPull Up / Down Config. Field\nSpeed Field\nSlew Rate Field\noutput driver disabled;\nR0(150 Ohm @ 3.3V, 260 Ohm@1.8V)\nR0/2\nR0/3\nR0/4\nR0/5\nR0/6\nR0/7\nHysteresis Disabled\nHysteresis Enabled\nOpen Drain Disabled\nOpen Drain Enabled\nPull/Keeper Disabled\nPull/Keeper Enabled\nKeeper\nPull\n100K Ohm Pull Down\n47K Ohm Pull Up\n100K Ohm Pull Up\n22K Ohm Pull Up\nmedium(100MHz)\nSlow Slew Rate\nFast Slew Rate\nGPR0 General Purpose Register\nGPR1 General Purpose Register\nGPR2 General Purpose Register\nGPR3 General Purpose Register\nGPR3 General Purpose Register\nIOMUXC\nIOMUXC\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDCDC_IN low voltage detect.\nDCDC output over current alert\nDCDC output over voltage alert\nDCDC captured status clear\nDCDC status OK\nSet to enable LPSR mode.\nPOR_B pad control\nKeypad Data Direction Register\nKeypad Data Direction Register\nKeypad Control Register\nKeypad Control Register\nKeypad Data Register\nKeypad Data Register\nKPP Registers\nKeypad Status Register\nKeypad Status Register\nKPP Registers\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nKeypad Column Data Direction Register\nKeypad Row Data Direction\nCOLn pin is configured as an input.\nCOLn pin is configured as an output.\nROWn pin configured as an input.\nROWn pin configured as an output.\nKeypad Column Strobe Open-Drain Enable\nKeypad Row Enable\nColumn strobe output is open drain.\nColumn strobe output is totem pole drive.\nRow is not included in the keypad key press detect.\nRow is included in the keypad key press detect.\nKeypad Column Data\nKeypad Row Data\nKeypad Key Depress Interrupt Enable\nKey Depress Synchronizer Clear\nKeypad Key Depress\nKeypad Key Release\nKeypad Release Interrupt Enable\nKey Release Synchronizer Set\nNo interrupt request is generated when KPKD is set.\nAn interrupt request is generated when KPKD is set.\nNo effect\nSet bits that clear the keypad depress synchronizer chain\nNo key presses detected\nA key has been depressed\nNo key release detected\nAll keys have been released\nNo interrupt request is generated when KPKR is set.\nAn interrupt request is generated when KPKR is set.\nNo effect\nSet bits which sets keypad release synchronizer chain\nLPI2C\nLPI2C\nMaster Clock Configuration Register 0\nMaster Clock Configuration Register 0\nMaster Clock Configuration Register 1\nMaster Clock Configuration Register 1\nMaster Configuration Register 0\nMaster Configuration Register 0\nMaster Configuration Register 1\nMaster Configuration Register 1\nMaster Configuration Register 2\nMaster Configuration Register 2\nMaster Configuration Register 3\nMaster Configuration Register 3\nMaster Control Register\nMaster Control Register\nMaster DMA Enable Register\nMaster DMA Enable Register\nMaster Data Match Register\nMaster Data Match Register\nMaster FIFO Control Register\nMaster FIFO Control Register\nMaster FIFO Status Register\nMaster FIFO Status Register\nMaster Interrupt Enable Register\nMaster Interrupt Enable Register\nMaster Receive Data Register\nMaster Receive Data Register\nMaster Status Register\nMaster Status Register\nMaster Transmit Data Register\nMaster Transmit Data Register\nParameter Register\nParameter Register\nLPI2C\nSlave Address Match Register\nSlave Address Match Register\nSlave Address Status Register\nSlave Address Status Register\nSlave Configuration Register 1\nSlave Configuration Register 1\nSlave Configuration Register 2\nSlave Configuration Register 2\nSlave Control Register\nSlave Control Register\nSlave DMA Enable Register\nSlave DMA Enable Register\nSlave Interrupt Enable Register\nSlave Interrupt Enable Register\nSlave Receive Data Register\nSlave Receive Data Register\nSlave Status Register\nSlave Status Register\nSlave Transmit ACK Register\nSlave Transmit ACK Register\nSlave Transmit Data Register\nSlave Transmit Data Register\nVersion ID Register\nVersion ID Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nClock High Period\nClock Low Period\nData Valid Delay\nSetup Hold Delay\nClock High Period\nClock Low Period\nData Valid Delay\nSetup Hold Delay\nCircular FIFO Enable\nHost Request Enable\nHost Request Polarity\nHost Request Select\nReceive Data Match Only\nCircular FIFO is disabled\nCircular FIFO is enabled\nHost request input is disabled\nHost request input is enabled\nActive low\nActive high\nHost request input is pin HREQ\nHost request input is input trigger\nReceived data is stored in the receive FIFO\nReceived data is discarded unless the the Data Match Flag …\nAutomatic STOP Generation\nIGNACK\nMatch Configuration\nPin Configuration\nPrescaler\nTimeout Configuration\nNo effect\nSTOP condition is automatically generated whenever the …\nLPI2C Master will receive ACK and NACK normally\nLPI2C Master will treat a received NACK as if it (NACK) …\nMatch is disabled\nMatch is enabled (1st data word equals MATCH0 OR MATCH1)\nMatch is enabled (any data word equals MATCH0 OR MATCH1)\nMatch is enabled (1st data word equals MATCH0 AND 2nd data …\nMatch is enabled (any data word equals MATCH0 AND next …\nMatch is enabled (1st data word AND MATCH1 equals MATCH0 …\nMatch is enabled (any data word AND MATCH1 equals MATCH0 …\n2-pin open drain mode\n2-pin output only mode (ultra-fast mode)\n2-pin push-pull mode\n4-pin push-pull mode\n2-pin open drain mode with separate LPI2C slave\n2-pin output only mode (ultra-fast mode) with separate …\n2-pin push-pull mode with separate LPI2C slave\n4-pin push-pull mode (inverted outputs)\nDivide by 1\nDivide by 2\nDivide by 4\nDivide by 8\nDivide by 16\nDivide by 32\nDivide by 64\nDivide by 128\nPin Low Timeout Flag will set if SCL is low for longer …\nPin Low Timeout Flag will set if either SCL or SDA is low …\nBus Idle Timeout\nGlitch Filter SCL\nGlitch Filter SDA\nPin Low Timeout\nDebug Enable\nDoze mode enable\nMaster Enable\nReset Receive FIFO\nSoftware Reset\nReset Transmit FIFO\nMaster is disabled in debug mode\nMaster is enabled in debug mode\nMaster is enabled in Doze mode\nMaster is disabled in Doze mode\nMaster logic is disabled\nMaster logic is enabled\nNo effect\nReceive FIFO is reset\nMaster logic is not reset\nMaster logic is reset\nNo effect\nTransmit FIFO is reset\nReceive Data DMA Enable\nTransmit Data DMA Enable\nDMA request is disabled\nDMA request is enabled\nDMA request is disabled\nDMA request is enabled\nMatch 0 Value\nMatch 1 Value\nReceive FIFO Watermark\nTransmit FIFO Watermark\nReceive FIFO Count\nTransmit FIFO Count\nArbitration Lost Interrupt Enable\nData Match Interrupt Enable\nEnd Packet Interrupt Enable\nFIFO Error Interrupt Enable\nNACK Detect Interrupt Enable\nPin Low Timeout Interrupt Enable\nReceive Data Interrupt Enable\nSTOP Detect Interrupt Enable\nTransmit Data Interrupt Enable\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nEnabled\nDisabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nReceive Data\nRX Empty\nReceive FIFO is not empty\nReceive FIFO is empty\nArbitration Lost Flag\nBus Busy Flag\nData Match Flag\nEnd Packet Flag\nFIFO Error Flag\nMaster Busy Flag\nNACK Detect Flag\nPin Low Timeout Flag\nReceive Data Flag\nSTOP Detect Flag\nTransmit Data Flag\nMaster has not lost arbitration\nMaster has lost arbitration\nI2C Bus is idle\nI2C Bus is busy\nHave not received matching data\nHave received matching data\nMaster has not generated a STOP or Repeated START condition\nMaster has generated a STOP or Repeated START condition\nNo error\nMaster sending or receiving data without a START condition\nI2C Master is idle\nI2C Master is busy\nUnexpected NACK was not detected\nUnexpected NACK was detected\nPin low timeout has not occurred or is disabled\nPin low timeout has occurred\nReceive Data is not ready\nReceive data is ready\nMaster has not generated a STOP condition\nMaster has generated a STOP condition\nTransmit data is not requested\nTransmit data is requested\nCommand Data\nTransmit Data\nTransmit DATA[7:0]\nReceive (DATA[7:0] + 1) bytes\nGenerate STOP condition\nReceive and discard (DATA[7:0] + 1) bytes\nGenerate (repeated) START and transmit address in DATA[7:0]\nGenerate (repeated) START and transmit address in DATA[7:0…\nGenerate (repeated) START and transmit address in DATA[7:0…\nGenerate (repeated) START and transmit address in DATA[7:0…\nMaster Receive FIFO Size\nMaster Transmit FIFO Size\nAddress 0 Value\nAddress 1 Value\nAddress Not Valid\nReceived Address\nReceived Address (RADDR) is valid\nReceived Address (RADDR) is not valid\nACK SCL Stall\nAddress Configuration\nAddress SCL Stall\nGeneral Call Enable\nHigh Speed Mode Enable\nIgnore NACK\nReceive Data Configuration\nRX SCL Stall\nSMBus Alert Enable\nTransmit Flag Configuration\nTX Data SCL Stall\nClock stretching is disabled\nClock stretching is enabled\nAddress match 0 (7-bit)\nAddress match 0 (10-bit)\nAddress match 0 (7-bit) or Address match 1 (7-bit)\nAddress match 0 (10-bit) or Address match 1 (10-bit)\nAddress match 0 (7-bit) or Address match 1 (10-bit)\nAddress match 0 (10-bit) or Address match 1 (7-bit)\nFrom Address match 0 (7-bit) to Address match 1 (7-bit)\nFrom Address match 0 (10-bit) to Address match 1 (10-bit)\nClock stretching is disabled\nClock stretching is enabled\nGeneral Call address is disabled\nGeneral Call address is enabled\nDisables detection of HS-mode master code\nEnables detection of HS-mode master code\nSlave will end transfer when NACK is detected\nSlave will not end transfer when NACK detected\nReading the Receive Data register will return received …\nReading the Receive Data register when the Address Valid …\nClock stretching is disabled\nClock stretching is enabled\nDisables match on SMBus Alert\nEnables match on SMBus Alert\nTransmit Data Flag will only assert during a …\nTransmit Data Flag will assert whenever the Transmit Data …\nClock stretching is disabled\nClock stretching is enabled\nClock Hold Time\nData Valid Delay\nGlitch Filter SCL\nGlitch Filter SDA\nFilter Doze Enable\nFilter Enable\nReset Receive FIFO\nSoftware Reset\nReset Transmit FIFO\nSlave Enable\nFilter remains enabled in Doze mode\nFilter is disabled in Doze mode\nDisable digital filter and output delay counter for slave …\nEnable digital filter and output delay counter for slave …\nNo effect\nReceive Data Register is now empty\nSlave mode logic is not reset\nSlave mode logic is reset\nNo effect\nTransmit Data Register is now empty\nI2C Slave mode is disabled\nI2C Slave mode is enabled\nAddress Valid DMA Enable\nReceive Data DMA Enable\nTransmit Data DMA Enable\nDMA request is disabled\nDMA request is enabled\nDMA request is disabled\nDMA request is enabled\nDMA request is disabled\nDMA request is enabled\nAddress Match 0 Interrupt Enable\nAddress Match 1 Interrupt Enable\nAddress Match 1 Interrupt Enable\nAddress Valid Interrupt Enable\nBit Error Interrupt Enable\nFIFO Error Interrupt Enable\nGeneral Call Interrupt Enable\nReceive Data Interrupt Enable\nRepeated Start Interrupt Enable\nSMBus Alert Response Interrupt Enable\nSTOP Detect Interrupt Enable\nTransmit ACK Interrupt Enable\nTransmit Data Interrupt Enable\nEnabled\nDisabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nReceive Data\nRX Empty\nStart Of Frame\nThe Receive Data Register is not empty\nThe Receive Data Register is empty\nIndicates this is not the first data word since a …\nIndicates this is the first data word since a (repeated) …\nAddress Match 0 Flag\nAddress Match 1 Flag\nAddress Valid Flag\nBus Busy Flag\nBit Error Flag\nFIFO Error Flag\nGeneral Call Flag\nReceive Data Flag\nRepeated Start Flag\nSMBus Alert Response Flag\nSlave Busy Flag\nSTOP Detect Flag\nTransmit ACK Flag\nTransmit Data Flag\nHave not received an ADDR0 matching address\nHave received an ADDR0 matching address\nHave not received an ADDR1 or ADDR0/ADDR1 range matching …\nHave received an ADDR1 or ADDR0/ADDR1 range matching …\nAddress Status Register is not valid\nAddress Status Register is valid\nI2C Bus is idle\nI2C Bus is busy\nSlave has not detected a bit error\nSlave has detected a bit error\nFIFO underflow or overflow was not detected\nFIFO underflow or overflow was detected\nSlave has not detected the General Call Address or the …\nSlave has detected the General Call Address\nReceive data is not ready\nReceive data is ready\nSlave has not detected a Repeated START condition\nSlave has detected a Repeated START condition\nSMBus Alert Response is disabled or not detected\nSMBus Alert Response is enabled and detected\nI2C Slave is idle\nI2C Slave is busy\nSlave has not detected a STOP condition\nSlave has detected a STOP condition\nTransmit ACK/NACK is not required\nTransmit ACK/NACK is required\nTransmit data not requested\nTransmit data is requested\nTransmit NACK\nWrite a Transmit ACK for each received word\nWrite a Transmit NACK for each received word\nTransmit Data\nFeature Specification Number\nMajor Version Number\nMinor Version Number\nMaster only, with standard feature set\nMaster and slave, with standard feature set\nClock Configuration Register\nClock Configuration Register\nConfiguration Register 0\nConfiguration Register 0\nConfiguration Register 1\nConfiguration Register 1\nControl Register\nControl Register\nDMA Enable Register\nDMA Enable Register\nData Match Register 0\nData Match Register 0\nData Match Register 1\nData Match Register 1\nFIFO Control Register\nFIFO Control Register\nFIFO Status Register\nFIFO Status Register\nInterrupt Enable Register\nInterrupt Enable Register\nLPSPI\nLPSPI\nParameter Register\nParameter Register\nReceive Data Register\nReceive Data Register\nReceive Status Register\nReceive Status Register\nLPSPI\nStatus Register\nStatus Register\nTransmit Command Register\nTransmit Command Register\nTransmit Data Register\nTransmit Data Register\nVersion ID Register\nVersion ID Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nDelay Between Transfers\nPCS-to-SCK Delay\nSCK Divider\nSCK-to-PCS Delay\nCircular FIFO Enable\nHost Request Enable\nHost Request Polarity\nHost Request Select\nReceive Data Match Only\nCircular FIFO is disabled\nCircular FIFO is enabled\nReceived data is stored in the receive FIFO as in normal …\nReceived data is discarded unless the Data Match Flag …\nAutomatic PCS\nMaster Mode\nMatch Configuration\nNo Stall\nOutput Config\nPeripheral Chip Select Configuration\nPeripheral Chip Select Polarity\nPin Configuration\nSample Point\nAutomatic PCS generation is disabled\nAutomatic PCS generation is enabled\nSlave mode\nMaster mode\nMatch is disabled\n010b - Match is enabled, if 1st data word equals MATCH0 OR …\n011b - Match is enabled, if any data word equals MATCH0 OR …\n100b - Match is enabled, if 1st data word equals MATCH0 …\n101b - Match is enabled, if any data word equals MATCH0 …\n110b - Match is enabled, if (1st data word AND MATCH1) …\n111b - Match is enabled, if (any data word AND MATCH1) …\nTransfers will stall when the transmit FIFO is empty or …\nTransfers will not stall, allowing transmit FIFO underruns …\nOutput data retains last value when chip select is negated\nOutput data is tristated when chip select is negated\nPCS[3:2] are enabled\nPCS[3:2] are disabled\nSIN is used for input data and SOUT is used for output data\nSIN is used for both input and output data\nSOUT is used for both input and output data\nSOUT is used for input data and SIN is used for output data\nInput data is sampled on SCK edge\nInput data is sampled on delayed SCK edge\nDebug Enable\nDoze Mode Enable\nModule Enable\nReset Receive FIFO\nSoftware Reset\nReset Transmit FIFO\nLPSPI module is disabled in debug mode\nLPSPI module is enabled in debug mode\nLPSPI module is enabled in Doze mode\nLPSPI module is disabled in Doze mode\nModule is disabled\nModule is enabled\nNo effect\nReceive FIFO is reset\nModule is not reset\nModule is reset\nNo effect\nTransmit FIFO is reset\nReceive Data DMA Enable\nTransmit Data DMA Enable\nDMA request is disabled\nDMA request is enabled\nDMA request is disabled\nDMA request is enabled\nMatch 0 Value\nMatch 1 Value\nReceive FIFO Watermark\nTransmit FIFO Watermark\nReceive FIFO Count\nTransmit FIFO Count\nData Match Interrupt Enable\nFrame Complete Interrupt Enable\nReceive Data Interrupt Enable\nReceive Error Interrupt Enable\nTransfer Complete Interrupt Enable\nTransmit Data Interrupt Enable\nTransmit Error Interrupt Enable\nWord Complete Interrupt Enable\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nDisabled\nEnabled\nPCS Number\nReceive FIFO Size\nTransmit FIFO Size\nReceive Data\nRX FIFO Empty\nStart Of Frame\nRX FIFO is not empty\nRX FIFO is empty\nSubsequent data word received after LPSPI_PCS assertion\nFirst data word received after LPSPI_PCS assertion\nData Match Flag\nFrame Complete Flag\nModule Busy Flag\nReceive Data Flag\nReceive Error Flag\nTransfer Complete Flag\nTransmit Data Flag\nTransmit Error Flag\nWord Complete Flag\nHave not received matching data\nHave received matching data\nFrame transfer has not completed\nFrame transfer has completed\nLPSPI is idle\nLPSPI is busy\nReceive Data is not ready\nReceive data is ready\nReceive FIFO has not overflowed\nReceive FIFO has overflowed\nAll transfers have not completed\nAll transfers have completed\nTransmit data not requested\nTransmit data is requested\nTransmit FIFO underrun has not occurred\nTransmit FIFO underrun has occurred\nTransfer of a received word has not yet completed\nTransfer of a received word has completed\nByte Swap\nContinuous Transfer\nContinuing Command\nClock Phase\nClock Polarity\nFrame Size\nLSB First\nPeripheral Chip Select\nPrescaler Value\nReceive Data Mask\nTransmit Data Mask\nTransfer Width\nByte swap is disabled\nByte swap is enabled\nContinuous transfer is disabled\nContinuous transfer is enabled\nCommand word for start of new transfer\nCommand word for continuing transfer\nData is captured on the leading edge of SCK and changed on …\nData is changed on the leading edge of SCK and captured on …\nThe inactive state value of SCK is low\nThe inactive state value of SCK is high\nData is transferred MSB first\nData is transferred LSB first\nTransfer using LPSPI_PCS[0]\nTransfer using LPSPI_PCS[1]\nTransfer using LPSPI_PCS[2]\nTransfer using LPSPI_PCS[3]\nDivide by 1\nDivide by 2\nDivide by 4\nDivide by 8\nDivide by 16\nDivide by 32\nDivide by 64\nDivide by 128\nNormal transfer\nReceive data is masked\nNormal transfer\nMask transmit data\n1 bit transfer\n2 bit transfer\n4 bit transfer\nTransmit Data\nModule Identification Number\nMajor Version Number\nMinor Version Number\nStandard feature set supporting a 32-bit shift register.\nLPUART Baud Rate Register\nLPUART Baud Rate Register\nLPUART Control Register\nLPUART Control Register\nLPUART Data Register\nLPUART Data Register\nLPUART FIFO Register\nLPUART FIFO Register\nLPUART Global Register\nLPUART Global Register\nLPUART\nLPUART\nLPUART\nLPUART\nLPUART Match Address Register\nLPUART Match Address Register\nLPUART Modem IrDA Register\nLPUART Modem IrDA Register\nParameter Register\nParameter Register\nLPUART Pin Configuration Register\nLPUART Pin Configuration Register\nLPUART\nLPUART Status Register\nLPUART Status Register\nVersion ID Register\nVersion ID Register\nLPUART Watermark Register\nLPUART Watermark Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nBoth Edge Sampling\nLIN Break Detect Interrupt Enable\n10-bit Mode select\nMatch Address Mode Enable 1\nMatch Address Mode Enable 2\nMatch Configuration\nOversampling Ratio\nReceiver Full DMA Enable\nResynchronization Disable\nReceiver Idle DMA Enable\nRX Input Active Edge Interrupt Enable\nStop Bit Number Select\nBaud Rate Modulo Divisor.\nTransmitter DMA Enable\nReceiver samples input data using the rising edge of the …\nReceiver samples input data using the rising and falling …\nHardware interrupts from STAT[LBKDIF] flag are disabled …\nHardware interrupt requested when STAT[LBKDIF] flag is 1.\nReceiver and transmitter use 7-bit to 9-bit data …\nReceiver and transmitter use 10-bit data characters.\nNormal operation.\nEnables automatic address matching or data matching mode …\nNormal operation.\nEnables automatic address matching or data matching mode …\nAddress Match Wakeup\nIdle Match Wakeup\nMatch On and Match Off\nEnables RWU on Data Match and Match On/Off for transmitter …\nWriting 0 to this field will result in an oversampling …\nOversampling ratio of 11.\nOversampling ratio of 12.\nOversampling ratio of 13.\nOversampling ratio of 14.\nOversampling ratio of 15.\nOversampling ratio of 16.\nOversampling ratio of 17.\nOversampling ratio of 18.\nOversampling ratio of 19.\nOversampling ratio of 20.\nOversampling ratio of 21.\nOversampling ratio of 22.\nOversampling ratio of 23.\nOversampling ratio of 24.\nOversampling ratio of 25.\nOversampling ratio of 26.\nOversampling ratio of 27.\nOversampling ratio of 28.\nOversampling ratio of 29.\nOversampling ratio of 30.\nOversampling ratio of 4, requires BOTHEDGE to be set.\nOversampling ratio of 31.\nOversampling ratio of 32.\nOversampling ratio of 5, requires BOTHEDGE to be set.\nOversampling ratio of 6, requires BOTHEDGE to be set.\nOversampling ratio of 7, requires BOTHEDGE to be set.\nOversampling ratio of 8.\nOversampling ratio of 9.\nOversampling ratio of 10.\nDMA request disabled.\nDMA request enabled.\nResynchronization during received data word is supported\nResynchronization during received data word is disabled\nDMA request disabled.\nDMA request enabled.\nHardware interrupts from STAT[RXEDGIF] are disabled.\nHardware interrupt is requested when STAT[RXEDGIF] flag is …\nOne stop bit.\nTwo stop bits.\nDMA request disabled.\nDMA request enabled.\nDoze Enable\nFraming Error Interrupt Enable\nIdle Configuration\nIdle Line Interrupt Enable\nIdle Line Type Select\nLoop Mode Select\n9-Bit or 8-Bit Mode Select\n7-Bit Mode Select\nMatch 1 Interrupt Enable\nMatch 2 Interrupt Enable\nNoise Error Interrupt Enable\nOverrun Interrupt Enable\nParity Enable\nParity Error Interrupt Enable\nParity Type\nReceive Bit 8 / Transmit Bit 9\nReceive Bit 9 / Transmit Bit 8\nReceiver Enable\nReceiver Interrupt Enable\nReceiver Source Select\nReceiver Wakeup Control\nSend Break\nTransmission Complete Interrupt Enable for\nTransmitter Enable\nTransmit Interrupt Enable\nTXD Pin Direction in Single-Wire Mode\nTransmit Data Inversion\nReceiver Wakeup Method Select\nLPUART is enabled in Doze mode.\nLPUART is disabled in Doze mode.\nFE interrupts disabled; use polling.\nHardware interrupt requested when FE is set.\n1 idle character\n2 idle characters\n4 idle characters\n8 idle characters\n16 idle characters\n32 idle characters\n64 idle characters\n128 idle characters\nHardware interrupts from IDLE disabled; use polling.\nHardware interrupt requested when IDLE flag is 1.\nIdle character bit count starts after start bit.\nIdle character bit count starts after stop bit.\nNormal operation - RXD and TXD use separate pins.\nLoop mode or single-wire mode where transmitter outputs …\nReceiver and transmitter use 8-bit to 10-bit data …\nReceiver and transmitter use 7-bit data characters.\nReceiver and transmitter use 8-bit data characters.\nReceiver and transmitter use 9-bit data characters.\nMA1F interrupt disabled\nMA1F interrupt enabled\nMA2F interrupt disabled\nMA2F interrupt enabled\nNF interrupts disabled; use polling.\nHardware interrupt requested when NF is set.\nOR interrupts disabled; use polling.\nHardware interrupt requested when OR is set.\nNo hardware parity generation or checking.\nParity enabled.\nPF interrupts disabled; use polling).\nHardware interrupt requested when PF is set.\nEven parity.\nOdd parity.\nReceiver disabled.\nReceiver enabled.\nHardware interrupts from RDRF disabled; use polling.\nHardware interrupt requested when RDRF flag is 1.\nProvided LOOPS is set, RSRC is cleared, selects internal …\nSingle-wire LPUART mode where the TXD pin is connected to …\nNormal receiver operation.\nLPUART receiver in standby waiting for wakeup condition.\nNormal transmitter operation.\nQueue break character(s) to be sent.\nHardware interrupts from TC disabled; use polling.\nHardware interrupt requested when TC flag is 1.\nTransmitter disabled.\nTransmitter enabled.\nHardware interrupts from TDRE disabled; use polling.\nHardware interrupt requested when TDRE flag is 1.\nTXD pin is an input in single-wire mode.\nTXD pin is an output in single-wire mode.\nTransmit data not inverted.\nTransmit data inverted.\nConfigures RWU for idle-line wakeup.\nConfigures RWU with address-mark wakeup.\nFrame Error / Transmit Special Character\nIdle Line\nNOISY\nPARITYE\nR0T0\nR1T1\nR2T2\nR3T3\nR4T4\nR5T5\nR6T6\nR7T7\nR8T8\nR9T9\nReceive Buffer Empty\nThe dataword was received without a frame error on read, …\nThe dataword was received with a frame error, or transmit …\nReceiver was not idle before receiving this character.\nReceiver was idle before receiving this character.\nThe dataword was received without noise.\nThe data was received with noise.\nThe dataword was received without a parity error.\nThe dataword was received with a parity error.\nReceive buffer contains valid data.\nReceive buffer is empty, data returned on read is not …\nReceive Buffer/FIFO Empty\nReceive FIFO Enable\nReceive FIFO Buffer Depth\nReceive FIFO/Buffer Flush\nReceiver Idle Empty Enable\nReceiver Buffer Underflow Flag\nReceive FIFO Underflow Interrupt Enable\nTransmit Buffer/FIFO Empty\nTransmit FIFO Enable\nTransmit FIFO Buffer Depth\nTransmit FIFO/Buffer Flush\nTransmitter Buffer Overflow Flag\nTransmit FIFO Overflow Interrupt Enable\nReceive buffer is not empty.\nReceive buffer is empty.\nReceive FIFO is not enabled. Buffer is depth 1.\nReceive FIFO is enabled. Buffer is depth indicted by …\nReceive FIFO/Buffer depth = 1 dataword.\nReceive FIFO/Buffer depth = 4 datawords.\nReceive FIFO/Buffer depth = 8 datawords.\nReceive FIFO/Buffer depth = 16 datawords.\nReceive FIFO/Buffer depth = 32 datawords.\nReceive FIFO/Buffer depth = 64 datawords.\nReceive FIFO/Buffer depth = 128 datawords.\nReceive FIFO/Buffer depth = 256 datawords.\nNo flush operation occurs.\nAll data in the receive FIFO/buffer is cleared out.\nDisable RDRF assertion due to partially filled FIFO when …\nEnable RDRF assertion due to partially filled FIFO when …\nEnable RDRF assertion due to partially filled FIFO when …\nEnable RDRF assertion due to partially filled FIFO when …\nEnable RDRF assertion due to partially filled FIFO when …\nEnable RDRF assertion due to partially filled FIFO when …\nEnable RDRF assertion due to partially filled FIFO when …\nEnable RDRF assertion due to partially filled FIFO when …\nNo receive buffer underflow has occurred since the last …\nAt least one receive buffer underflow has occurred since …\nRXUF flag does not generate an interrupt to the host.\nRXUF flag generates an interrupt to the host.\nTransmit buffer is not empty.\nTransmit buffer is empty.\nTransmit FIFO is not enabled. Buffer is depth 1.\nTransmit FIFO is enabled. Buffer is depth indicated by …\nTransmit FIFO/Buffer depth = 1 dataword.\nTransmit FIFO/Buffer depth = 4 datawords.\nTransmit FIFO/Buffer depth = 8 datawords.\nTransmit FIFO/Buffer depth = 16 datawords.\nTransmit FIFO/Buffer depth = 32 datawords.\nTransmit FIFO/Buffer depth = 64 datawords.\nTransmit FIFO/Buffer depth = 128 datawords.\nTransmit FIFO/Buffer depth = 256 datawords\nNo flush operation occurs.\nAll data in the transmit FIFO/Buffer is cleared out.\nNo transmit buffer overflow has occurred since the last …\nAt least one transmit buffer overflow has occurred since …\nTXOF flag does not generate an interrupt to the host.\nTXOF flag generates an interrupt to the host.\nSoftware Reset\nModule is not reset.\nModule is reset.\nMatch Address 1\nMatch Address 2\nInfrared enable\nReceive RTS Configuration\nReceiver request-to-send enable\nTransmitter narrow pulse\nTransmit CTS Configuration\nTransmitter clear-to-send enable\nTransmit CTS Source\nTransmitter request-to-send enable\nTransmitter request-to-send polarity\nIR disabled.\nIR enabled.\nThe receiver has no effect on RTS.\nRTS is deasserted if the receiver data register is full or …\n1/OSR.\n2/OSR.\n3/OSR.\n4/OSR.\nCTS input is sampled at the start of each character.\nCTS input is sampled when the transmitter is idle.\nCTS has no effect on the transmitter.\nEnables clear-to-send operation. The transmitter checks …\nCTS input is the CTS_B pin.\nCTS input is the inverted Receiver Match result.\nThe transmitter has no effect on RTS.\nWhen a character is placed into an empty transmitter data …\nTransmitter RTS is active low.\nTransmitter RTS is active high.\nReceive FIFO Size\nTransmit FIFO Size\nTrigger Select\nInput trigger is disabled.\nInput trigger is used instead of RXD pin input.\nInput trigger is used instead of CTS_B pin input.\nInput trigger is used to modulate the TXD pin output. The …\nBreak Character Generation Length\nFraming Error Flag\nIdle Line Flag\nLIN Break Detection Enable\nLIN Break Detect Interrupt Flag\nMatch 1 Flag\nMatch 2 Flag\nMSB First\nNoise Flag\nReceiver Overrun Flag\nParity Error Flag\nReceiver Active Flag\nReceive Data Register Full Flag\nReceive Wake Up Idle Detect\nRXD Pin Active Edge Interrupt Flag\nReceive Data Inversion\nTransmission Complete Flag\nTransmit Data Register Empty Flag\nBreak character is transmitted with length of 9 to 13 bit …\nBreak character is transmitted with length of 12 to 15 bit …\nNo framing error detected. This does not guarantee the …\nFraming error.\nNo idle line detected.\nIdle line was detected.\nLIN break detect is disabled, normal break character can …\nLIN break detect is enabled. LIN break character is …\nNo LIN break character has been detected.\nLIN break character has been detected.\nReceived data is not equal to MA1\nReceived data is equal to MA1\nReceived data is not equal to MA2\nReceived data is equal to MA2\nLSB (bit0) is the first bit that is transmitted following …\nMSB (bit9, bit8, bit7 or bit6) is the first bit that is …\nNo noise detected.\nNoise detected in the received character in the DATA …\nNo overrun.\nReceive overrun (new LPUART data lost).\nNo parity error.\nParity error.\nLPUART receiver idle waiting for a start bit.\nLPUART receiver active (RXD input not idle).\nReceive data buffer empty.\nReceive data buffer full.\nDuring receive standby state (RWU = 1), the IDLE bit does …\nDuring receive standby state (RWU = 1), the IDLE bit gets …\nNo active edge on the receive pin has occurred.\nAn active edge on the receive pin has occurred.\nReceive data not inverted.\nReceive data inverted.\nTransmitter active (sending data, a preamble, or a break).\nTransmitter idle (transmission activity complete).\nTransmit data buffer full.\nTransmit data buffer empty.\nFeature Identification Number\nMajor Version Number\nMinor Version Number\nStandard feature set.\nStandard feature set with MODEM/IrDA support.\nReceive Counter\nReceive Watermark\nTransmit Counter\nTransmit Watermark\nValue of OTP Bank1 Word5 (Analog Info.)\nValue of OTP Bank1 Word5 (Analog Info.)\nValue of OTP Bank1 Word6 (Analog Info.)\nValue of OTP Bank1 Word6 (Analog Info.)\nValue of OTP Bank1 Word7 (Analog Info.)\nValue of OTP Bank1 Word7 (Analog Info.)\nValue of OTP Bank0 Word1 (Configuration and Manufacturing …\nValue of OTP Bank0 Word1 (Configuration and Manufacturing …\nValue of OTP Bank0 Word2 (Configuration and Manufacturing …\nValue of OTP Bank0 Word2 (Configuration and Manufacturing …\nValue of OTP Bank0 Word3 (Configuration and Manufacturing …\nValue of OTP Bank0 Word3 (Configuration and Manufacturing …\nValue of OTP Bank0 Word4 (Configuration and Manufacturing …\nValue of OTP Bank0 Word4 (Configuration and Manufacturing …\nValue of OTP Bank0 Word5 (Configuration and Manufacturing …\nValue of OTP Bank0 Word5 (Configuration and Manufacturing …\nValue of OTP Bank0 Word6 (Configuration and Manufacturing …\nValue of OTP Bank0 Word6 (Configuration and Manufacturing …\nValue of OTP Bank0 Word7 (Configuration and Manufacturing …\nValue of OTP Bank0 Word7 (Configuration and Manufacturing …\nOTP Controller Control Register\nOTP Controller Control Register\nOTP Controller Control Register\nOTP Controller Control Register\nOTP Controller Control Register\nOTP Controller Control Register\nOTP Controller Control Register\nOTP Controller Control Register\nOTP Controller Write Data Register\nOTP Controller Write Data Register\nValue of OTP Bank4 Word6 (General Purpose Customer Defined …\nValue of OTP Bank4 Word6 (General Purpose Customer Defined …\nValue of OTP Bank4 Word7 (General Purpose Customer Defined …\nValue of OTP Bank4 Word7 (General Purpose Customer Defined …\nValue of OTP Bank4 Word4 (MAC Address)\nValue of OTP Bank4 Word4 (MAC Address)\nValue of OTP Bank0 Word0 (Lock controls)\nValue of OTP Bank0 Word0 (Lock controls)\nValue of OTP Bank4 Word2 (MAC Address)\nValue of OTP Bank4 Word2 (MAC Address)\nValue of OTP Bank4 Word3 (MAC Address)\nValue of OTP Bank4 Word3 (MAC Address)\nValue of OTP Bank1 Word0 (Memory Related Info.)\nValue of OTP Bank1 Word0 (Memory Related Info.)\nValue of OTP Bank1 Word1 (Memory Related Info.)\nValue of OTP Bank1 Word1 (Memory Related Info.)\nValue of OTP Bank1 Word2 (Memory Related Info.)\nValue of OTP Bank1 Word2 (Memory Related Info.)\nValue of OTP Bank1 Word3 (Memory Related Info.)\nValue of OTP Bank1 Word3 (Memory Related Info.)\nValue of OTP Bank1 Word4 (Memory Related Info.)\nValue of OTP Bank1 Word4 (Memory Related Info.)\nValue of OTP Bank5 Word5 (Misc Conf)\nValue of OTP Bank5 Word5 (Misc Conf)\nValue of OTP Bank5 Word6 (Misc Conf)\nValue of OTP Bank5 Word6 (Misc Conf)\nno description available\nOTP Controller Write Data Register\nOTP Controller Write Data Register\nOTP Controller Read Data Register\nOTP Controller Read Data Register\nno description available\nSoftware Controllable Signals Register\nSoftware Controllable Signals Register\nSoftware Controllable Signals Register\nSoftware Controllable Signals Register\nSoftware Controllable Signals Register\nSoftware Controllable Signals Register\nSoftware Controllable Signals Register\nSoftware Controllable Signals Register\nValue of OTP Bank4 Word0 (Secure JTAG Response Field)\nValue of OTP Bank4 Word0 (Secure JTAG Response Field)\nValue of OTP Bank4 Word1 (Secure JTAG Response Field)\nValue of OTP Bank4 Word1 (Secure JTAG Response Field)\nShadow Register for OTP Bank3 Word0 (SRK Hash)\nShadow Register for OTP Bank3 Word0 (SRK Hash)\nShadow Register for OTP Bank3 Word1 (SRK Hash)\nShadow Register for OTP Bank3 Word1 (SRK Hash)\nShadow Register for OTP Bank3 Word2 (SRK Hash)\nShadow Register for OTP Bank3 Word2 (SRK Hash)\nShadow Register for OTP Bank3 Word3 (SRK Hash)\nShadow Register for OTP Bank3 Word3 (SRK Hash)\nShadow Register for OTP Bank3 Word4 (SRK Hash)\nShadow Register for OTP Bank3 Word4 (SRK Hash)\nShadow Register for OTP Bank3 Word5 (SRK Hash)\nShadow Register for OTP Bank3 Word5 (SRK Hash)\nShadow Register for OTP Bank3 Word6 (SRK Hash)\nShadow Register for OTP Bank3 Word6 (SRK Hash)\nShadow Register for OTP Bank3 Word7 (SRK Hash)\nShadow Register for OTP Bank3 Word7 (SRK Hash)\nValue of OTP Bank5 Word7 (SRK Revoke)\nValue of OTP Bank5 Word7 (SRK Revoke)\nValue of OTP Bank5 Word0 (SW GP1)\nValue of OTP Bank5 Word0 (SW GP1)\nValue of OTP Bank5 Word1 (SW GP2)\nValue of OTP Bank5 Word1 (SW GP2)\nValue of OTP Bank5 Word2 (SW GP2)\nValue of OTP Bank5 Word2 (SW GP2)\nValue of OTP Bank5 Word3 (SW GP2)\nValue of OTP Bank5 Word3 (SW GP2)\nValue of OTP Bank5 Word4 (SW GP2)\nValue of OTP Bank5 Word4 (SW GP2)\nSticky bit Register\nSticky bit Register\nOTP Controller Timing Register\nOTP Controller Timing Register\nOTP Controller Timing Register 2\nOTP Controller Timing Register 2\nOTP Controller Version Register\nOTP Controller Version Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nReflects value of OTP bank 1, word 5 (ADDR = 0x0D)\nReflects value of OTP bank 1, word 6 (ADDR = 0x0E)\nReflects value of OTP bank 1, word 7 (ADDR = 0x0F)\nThis register contains 32 bits of the Unique ID and …\nThis register contains 32 bits of the Unique ID and …\nReflects value of OTP Bank 0, word 3 (ADDR = 0x03)\nReflects value of OTP Bank 0, word 4 (ADDR = 0x04)\nReflects value of OTP Bank 0, word 5 (ADDR = 0x05)\nReflects value of OTP Bank 0, word 6 (ADDR = 0x06)\nReflects value of OTP Bank 0, word 7 (ADDR = 0x07)\nOTP write and read access address register\nOTP controller status bit\nSet by the controller when an access to a locked …\nSet to force re-loading the shadow registers (HW/SW …\nWrite 0x3E77 to enable OTP write accesses\nOTP write and read access address register\nOTP controller status bit\nSet by the controller when an access to a locked …\nSet to force re-loading the shadow registers (HW/SW …\nWrite 0x3E77 to enable OTP write accesses\nOTP write and read access address register\nOTP controller status bit\nSet by the controller when an access to a locked …\nSet to force re-loading the shadow registers (HW/SW …\nWrite 0x3E77 to enable OTP write accesses\nOTP write and read access address register\nOTP controller status bit\nSet by the controller when an access to a locked …\nSet to force re-loading the shadow registers (HW/SW …\nWrite 0x3E77 to enable OTP write accesses\nUsed to initiate a write to OTP\nReflects value of OTP Bank 4, word 6 (ADDR = 0x26).\nReflects value of OTP Bank 4, word 7 (ADDR = 0x27).\nReflects value of OTP Bank 4, word 4 (ADDR = 0x24).\nStatus of shadow register and OTP write lock for analog …\nStatus of shadow register and OTP write lock for boot_cfg …\nReserved\nStatus of shadow register and OTP write lock for gp1 region\nStatus of shadow register and OTP write lock for gp2 region\nStatus of shadow register and OTP write lock for gp3 region\nStatus of shadow register and OTP write lock for mac_addr …\nStatus of shadow register and OTP write lock for mem_trim …\nStatus of shadow register and OTP write lock for misc_conf …\nStatus of shadow register and OTP write lock for otpmk_crc …\nStatus of shadow register read and write, OTP read and …\nStatus of shadow register read and write, OTP read and …\nStatus of shadow register read and write, OTP read and …\nStatus of shadow register and OTP write lock for sw_gp1 …\nStatus of shadow register and OTP write lock for sw_gp2 …\nStatus of shadow register and OTP read lock for sw_gp2 …\nStatus of shadow register and OTP write lock for tester …\nReflects value of OTP Bank 4, word 2 (ADDR = 0x22).\nReflects value of OTP Bank 4, word 3 (ADDR = 0x23).\nReflects value of OTP bank 1, word 0 (ADDR = 0x08)\nReflects value of OTP bank 1, word 1 (ADDR = 0x09)\nReflects value of OTP bank 1, word 2 (ADDR = 0x0A)\nReflects value of OTP bank 1, word 3 (ADDR = 0x0B)\nReflects value of OTP bank 1, word 4 (ADDR = 0x0C)\nReflects value of OTP Bank 5, word 5 (ADDR = 0x2d).\nReflects value of OTP Bank 5, word 6 (ADDR = 0x2e).\nUsed to initiate a read to OTP\nThe data read from OTP\nHAB JTAG Debug Enable\nWhen set, all of the bits in this register are locked and …\nUnallocated read/write bits for implementation specific …\nHAB JTAG Debug Enable\nWhen set, all of the bits in this register are locked and …\nUnallocated read/write bits for implementation specific …\nHAB JTAG Debug Enable\nWhen set, all of the bits in this register are locked and …\nUnallocated read/write bits for implementation specific …\nHAB JTAG Debug Enable\nWhen set, all of the bits in this register are locked and …\nUnallocated read/write bits for implementation specific …\nShadow register for the SJC_RESP Key word0 (Copy of OTP …\nShadow register for the SJC_RESP Key word1 (Copy of OTP …\nShadow register for the hash of the Super Root Key word0 …\nShadow register for the hash of the Super Root Key word1 …\nShadow register for the hash of the Super Root Key word2 …\nShadow register for the hash of the Super Root Key word3 …\nShadow register for the hash of the Super Root Key word4 …\nShadow register for the hash of the Super Root Key word5 …\nShadow register for the hash of the Super Root Key word6 …\nShadow register for the hash of the Super Root Key word7 …\nReflects value of OTP Bank 5, word 7 (ADDR = 0x2f).\nReflects value of OTP Bank 5, word 0 (ADDR = 0x28).\nReflects value of OTP Bank 5, word 1 (ADDR = 0x29).\nReflects value of OTP Bank 5, word 2 (ADDR = 0x2a).\nReflects value of OTP Bank 5, word 3 (ADDR = 0x2b).\nReflects value of OTP Bank 5, word 4 (ADDR = 0x2c).\nShadow register write and OTP write lock for FIELD_RETURN …\nShadow register write and OTP write lock for SRK_REVOKE …\nThis count value specifies the time to add to all default …\nThis count value specifies the strobe period in one time …\nThis count value specifies the strobe period in one time …\nThis count value specifies time interval between auto read …\nThis count value specifies time interval between auto read …\nThis count value specifies the strobe period in one time …\nThis count value specifies the strobe period in one time …\nFixed read-only value reflecting the MAJOR field of the …\nFixed read-only value reflecting the MINOR field of the …\nFixed read-only value reflecting the stepping of the RTL …\nControl Register\nControl Register\nno description available\nOTFAD\nOTFAD\nStatus Register\nStatus Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nForce Error\nForce Logically Disabled Mode\nForce Security Violation Mode\nGlobal OTFAD Enable\nIRQE\nKey Blob CRC Enable\nKey Blob Processing Enable\nKey Blob Scramble Enable\nRestricted Register Access Enable\nStart key blob processing\nNo effect on the SR[KBERE] indicator.\nSR[KBERR] is immediately set after a write with this data …\nNo effect on the operating mode.\nForce entry into LDM after a write with this data bit set. …\nNo effect on the operating mode.\nForce entry into SVM after a write with this data bit set …\nOTFAD has decryption disabled. All data fetched by the …\nOTFAD has decryption enabled, and processes data fetched …\nSR[KBERR] = 1 does not generate an interrupt request.\nSR[KBERR] = 1 generates an interrupt request.\nCRC-32 during key blob processing is disabled.\nCRC-32 during key blob processing is enabled.\nKey blob processing is disabled.\nKey blob processing is enabled.\nKey blob KEK scrambling is disabled.\nKey blob KEK scrambling is enabled.\nRegister access is fully enabled. The OTFAD programming …\nRegister access is restricted and only the CR, SR and …\nKey blob processing is not initiated.\nProperly-enabled key blob processing is initiated.\nContext Error\nContext Error\nContext Error\nContext Error\nContext Integrity Error\nContext Integrity Error\nContext Integrity Error\nContext Integrity Error\nGlobal Enable Mode\nHardware Revision Level\nKey Blob Processing Done\nKey Blob Error\nKey Blob Processing Enable\nMDPC Present\nOperating Mode\nNumber of Contexts\nRestricted Register Access Mode\nEither a key blob integrity error or a key blob CRC error …\nNo key blob error was detected for context “n”.\nEither a key blob integrity error or a key blob CRC error …\nNo key blob error was detected for context “n”.\nEither a key blob integrity error or a key blob CRC error …\nNo key blob error was detected for context “n”.\nEither a key blob integrity error or a key blob CRC error …\nNo key blob error was detected for context “n”.\nA key blob integrity error was detected in context “n”.\nNo key blob integrity error was detected for context “n…\nA key blob integrity error was detected in context “n”.\nNo key blob integrity error was detected for context “n…\nA key blob integrity error was detected in context “n”.\nNo key blob integrity error was detected for context “n…\nA key blob integrity error was detected in context “n”.\nNo key blob integrity error was detected for context “n…\nOTFAD is disabled. All data fetched by the FlexSPI …\nOTFAD is enabled, and processes data fetched by the …\nKey blob processing was not enabled, or is not complete.\nKey blob processing was enabled and is complete.\nNo key blob error detected.\nOne or more key blob errors has been detected.\nKey blob processing is not enabled.\nKey blob processing is enabled.\nOperating in Normal mode (NRM)\nUnused (reserved)\nOperating in Security Violation Mode (SVM)\nOperating in Logically Disabled Mode (LDM)\nRegister access is fully enabled. The OTFAD programming …\nRegister access is restricted and only the CR, SR and …\nAES Counter Word\nAES Counter Word\nAES Key Word\nAES Key Word\nAES Region Descriptor Word0\nAES Region Descriptor Word0\nAES Region Descriptor Word1\nAES Region Descriptor Word1\nno description available\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nAES Counter\nAES Key\nStart Address\nAES Decryption Enable.\nEnd Address\nRead-Only\nValid\nBypass the fetched data.\nPerform the CTR-AES128 mode decryption on the fetched data.\nThe context registers can be accessed normally (as defined …\nThe context registers are read-only and accesses may be …\nContext is invalid.\nContext is valid.\nPGC CPU Control Register\nPGC CPU Control Register\nPGC CPU Pull Down Sequence Control Register\nPGC CPU Pull Down Sequence Control Register\nPGC CPU Power Up Sequence Control Register\nPGC CPU Power Up Sequence Control Register\nPGC CPU Power Gating Controller Status Register\nPGC CPU Power Gating Controller Status Register\nPGC Mega Control Register\nPGC Mega Control Register\nPGC Mega Pull Down Sequence Control Register\nPGC Mega Pull Down Sequence Control Register\nPGC Mega Power Up Sequence Control Register\nPGC Mega Power Up Sequence Control Register\nPGC Mega Power Gating Controller Status Register\nPGC Mega Power Gating Controller Status Register\nPGC\nPGC\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nPower Control PCR must not change from power-down request …\nDo not switch off power even if pdn_req is asserted.\nSwitch off power when pdn_req is asserted.\nAfter a power-down request (pdn_req assertion), the PGC …\nAfter asserting isolation, the PGC waits a number of 32k …\nThere are two different silicon revisions: 1\nThere are two different silicon revisions: 1\nPower status\nThe target subsystem was not powered down for the previous …\nThe target subsystem was powered down for the previous …\nPower Control PCR must not change from power-down request …\nDo not switch off power even if pdn_req is asserted.\nSwitch off power when pdn_req is asserted.\nAfter a power-down request (pdn_req assertion), the PGC …\nAfter asserting isolation, the PGC waits a number of IPG …\nAfter a power-up request (pup_req assertion), the PGC …\nAfter asserting power toggle on/off signal (switch_b), the …\nPower status\nThe target subsystem was not powered down for the previous …\nThe target subsystem was powered down for the previous …\nPIT Upper Lifetime Timer Register\nPIT Upper Lifetime Timer Register\nPIT Lower Lifetime Timer Register\nPIT Lower Lifetime Timer Register\nPIT Module Control Register\nPIT Module Control Register\nPIT\nPIT\nno description available\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nLife Timer value\nLife Timer value\nFreeze\nModule Disable for PIT\nTimers continue to run in Debug mode.\nTimers are stopped in Debug mode.\nClock for standard PIT timers is enabled.\nClock for standard PIT timers is disabled.\nCurrent Timer Value Register\nCurrent Timer Value Register\nTimer Load Value Register\nTimer Load Value Register\nno description available\nTimer Control Register\nTimer Control Register\nTimer Flag Register\nTimer Flag Register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCurrent Timer Value\nTimer Start Value\nChain Mode\nTimer Enable\nTimer Interrupt Enable\nTimer is not chained.\nTimer is chained to a previous timer. For example, for …\nTimer n is disabled.\nTimer n is enabled.\nInterrupt requests from Timer n are disabled.\nInterrupt is requested whenever TIF is set.\nTimer Interrupt Flag\nTimeout has not yet occurred.\nTimeout has occurred.\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 0\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Register 1\nMiscellaneous Control Register\nMiscellaneous Control Register\nMiscellaneous Control Register\nMiscellaneous Control Register\nMiscellaneous Control Register\nMiscellaneous Control Register\nMiscellaneous Control Register\nMiscellaneous Control Register\nPMU\nRegulator 1P1 Register\nRegulator 1P1 Register\nRegulator 1P1 Register\nRegulator 1P1 Register\nRegulator 1P1 Register\nRegulator 1P1 Register\nRegulator 1P1 Register\nRegulator 1P1 Register\nRegulator 2P5 Register\nRegulator 2P5 Register\nRegulator 2P5 Register\nRegulator 2P5 Register\nRegulator 2P5 Register\nRegulator 2P5 Register\nRegulator 2P5 Register\nRegulator 2P5 Register\nRegulator 3P0 Register\nRegulator 3P0 Register\nRegulator 3P0 Register\nRegulator 3P0 Register\nRegulator 3P0 Register\nRegulator 3P0 Register\nRegulator 3P0 Register\nRegulator 3P0 Register\nDigital Regulator Core Register\nDigital Regulator Core Register\nDigital Regulator Core Register\nDigital Regulator Core Register\nDigital Regulator Core Register\nDigital Regulator Core Register\nDigital Regulator Core Register\nDigital Regulator Core Register\nPMU\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to enable the low-power mode in the analog …\nControl bit to power-down the analog bandgap reference …\nControl bit to power down the VBG-up detection circuitry …\nControl bit to disable the self-bias circuit in the analog …\nno description available\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAnalog regulators are ON.\nSUSPEND (DSM)\nSTOP (lower power)\nSTOP (very lower power)\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to enable the low-power mode in the analog …\nControl bit to power-down the analog bandgap reference …\nControl bit to power down the VBG-up detection circuitry …\nControl bit to disable the self-bias circuit in the analog …\nno description available\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAnalog regulators are ON.\nSUSPEND (DSM)\nSTOP (lower power)\nSTOP (very lower power)\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to enable the low-power mode in the analog …\nControl bit to power-down the analog bandgap reference …\nControl bit to power down the VBG-up detection circuitry …\nControl bit to disable the self-bias circuit in the analog …\nno description available\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAnalog regulators are ON.\nSUSPEND (DSM)\nSTOP (lower power)\nSTOP (very lower power)\nThis bit allows disabling the clock gate (always ungated) …\nThis field specifies the delay between powering up the …\nThis bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.\nThis field determines the bias current in the 24MHz …\nStatus bit that signals that the output of the 24-MHz …\nThis bit enables the detector that signals when the 24MHz …\nControl bit to enable the low-power mode in the analog …\nControl bit to power-down the analog bandgap reference …\nControl bit to power down the VBG-up detection circuitry …\nControl bit to disable the self-bias circuit in the analog …\nno description available\nStatus bit that signals the analog bandgap voltage is up …\nThis field indicates which chip source is being used for …\nConfigure the analog behavior in stop mode.\nThis field powers down the 24M crystal oscillator if set …\nAllow the logic to automatically gate the clock when the …\nPrevent the logic from ever gating off the clock.\n0.5ms\n1.0ms\n2.0ms\n3.0ms\n4.0ms\n5.0ms\n6.0ms\n7.0ms\nTurn on the switch\nTurn off the switch\nDecrease current by 12.5%\nDecrease current by 25.0%\nDecrease current by 37.5%\nNominal\nUses coarse bias currents for startup\nUses bandgap-based bias currents for best performance.\nNominal VBG\nVBG+0.78%\nVBG+1.56%\nVBG+2.34%\nVBG-0.78%\nVBG-1.56%\nVBG-2.34%\nVBG-3.12%\nInternal ring oscillator\nRTC_XTAL\nAnalog regulators are ON.\nSUSPEND (DSM)\nSTOP (lower power)\nSTOP (very lower power)\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nThis status bit is set to one when when any of the analog …\nThis status bit is set to one when when any of the digital …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis status bit is set to one when the temperature sensor …\nThis enables a feature that will clkgate (reset) all …\nThis enables a feature that will clkgate (reset) all …\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nDefault value of “0”\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.\nEnables the brownout detection.\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nDefault value of “0”\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.\nEnables the brownout detection.\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nDefault value of “0”\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.\nEnables the brownout detection.\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nLSB of Post-divider for Audio PLL\nMSB of Post-divider for Audio PLL\nDefault value of “0”\nThis field defines the brown out voltage offset for the …\nReg0 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg1 brownout status bit.\nEnables the brownout detection.\nNumber of clock periods (24MHz clock).\nThis field defines the brown out voltage offset for the …\nReg2 brownout status bit.\nEnables the brownout detection.\nSignals that the voltage is above the brownout level for …\nNumber of clock periods (24MHz clock).\ndivide by 1 (Default)\ndivide by 2\ndivide by 1 (Default)\ndivide by 2\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\nBrownout, supply is below target minus brownout offset.\n128\n256\n512\n64\nBrownout offset = 0.100V\nBrownout offset = 0.175V\n128\n256\n512\n64\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 1p1 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelects the source for the reference voltage of the weak …\n1.1V\n0.8V\nWeak-linreg output tracks low-power-bandgap voltage\nWeak-linreg output tracks VDD_SOC_IN voltage\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 1p1 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelects the source for the reference voltage of the weak …\n1.1V\n0.8V\nWeak-linreg output tracks low-power-bandgap voltage\nWeak-linreg output tracks VDD_SOC_IN voltage\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 1p1 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelects the source for the reference voltage of the weak …\n1.1V\n0.8V\nWeak-linreg output tracks low-power-bandgap voltage\nWeak-linreg output tracks VDD_SOC_IN voltage\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 1p1 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelects the source for the reference voltage of the weak …\n1.1V\n0.8V\nWeak-linreg output tracks low-power-bandgap voltage\nWeak-linreg output tracks VDD_SOC_IN voltage\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 2p5 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\n2.10V\n2.50V\n2.875V\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 2p5 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\n2.10V\n2.50V\n2.875V\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 2p5 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\n2.10V\n2.50V\n2.875V\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output.\nControl bit to enable the pull-down circuitry in the …\nEnables the weak 2p5 regulator\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\n2.10V\n2.50V\n2.875V\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output to be set by …\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelect input voltage source for LDO_3P0 from either …\n2.625V\n3.000V\n3.400V\nUtilize VBUS OTG1 power\nUtilize VBUS OTG2 power\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output to be set by …\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelect input voltage source for LDO_3P0 from either …\n2.625V\n3.000V\n3.400V\nUtilize VBUS OTG1 power\nUtilize VBUS OTG2 power\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output to be set by …\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelect input voltage source for LDO_3P0 from either …\n2.625V\n3.000V\n3.400V\nUtilize VBUS OTG1 power\nUtilize VBUS OTG2 power\nControl bits to adjust the regulator brownout offset …\nStatus bit that signals when a brownout is detected on the …\nControl bit to enable the brownout circuitry in the …\nControl bit to enable the current-limit circuitry in the …\nControl bit to enable the regulator output to be set by …\nStatus bit that signals when the regulator output is ok. 1 …\nControl bits to adjust the regulator output voltage\nSelect input voltage source for LDO_3P0 from either …\n2.625V\n3.000V\n3.400V\nUtilize VBUS OTG1 power\nUtilize VBUS OTG2 power\nIf set, increases the gate drive on power gating FETs to …\nRegulator voltage ramp rate.\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the ARM core …\nThis bit field defines the adjustment bits to calibrate …\nThis bit field defines the target voltage for the vpu/gpu …\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the SOC power …\nFast\nMedium Fast\nMedium Slow\nSlow\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nIf set, increases the gate drive on power gating FETs to …\nRegulator voltage ramp rate.\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the ARM core …\nThis bit field defines the adjustment bits to calibrate …\nThis bit field defines the target voltage for the vpu/gpu …\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the SOC power …\nFast\nMedium Fast\nMedium Slow\nSlow\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nIf set, increases the gate drive on power gating FETs to …\nRegulator voltage ramp rate.\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the ARM core …\nThis bit field defines the adjustment bits to calibrate …\nThis bit field defines the target voltage for the vpu/gpu …\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the SOC power …\nFast\nMedium Fast\nMedium Slow\nSlow\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nIf set, increases the gate drive on power gating FETs to …\nRegulator voltage ramp rate.\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the ARM core …\nThis bit field defines the adjustment bits to calibrate …\nThis bit field defines the target voltage for the vpu/gpu …\nThis bit field defines the adjustment bits to calibrate …\nThis field defines the target voltage for the SOC power …\nFast\nMedium Fast\nMedium Slow\nSlow\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nNo adjustment\n0.25%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n2.00%\n0.50%\n0.75%\n1.00%\n1.25%\n1.50%\n1.75%\n0.25%\n0.50%\nPower gated off\nTarget core voltage = 0.725V\nTarget core voltage = 1.100V\nTarget core voltage = 0.750V\nTarget core voltage = 0.775V\nTarget core voltage = 1.450V\nPower FET switched full on. No regulation.\nPWM Source Select Register\nPWM Source Select Register\nFault Control Register\nFault Control Register\nFault Control 2 Register\nFault Control 2 Register\nFault Filter Register\nFault Filter Register\nFault Status Register\nFault Status Register\nFault Test Register\nFault Test Register\nMask Register\nMask Register\nMaster Control Register\nMaster Control Register\nMaster Control 2 Register\nMaster Control 2 Register\nOutput Enable Register\nOutput Enable Register\nPWM\nPWM\nCluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, …\nSoftware Controlled Output Register\nSoftware Controlled Output Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nSubmodule 0 PWM23 Control Select\nSubmodule 0 PWM45 Control Select\nSubmodule 1 PWM23 Control Select\nSubmodule 1 PWM45 Control Select\nSubmodule 2 PWM23 Control Select\nSubmodule 2 PWM45 Control Select\nSubmodule 3 PWM23 Control Select\nSubmodule 3 PWM45 Control Select\nGenerated SM0PWM23 signal is used by the deadtime logic.\nInverted generated SM0PWM23 signal is used by the deadtime …\nSWCOUT[SM0OUT23] is used by the deadtime logic.\nPWM0_EXTA signal is used by the deadtime logic.\nGenerated SM0PWM45 signal is used by the deadtime logic.\nInverted generated SM0PWM45 signal is used by the deadtime …\nSWCOUT[SM0OUT45] is used by the deadtime logic.\nPWM0_EXTB signal is used by the deadtime logic.\nGenerated SM1PWM23 signal is used by the deadtime logic.\nInverted generated SM1PWM23 signal is used by the deadtime …\nSWCOUT[SM1OUT23] is used by the deadtime logic.\nPWM1_EXTA signal is used by the deadtime logic.\nGenerated SM1PWM45 signal is used by the deadtime logic.\nInverted generated SM1PWM45 signal is used by the deadtime …\nSWCOUT[SM1OUT45] is used by the deadtime logic.\nPWM1_EXTB signal is used by the deadtime logic.\nGenerated SM2PWM23 signal is used by the deadtime logic.\nInverted generated SM2PWM23 signal is used by the deadtime …\nSWCOUT[SM2OUT23] is used by the deadtime logic.\nPWM2_EXTA signal is used by the deadtime logic.\nGenerated SM2PWM45 signal is used by the deadtime logic.\nInverted generated SM2PWM45 signal is used by the deadtime …\nSWCOUT[SM2OUT45] is used by the deadtime logic.\nPWM2_EXTB signal is used by the deadtime logic.\nGenerated SM3PWM23 signal is used by the deadtime logic.\nInverted generated SM3PWM23 signal is used by the deadtime …\nSWCOUT[SM3OUT23] is used by the deadtime logic.\nPWM3_EXTA signal is used by the deadtime logic.\nGenerated SM3PWM45 signal is used by the deadtime logic.\nInverted generated SM3PWM45 signal is used by the deadtime …\nSWCOUT[SM3OUT45] is used by the deadtime logic.\nPWM3_EXTB signal is used by the deadtime logic.\nAutomatic Fault Clearing\nFault Interrupt Enables\nFault Level\nFault Safety Mode\nManual fault clearing. PWM outputs disabled by this fault …\nAutomatic fault clearing. PWM outputs disabled by this …\nFAULTx CPU interrupt requests disabled.\nFAULTx CPU interrupt requests enabled.\nA logic 0 on the fault input indicates a fault condition.\nA logic 1 on the fault input indicates a fault condition.\nNormal mode. PWM outputs disabled by this fault are not …\nSafe mode. PWM outputs disabled by this fault are not …\nNo Combinational Path From Fault Input To PWM Output\nThere is a combinational link from the fault inputs to the …\nThe direct combinational path from the fault inputs to the …\nFault Filter Count\nFault Filter Period\nFault Glitch Stretch Enable\nFault input glitch stretching is disabled.\nInput fault signals will be stretched to at least 2 IPBus …\nFault Flags\nFiltered Fault Pins\nFull Cycle\nHalf Cycle Fault Recovery\nNo fault on the FAULTx pin.\nFault on the FAULTx pin.\nPWM outputs are not re-enabled at the start of a full cycle\nPWM outputs are re-enabled at the start of a full cycle\nPWM outputs are not re-enabled at the start of a half …\nPWM outputs are re-enabled at the start of a half cycle …\nFault Test\nNo fault\nCause a simulated fault\nPWM_A Masks\nPWM_B Masks\nPWM_X Masks\nUpdate Mask Bits Immediately\nPWM_A output normal.\nPWM_A output masked.\nPWM_B output normal.\nPWM_B output masked.\nPWM_X output normal.\nPWM_X output masked.\nNormal operation. MASK* bits within the corresponding …\nImmediate operation. MASK* bits within the corresponding …\nClear Load Okay\nCurrent Polarity\nLoad Okay\nRun\nMonitor PLL State\nNot locked. Do not monitor PLL operation. Resetting of the …\nNot locked. Monitor PLL operation to automatically disable …\nLocked. Do not monitor PLL operation. Resetting of the …\nLocked. Monitor PLL operation to automatically disable the …\nPWM23 is used to generate complementary PWM pair in the …\nPWM45 is used to generate complementary PWM pair in the …\nDo not load new values.\nLoad prescaler, modulus, and PWM values of the …\nPWM generator is disabled in the corresponding submodule.\nPWM generator is enabled in the corresponding submodule.\nPWM_A Output Enables\nPWM_B Output Enables\nPWM_X Output Enables\nPWM_A output disabled.\nPWM_A output enabled.\nPWM_B output disabled.\nPWM_B output enabled.\nPWM_X output disabled.\nPWM_X output enabled.\nSubmodule 0 Software Controlled Output 23\nSubmodule 0 Software Controlled Output 45\nSubmodule 1 Software Controlled Output 23\nSubmodule 1 Software Controlled Output 45\nSubmodule 2 Software Controlled Output 23\nSubmodule 2 Software Controlled Output 45\nSubmodule 3 Software Controlled Output 23\nSubmodule 3 Software Controlled Output 45\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nA logic 0 is supplied to the deadtime generator of …\nA logic 1 is supplied to the deadtime generator of …\nCluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, …\nCapture Compare A Register\nCapture Compare A Register\nCapture Compare B Register\nCapture Compare B Register\nCapture Compare X Register\nCapture Compare X Register\nCapture Control A Register\nCapture Control A Register\nCapture Control B Register\nCapture Control B Register\nCapture Control X Register\nCapture Control X Register\nCounter Register\nCounter Register\nControl Register\nControl Register\nControl 2 Register\nControl 2 Register\nCapture Value 0 Register\nCapture Value 0 Register\nCapture Value 0 Cycle Register\nCapture Value 0 Cycle Register\nCapture Value 1 Register\nCapture Value 1 Register\nCapture Value 1 Cycle Register\nCapture Value 1 Cycle Register\nCapture Value 2 Register\nCapture Value 2 Register\nCapture Value 2 Cycle Register\nCapture Value 2 Cycle Register\nCapture Value 3 Register\nCapture Value 3 Register\nCapture Value 3 Cycle Register\nCapture Value 3 Cycle Register\nCapture Value 4 Register\nCapture Value 4 Register\nCapture Value 4 Cycle Register\nCapture Value 4 Cycle Register\nCapture Value 5 Register\nCapture Value 5 Register\nCapture Value 5 Cycle Register\nCapture Value 5 Cycle Register\nFault Disable Mapping Register 0\nFault Disable Mapping Register 0\nFault Disable Mapping Register 1\nFault Disable Mapping Register 1\nDMA Enable Register\nDMA Enable Register\nDeadtime Count Register 0\nDeadtime Count Register 0\nDeadtime Count Register 1\nDeadtime Count Register 1\nFractional Value Register 1\nFractional Value Register 1\nFractional Value Register 2\nFractional Value Register 2\nFractional Value Register 3\nFractional Value Register 3\nFractional Value Register 4\nFractional Value Register 4\nFractional Value Register 5\nFractional Value Register 5\nFractional Control Register\nFractional Control Register\nInitial Count Register\nInitial Count Register\nInterrupt Enable Register\nInterrupt Enable Register\nOutput Control Register\nOutput Control Register\nPhase Delay Register\nPhase Delay Register\nStatus Register\nStatus Register\nOutput Trigger Control Register\nOutput Trigger Control Register\nValue Register 0\nValue Register 0\nValue Register 1\nValue Register 1\nValue Register 2\nValue Register 2\nValue Register 3\nValue Register 3\nValue Register 4\nValue Register 4\nValue Register 5\nValue Register 5\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nEdge Compare A\nEdge Counter A\nEdge Compare B\nEdge Counter B\nEdge Compare X\nEdge Counter X\nArm A\nCapture A0 FIFO Word Count\nCapture A1 FIFO Word Count\nCapture A FIFOs Water Mark\nEdge A 0\nEdge A 1\nEdge Counter A Enable\nInput Select A\nOne Shot Mode A\nInput capture operation is disabled.\nInput capture operation as specified by CAPTCTRLA[EDGAx] …\nDisabled\nCapture falling edges\nCapture rising edges\nCapture any edge\nDisabled\nCapture falling edges\nCapture rising edges\nCapture any edge\nEdge counter disabled and held in reset\nEdge counter enabled\nRaw PWM_A input signal selected as source.\nOutput of edge counter/compare selected as source. Note …\nFree running mode is selected. If both capture circuits …\nOne shot mode is selected. If both capture circuits are …\nArm B\nCapture B0 FIFO Word Count\nCapture B1 FIFO Word Count\nCapture B FIFOs Water Mark\nEdge B 0\nEdge B 1\nEdge Counter B Enable\nInput Select B\nOne Shot Mode B\nInput capture operation is disabled.\nInput capture operation as specified by CAPTCTRLB[EDGBx] …\nDisabled\nCapture falling edges\nCapture rising edges\nCapture any edge\nDisabled\nCapture falling edges\nCapture rising edges\nCapture any edge\nEdge counter disabled and held in reset\nEdge counter enabled\nRaw PWM_B input signal selected as source.\nOutput of edge counter/compare selected as source. Note …\nFree running mode is selected. If both capture circuits …\nOne shot mode is selected. If both capture circuits are …\nArm X\nCapture X FIFOs Water Mark\nCapture X0 FIFO Word Count\nCapture X1 FIFO Word Count\nEdge Counter X Enable\nEdge X 0\nEdge X 1\nInput Select X\nOne Shot Mode Aux\nInput capture operation is disabled.\nInput capture operation as specified by CAPTCTRLX[EDGXx] …\nEdge counter disabled and held in reset\nEdge counter enabled\nDisabled\nCapture falling edges\nCapture rising edges\nCapture any edge\nDisabled\nCapture falling edges\nCapture rising edges\nCapture any edge\nRaw PWM_X input signal selected as source.\nOutput of edge counter/compare selected as source. Note …\nFree running mode is selected. If both capture circuits …\nOne shot mode is selected. If both capture circuits are …\nCounter Register Bits\nCompare Mode\nDouble Switching Enable\nPWMX Double Switching Enable\nDeadtime\nFull Cycle Reload\nHalf Cycle Reload\nLoad Frequency\nLoad Mode Select\nPrescaler\nSplit the DBLPWM signal to PWMA and PWMB\nClock Source Select\nDebug Enable\nForce Initialization\nThis read/write bit determines the source of the FORCE …\nFRCEN\nIndependent or Complementary Pair Operation\nInitialization Control Select\nPWM23 Initial Value\nPWM45 Initial Value\nPWM_X Initial Value\nReload Source Select\nWAIT Enable\nThe IPBus clock is used as the clock for the local …\nEXT_CLK is used as the clock for the local prescaler and …\nSubmodule 0’s clock (AUX_CLK) is used as the source …\nThe local force signal, CTRL2[FORCE], from this submodule …\nThe master force signal from submodule 0 is used to force …\nThe local reload signal from this submodule is used to …\nThe master reload signal from submodule0 is used to force …\nThe local sync signal from this submodule is used to force …\nThe master sync signal from submodule0 is used to force …\nThe external force signal, EXT_FORCE, from outside the PWM …\nThe external sync signal, EXT_SYNC, from outside the PWM …\nInitialization from a FORCE_OUT is disabled.\nInitialization from a FORCE_OUT is enabled.\nPWM_A and PWM_B form a complementary PWM pair.\nPWM_A and PWM_B outputs are independent PWMs.\nLocal sync (PWM_X) causes initialization.\nMaster reload from submodule 0 causes initialization. This …\nMaster sync from submodule 0 causes initialization. This …\nEXT_SYNC causes initialization.\nThe local RELOAD signal is used to reload registers.\nThe master RELOAD signal (from submodule 0) is used to …\nThe VAL* registers and the PWM counter are compared using …\nThe VAL* registers and the PWM counter are compared using …\nDouble switching disabled.\nDouble switching enabled.\nPWMX double pulse disabled.\nPWMX double pulse enabled.\nFull-cycle reloads disabled.\nFull-cycle reloads enabled.\nHalf-cycle reloads disabled.\nHalf-cycle reloads enabled.\nEvery PWM opportunity\nEvery 2 PWM opportunities\nEvery 11 PWM opportunities\nEvery 12 PWM opportunities\nEvery 13 PWM opportunities\nEvery 14 PWM opportunities\nEvery 15 PWM opportunities\nEvery 16 PWM opportunities\nEvery 3 PWM opportunities\nEvery 4 PWM opportunities\nEvery 5 PWM opportunities\nEvery 6 PWM opportunities\nEvery 7 PWM opportunities\nEvery 8 PWM opportunities\nEvery 9 PWM opportunities\nEvery 10 PWM opportunities\nBuffered registers of this submodule are loaded and take …\nBuffered registers of this submodule are loaded and take …\nPWM clock frequency = fclk\nPWM clock frequency = fclk/2\nPWM clock frequency = fclk/4\nPWM clock frequency = fclk/8\nPWM clock frequency = fclk/16\nPWM clock frequency = fclk/32\nPWM clock frequency = fclk/64\nPWM clock frequency = fclk/128\nDBLPWM is not split. PWMA and PWMB each have double pulses.\nDBLPWM is split to PWMA and PWMB.\nCAPTVAL0\nCVAL0CYC\nCAPTVAL1\nCVAL1CYC\nCAPTVAL2\nCVAL2CYC\nCAPTVAL3\nCVAL3CYC\nCAPTVAL4\nCVAL4CYC\nCAPTVAL5\nCVAL5CYC\nPWM_A Fault Disable Mask 0\nPWM_B Fault Disable Mask 0\nPWM_X Fault Disable Mask 0\nPWM_A Fault Disable Mask 1\nPWM_B Fault Disable Mask 1\nPWM_X Fault Disable Mask 1\nCapture A0 FIFO DMA Enable\nCapture A1 FIFO DMA Enable\nCapture DMA Enable Source Select\nCapture B0 FIFO DMA Enable\nCapture B1 FIFO DMA Enable\nCapture X0 FIFO DMA Enable\nCapture X1 FIFO DMA Enable\nFIFO Watermark AND Control\nValue Registers DMA Enable\nRead DMA requests disabled.\nExceeding a FIFO watermark sets the DMA read request. This …\nA local sync (VAL1 matches counter) sets the read DMA …\nA local reload (STS[RF] being set) sets the read DMA …\nSelected FIFO watermarks are OR’ed together.\nSelected FIFO watermarks are AND’ed together.\nDMA write requests disabled\nDMA write requests for the VALx and FRACVALx registers …\nDTCNT0\nDTCNT1\nFractional Value 1 Register\nFractional Value 2\nFractional Value 3\nFractional Value 4\nFractional Value 5\nFractional Cycle PWM Period Enable\nFractional Cycle Placement Enable for PWM_A\nFractional Cycle Placement Enable for PWM_B\nFractional Delay Circuit Power Up\nTest Status Bit\nDisable fractional cycle length for the PWM period.\nEnable fractional cycle length for the PWM period.\nDisable fractional cycle placement for PWM_A.\nEnable fractional cycle placement for PWM_A.\nDisable fractional cycle placement for PWM_B.\nEnable fractional cycle placement for PWM_B.\nTurn off fractional delay logic.\nPower up fractional delay logic.\nInitial Count Register Bits\nCapture A 0 Interrupt Enable\nCapture A 1 Interrupt Enable\nCapture B 0 Interrupt Enable\nCapture B 1 Interrupt Enable\nCompare Interrupt Enables\nCapture X 0 Interrupt Enable\nCapture X 1 Interrupt Enable\nReload Error Interrupt Enable\nReload Interrupt Enable\nInterrupt request disabled for STS[CFA0].\nInterrupt request enabled for STS[CFA0].\nInterrupt request disabled for STS[CFA1].\nInterrupt request enabled for STS[CFA1].\nInterrupt request disabled for STS[CFB0].\nInterrupt request enabled for STS[CFB0].\nInterrupt request disabled for STS[CFB1].\nInterrupt request enabled for STS[CFB1].\nThe corresponding STS[CMPF] bit will not cause an …\nThe corresponding STS[CMPF] bit will cause an interrupt …\nInterrupt request disabled for STS[CFX0].\nInterrupt request enabled for STS[CFX0].\nInterrupt request disabled for STS[CFX1].\nInterrupt request enabled for STS[CFX1].\nSTS[REF] CPU interrupt requests disabled\nSTS[REF] CPU interrupt requests enabled\nSTS[RF] CPU interrupt requests disabled\nSTS[RF] CPU interrupt requests enabled\nPWM_A Output Polarity\nPWM_B Output Polarity\nPWM_X Output Polarity\nPWM_A Fault State\nPWM_A Input\nPWM_B Fault State\nPWM_B Input\nPWM_X Fault State\nPWM_X Input\nPWM_A output not inverted. A high level on the PWM_A pin …\nPWM_A output inverted. A low level on the PWM_A pin …\nPWM_B output not inverted. A high level on the PWM_B pin …\nPWM_B output inverted. A low level on the PWM_B pin …\nPWM_X output not inverted. A high level on the PWM_X pin …\nPWM_X output inverted. A low level on the PWM_X pin …\nOutput is forced to logic 0 state prior to consideration …\nOutput is forced to logic 1 state prior to consideration …\nOutput is tristated.\nOutput is tristated.\nOutput is forced to logic 0 state prior to consideration …\nOutput is forced to logic 1 state prior to consideration …\nOutput is tristated.\nOutput is tristated.\nOutput is forced to logic 0 state prior to consideration …\nOutput is forced to logic 1 state prior to consideration …\nOutput is tristated.\nOutput is tristated.\nInitial Count Register Bits\nCapture Flag A0\nCapture Flag A1\nCapture Flag B0\nCapture Flag B1\nCapture Flag X0\nCapture Flag X1\nCompare Flags\nReload Error Flag\nReload Flag\nRegisters Updated Flag\nNo compare event has occurred for a particular VALx value.\nA compare event has occurred for a particular VALx value.\nNo reload error occurred.\nReload signal occurred with non-coherent data and MCTRL…\nNo new reload cycle since last STS[RF] clearing\nNew reload cycle since last STS[RF] clearing\nNo register update has occurred since last reload.\nAt least one of the double buffered registers has been …\nOutput Trigger Enables\nOutput Trigger 0 Source Select\nOutput Trigger 1 Source Select\nTrigger frequency\nPWM_OUT_TRIGx will not set when the counter value matches …\nPWM_OUT_TRIGx will set when the counter value matches the …\nRoute the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.\nRoute the PWMA output to the PWM_OUT_TRIG0 port.\nRoute the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.\nRoute the PWMB output to the PWM_OUT_TRIG1 port.\nTrigger outputs are generated during every PWM period even …\nTrigger outputs are generated only during the final PWM …\nValue Register 0\nValue Register 1\nValue Register 2\nValue Register 3\nValue Register 4\nValue Register 5\nROMC\nROMC Address Registers\nROMC Address Registers\nROMC Control Register\nROMC Control Register\nROMC Data Registers\nROMC Data Registers\nROMC Enable Register High\nROMC Enable Register Low\nROMC Enable Register Low\nROMC Status Register\nROMC Status Register\nROMC\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nAddress Comparator Registers - Indicates the memory …\nTHUMB Comparator Select - Indicates that this address will …\nArm patch\nTHUMB patch (ignore if data fix)\nData Fix Enable - Controls the use of the first 8 address …\nROMC Disable – This bit, when set, disables all ROMC …\nAddress comparator triggers a opcode patch\nAddress comparator triggers a data fix\nDoes not affect any ROMC functions (default)\nDisable all ROMC functions: data fixing, and opcode …\nData Fix Registers - Stores the data used for 1-word data …\nEnable Address Comparator - This bit enables the …\nAddress comparator disabled\nAddress comparator enabled, ROMC will trigger a opcode …\nROMC Source Number - Binary encoding of the number of the …\nROMC AHB Multiple Address Comparator matches Indicator - …\nAddress Comparator 0 matched\nAddress Comparator 1 matched\nAddress Comparator 15 matched\nno event or comparator collisions\na collision has occurred\nWatchdog Counter Register\nWatchdog Counter Register\nWatchdog Control and Status Register\nWatchdog Control and Status Register\nWDOG\nWDOG\nWatchdog Timeout Value Register\nWatchdog Timeout Value Register\nWatchdog Window Register\nWatchdog Window Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nHigh byte of the Watchdog Counter\nLow byte of the Watchdog Counter\nWatchdog Clock\nEnables or disables WDOG support for 32-bit (otherwise …\nDebug Enable\nWatchdog Enable\nWatchdog Interrupt Flag\nWatchdog Interrupt\nWatchdog prescaler\nReconfiguration Success\nStop Enable\nWatchdog Test\nUnlock status\nAllow updates\nWait Enable\nWatchdog Window\nBus clock\nLPO clock\nINTCLK (internal clock)\nERCLK (external reference clock)\nDisables support for 32-bit refresh/unlock command write …\nEnables support for 32-bit refresh/unlock command write …\nWatchdog disabled in chip debug mode.\nWatchdog enabled in chip debug mode.\nWatchdog disabled.\nWatchdog enabled.\nNo interrupt occurred.\nAn interrupt occurred.\nWatchdog interrupts are disabled. Watchdog resets are not …\nWatchdog interrupts are enabled. Watchdog resets are …\n256 prescaler disabled.\n256 prescaler enabled.\nReconfiguring WDOG.\nReconfiguration is successful.\nWatchdog disabled in chip stop mode.\nWatchdog enabled in chip stop mode.\nWatchdog test mode disabled.\nWatchdog user mode enabled. (Watchdog test mode disabled.) …\nWatchdog test mode enabled, only the low byte is used. CNT…\nWatchdog test mode enabled, only the high byte is used. CNT…\nWDOG is locked.\nWDOG is unlocked.\nUpdates not allowed. After the initial configuration, the …\nUpdates allowed. Software can modify the watchdog …\nWatchdog disabled in chip wait mode.\nWatchdog enabled in chip wait mode.\nWindow mode disabled.\nWindow mode enabled.\nHigh byte of the timeout value\nLow byte of the timeout value\nHigh byte of Watchdog Window\nLow byte of Watchdog Window\nParameter Register\nParameter Register\nSAI Receive Configuration 1 Register\nSAI Receive Configuration 1 Register\nSAI Receive Configuration 2 Register\nSAI Receive Configuration 2 Register\nSAI Receive Configuration 3 Register\nSAI Receive Configuration 3 Register\nSAI Receive Configuration 4 Register\nSAI Receive Configuration 4 Register\nSAI Receive Configuration 5 Register\nSAI Receive Configuration 5 Register\nSAI Receive Control Register\nSAI Receive Control Register\nSAI Receive Data Register\nSAI Receive Data Register\nSAI Receive FIFO Register\nSAI Receive FIFO Register\nSAI Receive Mask Register\nSAI Receive Mask Register\nI2S\nI2S\nI2S\nSAI Transmit Configuration 1 Register\nSAI Transmit Configuration 1 Register\nSAI Transmit Configuration 2 Register\nSAI Transmit Configuration 2 Register\nSAI Transmit Configuration 3 Register\nSAI Transmit Configuration 3 Register\nSAI Transmit Configuration 4 Register\nSAI Transmit Configuration 4 Register\nSAI Transmit Configuration 5 Register\nSAI Transmit Configuration 5 Register\nSAI Transmit Control Register\nSAI Transmit Control Register\nSAI Transmit Data Register\nSAI Transmit Data Register\nSAI Transmit FIFO Register\nSAI Transmit FIFO Register\nSAI Transmit Mask Register\nSAI Transmit Mask Register\nVersion ID Register\nVersion ID Register\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nNumber of Datalines\nFIFO Size\nFrame Size\nReceive FIFO Watermark\nBit Clock Direction\nBit Clock Input\nBit Clock Polarity\nBit Clock Swap\nBit Clock Divide\nMCLK Select\nSynchronous Mode\nBit clock is generated externally in Slave mode.\nBit clock is generated internally in Master mode.\nNo effect.\nInternal logic is clocked as if bit clock was externally …\nBit Clock is active high with drive outputs on rising edge …\nBit Clock is active low with drive outputs on falling edge …\nUse the normal bit clock source.\nSwap the bit clock source.\nBus Clock selected.\nMaster Clock (MCLK) 1 option selected.\nMaster Clock (MCLK) 2 option selected.\nMaster Clock (MCLK) 3 option selected.\nAsynchronous mode.\nSynchronous with transmitter.\nChannel FIFO Reset\nReceive Channel Enable\nWord Flag Configuration\nFIFO Combine Mode\nFIFO Continue on Error\nFIFO Packing Mode\nFrame Size\nFrame Sync Direction\nFrame Sync Early\nFrame Sync Polarity\nMSB First\nOn Demand Mode\nSync Width\nFIFO combine mode disabled.\nFIFO combine mode enabled on FIFO writes (from receive …\nFIFO combine mode enabled on FIFO reads (by software).\nFIFO combine mode enabled on FIFO writes (from receive …\nOn FIFO error, the SAI will continue from the start of the …\nOn FIFO error, the SAI will continue from the same word …\nFIFO packing is disabled\n8-bit FIFO packing is enabled\n16-bit FIFO packing is enabled\nFrame Sync is generated externally in Slave mode.\nFrame Sync is generated internally in Master mode.\nFrame sync asserts with the first bit of the frame.\nFrame sync asserts one bit before the first bit of the …\nFrame sync is active high.\nFrame sync is active low.\nLSB is received first.\nMSB is received first.\nInternal frame sync is generated continuously.\nInternal frame sync is generated when the FIFO warning …\nFirst Bit Shifted\nWord 0 Width\nWord N Width\nBit Clock Enable\nDebug Enable\nFIFO Error Flag\nFIFO Error Interrupt Enable\nFIFO Reset\nFIFO Request DMA Enable\nFIFO Request Flag\nFIFO Request Interrupt Enable\nFIFO Warning DMA Enable\nFIFO Warning Flag\nFIFO Warning Interrupt Enable\nReceiver Enable\nSync Error Flag\nSync Error Interrupt Enable\nSoftware Reset\nStop Enable\nWord Start Flag\nWord Start Interrupt Enable\nReceive bit clock is disabled.\nReceive bit clock is enabled.\nReceiver is disabled in Debug mode, after completing the …\nReceiver is enabled in Debug mode.\nReceive overflow not detected.\nReceive overflow detected.\nDisables the interrupt.\nEnables the interrupt.\nNo effect.\nFIFO reset.\nDisables the DMA request.\nEnables the DMA request.\nReceive FIFO watermark not reached.\nReceive FIFO watermark has been reached.\nDisables the interrupt.\nEnables the interrupt.\nDisables the DMA request.\nEnables the DMA request.\nNo enabled receive FIFO is full.\nEnabled receive FIFO is full.\nDisables the interrupt.\nEnables the interrupt.\nReceiver is disabled.\nReceiver is enabled, or receiver has been disabled and has …\nSync error not detected.\nFrame sync error detected.\nDisables interrupt.\nEnables interrupt.\nNo effect.\nSoftware reset.\nReceiver disabled in Stop mode.\nReceiver enabled in Stop mode.\nStart of word not detected.\nStart of word detected.\nDisables interrupt.\nEnables interrupt.\nReceive Data Register\nReceive Channel Pointer\nRead FIFO Pointer\nWrite FIFO Pointer\nNo effect.\nFIFO combine is enabled for FIFO reads and this FIFO will …\nReceive Word Mask\nWord N is enabled.\nWord N is masked.\nTransmit FIFO Watermark\nBit Clock Direction\nBit Clock Input\nBit Clock Polarity\nBit Clock Swap\nBit Clock Divide\nMCLK Select\nSynchronous Mode\nBit clock is generated externally in Slave mode.\nBit clock is generated internally in Master mode.\nNo effect.\nInternal logic is clocked as if bit clock was externally …\nBit clock is active high with drive outputs on rising edge …\nBit clock is active low with drive outputs on falling edge …\nUse the normal bit clock source.\nSwap the bit clock source.\nBus Clock selected.\nMaster Clock (MCLK) 1 option selected.\nMaster Clock (MCLK) 2 option selected.\nMaster Clock (MCLK) 3 option selected.\nAsynchronous mode.\nSynchronous with receiver.\nChannel FIFO Reset\nTransmit Channel Enable\nWord Flag Configuration\nChannel Mode\nFIFO Combine Mode\nFIFO Continue on Error\nFIFO Packing Mode\nFrame size\nFrame Sync Direction\nFrame Sync Early\nFrame Sync Polarity\nMSB First\nOn Demand Mode\nSync Width\nTDM mode, transmit data pins are tri-stated when slots are …\nOutput mode, transmit data pins are never tri-stated and …\nFIFO combine mode disabled.\nFIFO combine mode enabled on FIFO reads (from transmit …\nFIFO combine mode enabled on FIFO writes (by software).\nFIFO combine mode enabled on FIFO reads (from transmit …\nOn FIFO error, the SAI will continue from the start of the …\nOn FIFO error, the SAI will continue from the same word …\nFIFO packing is disabled\n8-bit FIFO packing is enabled\n16-bit FIFO packing is enabled\nFrame sync is generated externally in Slave mode.\nFrame sync is generated internally in Master mode.\nFrame sync asserts with the first bit of the frame.\nFrame sync asserts one bit before the first bit of the …\nFrame sync is active high.\nFrame sync is active low.\nLSB is transmitted first.\nMSB is transmitted first.\nInternal frame sync is generated continuously.\nInternal frame sync is generated when the FIFO warning …\nFirst Bit Shifted\nWord 0 Width\nWord N Width\nBit Clock Enable\nDebug Enable\nFIFO Error Flag\nFIFO Error Interrupt Enable\nFIFO Reset\nFIFO Request DMA Enable\nFIFO Request Flag\nFIFO Request Interrupt Enable\nFIFO Warning DMA Enable\nFIFO Warning Flag\nFIFO Warning Interrupt Enable\nSync Error Flag\nSync Error Interrupt Enable\nSoftware Reset\nStop Enable\nTransmitter Enable\nWord Start Flag\nWord Start Interrupt Enable\nTransmit bit clock is disabled.\nTransmit bit clock is enabled.\nTransmitter is disabled in Debug mode, after completing …\nTransmitter is enabled in Debug mode.\nTransmit underrun not detected.\nTransmit underrun detected.\nDisables the interrupt.\nEnables the interrupt.\nNo effect.\nFIFO reset.\nDisables the DMA request.\nEnables the DMA request.\nTransmit FIFO watermark has not been reached.\nTransmit FIFO watermark has been reached.\nDisables the interrupt.\nEnables the interrupt.\nDisables the DMA request.\nEnables the DMA request.\nNo enabled transmit FIFO is empty.\nEnabled transmit FIFO is empty.\nDisables the interrupt.\nEnables the interrupt.\nSync error not detected.\nFrame sync error detected.\nDisables interrupt.\nEnables interrupt.\nNo effect.\nSoftware reset.\nTransmitter disabled in Stop mode.\nTransmitter enabled in Stop mode.\nTransmitter is disabled.\nTransmitter is enabled, or transmitter has been disabled …\nStart of word not detected.\nStart of word detected.\nDisables interrupt.\nEnables interrupt.\nTransmit Data Register\nRead FIFO Pointer\nWrite Channel Pointer\nWrite FIFO Pointer\nNo effect.\nFIFO combine is enabled for FIFO writes and this FIFO will …\nTransmit Word Mask\nWord N is enabled.\nWord N is masked. The transmit data pins are tri-stated or …\nFeature Specification Number\nMajor Version Number\nMinor Version Number\nStandard feature set.\nSNVS_HP Command Register\nSNVS_HP Command Register\nSNVS_HP Control Register\nSNVS_HP Control Register\nSNVS_HP High Assurance Counter IV Register\nSNVS_HP High Assurance Counter IV Register\nSNVS_HP High Assurance Counter Register\nSNVS_HP High Assurance Counter Register\nSNVS_HP Lock Register\nSNVS_HP Lock Register\nSNVS_HP Real Time Counter LSB Register\nSNVS_HP Real Time Counter LSB Register\nSNVS_HP Real Time Counter MSB Register\nSNVS_HP Real Time Counter MSB Register\nSNVS_HP Security Interrupt Control Register\nSNVS_HP Security Interrupt Control Register\nSNVS_HP Status Register\nSNVS_HP Status Register\nSNVS_HP Security Violation Control Register\nSNVS_HP Security Violation Control Register\nSNVS_HP Security Violation Status Register\nSNVS_HP Security Violation Status Register\nSNVS_HP Time Alarm LSB Register\nSNVS_HP Time Alarm LSB Register\nSNVS_HP Time Alarm MSB Register\nSNVS_HP Time Alarm MSB Register\nSNVS_HP Version ID Register 1\nSNVS_HP Version ID Register 1\nSNVS_HP Version ID Register 2\nSNVS_HP Version ID Register 2\nSNVS_LP Control Register\nSNVS_LP Control Register\nSNVS_LP General Purpose Registers 0 .. 3\nSNVS_LP General Purpose Registers 0 .. 3\nSNVS_LP General Purpose Register 0 (legacy alias)\nSNVS_LP General Purpose Register 0 (legacy alias)\nSNVS_LP General Purpose Registers 0 .. 3\nSNVS_LP General Purpose Registers 0 .. 3\nSNVS_LP Lock Register\nSNVS_LP Lock Register\nSNVS_LP Master Key Control Register\nSNVS_LP Master Key Control Register\nSNVS_LP Power Glitch Detector Register\nSNVS_LP Power Glitch Detector Register\nSNVS_LP Secure Monotonic Counter LSB Register\nSNVS_LP Secure Monotonic Counter LSB Register\nSNVS_LP Secure Monotonic Counter MSB Register\nSNVS_LP Secure Monotonic Counter MSB Register\nSNVS_LP Status Register\nSNVS_LP Status Register\nSNVS_LP Secure Real Time Counter LSB Register\nSNVS_LP Secure Real Time Counter LSB Register\nSNVS_LP Secure Real Time Counter MSB Register\nSNVS_LP Secure Real Time Counter MSB Register\nSNVS_LP Security Violation Control Register\nSNVS_LP Security Violation Control Register\nSNVS_LP Time Alarm Register\nSNVS_LP Time Alarm Register\nSNVS_LP Tamper Detectors Configuration Register\nSNVS_LP Tamper Detectors Configuration Register\nSNVS_LP Zeroizable Master Key Register\nSNVS_LP Zeroizable Master Key Register\nSNVS\nSNVS\nReturns the argument unchanged.\nAcquire a vaild, but possibly aliased, instance.\nCalls <code>U::from(self)</code>.\nReturns the instance number <code>N</code> for a peripheral instance.\nHigh Assurance Counter Clear When set, it clears the High …\nHigh Assurance Counter Enable This bit controls the SSM …\nHigh Assurance Counter Load When set, it loads the High …\nHigh Assurance Counter Stop This bit can be set only when …\nLP Software Reset When set to 1, most registers in the …\nLP Software Reset Disable When set, disables the LP …\nMaster Key Select Enable When not set, the one time …\nNon-Privileged Software Access Enable When set, allows …\nProgram Zeroizable Master Key This bit activates ZMK …\nSSM Soft Fail to Non-Secure State Transition Disable When …\nSSM State Transition Transition state of the system …\nSSM Secure to Trusted State Transition Disable When set, …\nSoftware Fatal Security Violation When set, the system …\nLP Software Security Violation When set, SNVS_LP treats …\nSoftware Security Violation When set, the system security …\nNo Action\nClear the HAC\nHigh Assurance Counter is disabled\nHigh Assurance Counter is enabled\nNo Action\nLoad the HAC\nNo Action\nReset LP section\nLP software reset is enabled\nLP software reset is disabled\nOTP master key is selected as an SNVS master key\nSNVS master key is selected according to the setting of …\nNo Action\nActivate hardware key programming mechanism\nSoft Fail to Non-Secure State transition is enabled\nSoft Fail to Non-Secure State transition is disabled\nSecure to Trusted State transition is enabled\nSecure to Trusted State transition is disabled\nButton Configuration\nButton interrupt mask\nDisable periodic interrupt in the functional interrupt\nHP Real Time Counter Calibration Enabled Indicates that …\nHP Calibration Value Defines signed calibration value for …\nHP Time Alarm Enable When set, the time alarm interrupt is …\nHP Time Synchronize\nHP Periodic Interrupt Enable The periodic interrupt can be …\nPeriodic Interrupt Frequency Defines frequency of the …\nHP Real Time Counter Enable\nPeriodic interrupt will trigger a functional interrupt\nDisable periodic interrupt in the function interrupt\nHP Timer calibration disabled\nHP Timer calibration enabled\n+0 counts per each 32768 ticks of the counter\n+1 counts per each 32768 ticks of the counter\n+15 counts per each 32768 ticks of the counter\n-16 counts per each 32768 ticks of the counter\n-15 counts per each 32768 ticks of the counter\n+2 counts per each 32768 ticks of the counter\n-2 counts per each 32768 ticks of the counter\n-1 counts per each 32768 ticks of the counter\nHP Time Alarm Interrupt is disabled\nHP Time Alarm Interrupt is enabled\nNo Action\nSynchronize the HP Time Counter to the LP Time Counter\nHP Periodic Interrupt is disabled\nHP Periodic Interrupt is enabled\nbit 0 of the HPRTCLR is selected as a source of the …\nbit 1 of the HPRTCLR is selected as a source of the …\nbit 10 of the HPRTCLR is selected as a source of the …\nbit 11 of the HPRTCLR is selected as a source of the …\nbit 12 of the HPRTCLR is selected as a source of the …\nbit 13 of the HPRTCLR is selected as a source of the …\nbit 14 of the HPRTCLR is selected as a source of the …\nbit 15 of the HPRTCLR is selected as a source of the …\nbit 2 of the HPRTCLR is selected as a source of the …\nbit 3 of the HPRTCLR is selected as a source of the …\nbit 4 of the HPRTCLR is selected as a source of the …\nbit 5 of the HPRTCLR is selected as a source of the …\nbit 6 of the HPRTCLR is selected as a source of the …\nbit 7 of the HPRTCLR is selected as a source of the …\nbit 8 of the HPRTCLR is selected as a source of the …\nbit 9 of the HPRTCLR is selected as a source of the …\nRTC is disabled\nRTC is enabled\nHigh Assurance Counter Initial Value This register is used …\nHigh Assurance Counter When the HAC_EN bit is set and the …\nGeneral Purpose Register Soft Lock When set, prevents any …\nHigh Assurance Counter Lock When set, prevents any writes …\nHP Security Interrupt Control Register Lock When set, …\nHP Security Violation Control Register Lock When set, …\nLP Calibration Soft Lock When set, prevents any writes to …\nLP Security Violation Control Register Soft Lock When set, …\nLP Tamper Detectors Configuration Register Soft Lock When …\nMonotonic Counter Soft Lock When set, prevents any writes …\nMaster Key Select Soft Lock When set, prevents any writes …\nSecure Real Time Counter Soft Lock When set, prevents any …\nZeroizable Master Key Read Soft Lock When set, prevents …\nZeroizable Master Key Write Soft Lock When set, prevents …\nWrite access is allowed\nWrite access is not allowed\nWrite access is allowed\nWrite access is not allowed\nWrite access is allowed\nWrite access is not allowed\nWrite access is allowed\nWrite access is not allowed\nWrite access is allowed\nWrite access is not allowed\nWrite access is allowed\nWrite access is not allowed\nWrite access is allowed\nWrite access is not allowed\nWrite access (increment) is allowed\nWrite access (increment) is not allowed\nWrite access is allowed\nWrite access is not allowed\nWrite access is allowed\nWrite access is not allowed\nRead access is allowed (only in software Programming mode)\nRead access is not allowed\nWrite access is allowed\nWrite access is not allowed\nHP Real Time Counter least-significant 32 bits\nHP Real Time Counter The most-significant 15 bits of the …\nLP Security Violation Interrupt Enable This bit enables …\nSecurity Violation 0 Interrupt Enable Setting this bit to …\nSecurity Violation 1 Interrupt Enable Setting this bit to …\nSecurity Violation 2 Interrupt Enable Setting this bit to …\nSecurity Violation 3 Interrupt Enable Setting this bit to …\nSecurity Violation 4 Interrupt Enable Setting this bit to …\nSecurity Violation 5 Interrupt Enable Setting this bit to …\nLP Security Violation Interrupt is Disabled\nLP Security Violation Interrupt is Enabled\nSecurity Violation 0 Interrupt is Disabled\nSecurity Violation 0 Interrupt is Enabled\nSecurity Violation 1 Interrupt is Disabled\nSecurity Violation 1 Interrupt is Enabled\nSecurity Violation 2 Interrupt is Disabled\nSecurity Violation 2 Interrupt is Enabled\nSecurity Violation 3 Interrupt is Disabled\nSecurity Violation 3 Interrupt is Enabled\nSecurity Violation 4 Interrupt is Disabled\nSecurity Violation 4 Interrupt is Enabled\nSecurity Violation 5 Interrupt is Disabled\nSecurity Violation 5 Interrupt is Enabled\nButton Interrupt Signal ipi_snvs_btn_int_b was asserted.\nButton Value of the BTN input\nHP Time Alarm Indicates that the HP Time Alarm has …\nLow Power Disable If 1, the low power section has been …\nOne Time Programmable Master Key Syndrome In the case of a …\nOne Time Programmable Master Key is Equal to Zero\nPeriodic Interrupt Indicates that periodic interrupt has …\nSecurity Configuration This field reflects the settings of …\nSystem Security Monitor State This field contains the …\nZeroizable Master Key is Equal to Zero\nNo time alarm interrupt occurred.\nA time alarm interrupt occurred.\nThe OTPMK is not zero.\nThe OTPMK is zero.\nNo periodic interrupt occurred.\nA periodic interrupt occurred.\nCLOSED Configuration\nFAB Configuration\nOPEN Configuration\nInit\nHard Fail\nNon-Secure\nTrusted\nSecure\nSoft Fail\nInit Intermediate (transition state between Init and Check …\nCheck\nThe ZMK is not zero.\nThe ZMK is zero.\nLP Security Violation Configuration This field configures …\nSecurity Violation 0 Security Violation Configuration This …\nSecurity Violation 1 Security Violation Configuration This …\nSecurity Violation 2 Security Violation Configuration This …\nSecurity Violation 3 Security Violation Configuration This …\nSecurity Violation 4 Security Violation Configuration This …\nSecurity Violation 5 Security Violation Configuration This …\nLP security violation is disabled\nLP security violation is a non-fatal violation\nLP security violation is a fatal violation\nSecurity Violation 0 is a non-fatal violation\nSecurity Violation 0 is a fatal violation\nSecurity Violation 1 is a non-fatal violation\nSecurity Violation 1 is a fatal violation\nSecurity Violation 2 is a non-fatal violation\nSecurity Violation 2 is a fatal violation\nSecurity Violation 3 is a non-fatal violation\nSecurity Violation 3 is a fatal violation\nSecurity Violation 4 is a non-fatal violation\nSecurity Violation 4 is a fatal violation\nSecurity Violation 5 is disabled\nSecurity Violation 5 is a non-fatal violation\nSecurity Violation 5 is a fatal violation\nLP Security Violation A security volation was detected in …\nSecurity Violation 0 security violation was detected.\nSecurity Violation 1 security violation was detected.\nSecurity Violation 2 security violation was detected.\nSecurity Violation 3 security violation was detected.\nSecurity Violation 4 security violation was detected.\nSecurity Violation 5 security violation was detected.\nSoftware Fatal Security Violation This bit is a read-only …\nLP Software Security Violation This bit is a read-only …\nSoftware Security Violation This bit is a read-only copy …\nZeroizable Master Key Error Correcting Code Check Failure …\nZeroizable Master Key Syndrome The ZMK syndrome indicates …\nNo Security Violation 0 security violation was detected.\nSecurity Violation 0 security violation was detected.\nNo Security Violation 1 security violation was detected.\nSecurity Violation 1 security violation was detected.\nNo Security Violation 2 security violation was detected.\nSecurity Violation 2 security violation was detected.\nNo Security Violation 3 security violation was detected.\nSecurity Violation 3 security violation was detected.\nNo Security Violation 4 security violation was detected.\nSecurity Violation 4 security violation was detected.\nNo Security Violation 5 security violation was detected.\nSecurity Violation 5 security violation was detected.\nZMK ECC Failure was not detected.\nZMK ECC Failure was detected.\nHP Time Alarm, 32 least-significant bits\nHP Time Alarm, most-significant 15 bits\nSNVS block ID\nSNVS block major version number\nSNVS block minor version number\nSNVS Configuration Options\nSNVS ECO Revision\nSNVS Integration Options\nIP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5\nThis field configures the button press time out values for …\nThis field configures the amount of debounce time for the …\nDumb PMIC Enabled When set, software can control the …\nGeneral Purpose Registers Zeroization Disable\nLP Calibration Enable When set, enables the SRTC …\nLP Calibration Value Defines signed calibration value for …\nLP Time Alarm Enable When set, the SNVS functional …\nLP Wake-Up Interrupt Enable This interrupt line should be …\nMonotonic Counter Enabled and Valid When set, the MC can …\nThe ON_TIME field is used to configure the period of time …")