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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="DMA with separate read and write masters"><title>rp2040_pac::dma - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module dma</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#reexports">Re-exports</a></li><li><a href="#modules">Modules</a></li><li><a href="#structs">Structs</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../index.html">rp2040_pac</a>::<wbr><a class="mod" href="#">dma</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../src/rp2040_pac/dma.rs.html#1-668">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>DMA with separate read and write masters</p>
</div></details><h2 id="reexports" class="section-header">Re-exports<a href="#reexports" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name" id="reexport.CH"><code>pub use self::ch::<a class="struct" href="ch/struct.CH.html" title="struct rp2040_pac::dma::ch::CH">CH</a>;</code></div></li></ul><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="ch/index.html" title="mod rp2040_pac::dma::ch">ch</a></div><div class="desc docblock-short">Cluster
Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG</div></li><li><div class="item-name"><a class="mod" href="ch0_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch0_dbg_ctdreq">ch0_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch0_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch0_dbg_tcr">ch0_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch1_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch1_dbg_ctdreq">ch1_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch1_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch1_dbg_tcr">ch1_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch2_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch2_dbg_ctdreq">ch2_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch2_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch2_dbg_tcr">ch2_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch3_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch3_dbg_ctdreq">ch3_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch3_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch3_dbg_tcr">ch3_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch4_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch4_dbg_ctdreq">ch4_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch4_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch4_dbg_tcr">ch4_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch5_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch5_dbg_ctdreq">ch5_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch5_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch5_dbg_tcr">ch5_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch6_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch6_dbg_ctdreq">ch6_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch6_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch6_dbg_tcr">ch6_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch7_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch7_dbg_ctdreq">ch7_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch7_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch7_dbg_tcr">ch7_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch8_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch8_dbg_ctdreq">ch8_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch8_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch8_dbg_tcr">ch8_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch9_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch9_dbg_ctdreq">ch9_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch9_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch9_dbg_tcr">ch9_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch10_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch10_dbg_ctdreq">ch10_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch10_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch10_dbg_tcr">ch10_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="ch11_dbg_ctdreq/index.html" title="mod rp2040_pac::dma::ch11_dbg_ctdreq">ch11_<wbr>dbg_<wbr>ctdreq</a></div><div class="desc docblock-short">Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="mod" href="ch11_dbg_tcr/index.html" title="mod rp2040_pac::dma::ch11_dbg_tcr">ch11_<wbr>dbg_<wbr>tcr</a></div><div class="desc docblock-short">Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="mod" href="chan_abort/index.html" title="mod rp2040_pac::dma::chan_abort">chan_<wbr>abort</a></div><div class="desc docblock-short">Abort an in-progress transfer sequence on one or more channels</div></li><li><div class="item-name"><a class="mod" href="fifo_levels/index.html" title="mod rp2040_pac::dma::fifo_levels">fifo_<wbr>levels</a></div><div class="desc docblock-short">Debug RAF, WAF, TDF levels</div></li><li><div class="item-name"><a class="mod" href="inte0/index.html" title="mod rp2040_pac::dma::inte0">inte0</a></div><div class="desc docblock-short">Interrupt Enables for IRQ 0</div></li><li><div class="item-name"><a class="mod" href="inte1/index.html" title="mod rp2040_pac::dma::inte1">inte1</a></div><div class="desc docblock-short">Interrupt Enables for IRQ 1</div></li><li><div class="item-name"><a class="mod" href="intf0/index.html" title="mod rp2040_pac::dma::intf0">intf0</a></div><div class="desc docblock-short">Force Interrupts</div></li><li><div class="item-name"><a class="mod" href="intf1/index.html" title="mod rp2040_pac::dma::intf1">intf1</a></div><div class="desc docblock-short">Force Interrupts for IRQ 1</div></li><li><div class="item-name"><a class="mod" href="intr/index.html" title="mod rp2040_pac::dma::intr">intr</a></div><div class="desc docblock-short">Interrupt Status (raw)</div></li><li><div class="item-name"><a class="mod" href="ints0/index.html" title="mod rp2040_pac::dma::ints0">ints0</a></div><div class="desc docblock-short">Interrupt Status for IRQ 0</div></li><li><div class="item-name"><a class="mod" href="ints1/index.html" title="mod rp2040_pac::dma::ints1">ints1</a></div><div class="desc docblock-short">Interrupt Status (masked) for IRQ 1</div></li><li><div class="item-name"><a class="mod" href="multi_chan_trigger/index.html" title="mod rp2040_pac::dma::multi_chan_trigger">multi_<wbr>chan_<wbr>trigger</a></div><div class="desc docblock-short">Trigger one or more channels simultaneously</div></li><li><div class="item-name"><a class="mod" href="n_channels/index.html" title="mod rp2040_pac::dma::n_channels">n_<wbr>channels</a></div><div class="desc docblock-short">The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.</div></li><li><div class="item-name"><a class="mod" href="sniff_ctrl/index.html" title="mod rp2040_pac::dma::sniff_ctrl">sniff_<wbr>ctrl</a></div><div class="desc docblock-short">Sniffer Control</div></li><li><div class="item-name"><a class="mod" href="sniff_data/index.html" title="mod rp2040_pac::dma::sniff_data">sniff_<wbr>data</a></div><div class="desc docblock-short">Data accumulator for sniff hardware<br />
Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</div></li><li><div class="item-name"><a class="mod" href="timer0/index.html" title="mod rp2040_pac::dma::timer0">timer0</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="mod" href="timer1/index.html" title="mod rp2040_pac::dma::timer1">timer1</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="mod" href="timer2/index.html" title="mod rp2040_pac::dma::timer2">timer2</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="mod" href="timer3/index.html" title="mod rp2040_pac::dma::timer3">timer3</a></div><div class="desc docblock-short">Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::dma::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.CH0_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH0_DBG_CTDREQ">CH0_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH0_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH0_DBG_TCR.html" title="type rp2040_pac::dma::CH0_DBG_TCR">CH0_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH0_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH1_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH1_DBG_CTDREQ">CH1_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH1_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH1_DBG_TCR.html" title="type rp2040_pac::dma::CH1_DBG_TCR">CH1_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH1_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH2_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH2_DBG_CTDREQ">CH2_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH2_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH2_DBG_TCR.html" title="type rp2040_pac::dma::CH2_DBG_TCR">CH2_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH2_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH3_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH3_DBG_CTDREQ">CH3_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH3_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH3_DBG_TCR.html" title="type rp2040_pac::dma::CH3_DBG_TCR">CH3_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH3_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH4_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH4_DBG_CTDREQ">CH4_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH4_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH4_DBG_TCR.html" title="type rp2040_pac::dma::CH4_DBG_TCR">CH4_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH4_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH5_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH5_DBG_CTDREQ">CH5_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH5_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH5_DBG_TCR.html" title="type rp2040_pac::dma::CH5_DBG_TCR">CH5_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH5_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH6_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH6_DBG_CTDREQ">CH6_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH6_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH6_DBG_TCR.html" title="type rp2040_pac::dma::CH6_DBG_TCR">CH6_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH6_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH7_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH7_DBG_CTDREQ">CH7_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH7_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH7_DBG_TCR.html" title="type rp2040_pac::dma::CH7_DBG_TCR">CH7_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH7_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH8_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH8_DBG_CTDREQ">CH8_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH8_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH8_DBG_TCR.html" title="type rp2040_pac::dma::CH8_DBG_TCR">CH8_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH8_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH9_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH9_DBG_CTDREQ">CH9_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH9_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH9_DBG_TCR.html" title="type rp2040_pac::dma::CH9_DBG_TCR">CH9_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH9_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH10_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH10_DBG_CTDREQ">CH10_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH10_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH10_DBG_TCR.html" title="type rp2040_pac::dma::CH10_DBG_TCR">CH10_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH10_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CH11_DBG_CTDREQ.html" title="type rp2040_pac::dma::CH11_DBG_CTDREQ">CH11_<wbr>DBG_<wbr>CTDREQ</a></div><div class="desc docblock-short">CH11_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.</div></li><li><div class="item-name"><a class="type" href="type.CH11_DBG_TCR.html" title="type rp2040_pac::dma::CH11_DBG_TCR">CH11_<wbr>DBG_<wbr>TCR</a></div><div class="desc docblock-short">CH11_DBG_TCR (r) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer</div></li><li><div class="item-name"><a class="type" href="type.CHAN_ABORT.html" title="type rp2040_pac::dma::CHAN_ABORT">CHAN_<wbr>ABORT</a></div><div class="desc docblock-short">CHAN_ABORT (rw) register accessor: Abort an in-progress transfer sequence on one or more channels</div></li><li><div class="item-name"><a class="type" href="type.FIFO_LEVELS.html" title="type rp2040_pac::dma::FIFO_LEVELS">FIFO_<wbr>LEVELS</a></div><div class="desc docblock-short">FIFO_LEVELS (r) register accessor: Debug RAF, WAF, TDF levels</div></li><li><div class="item-name"><a class="type" href="type.INTE0.html" title="type rp2040_pac::dma::INTE0">INTE0</a></div><div class="desc docblock-short">INTE0 (rw) register accessor: Interrupt Enables for IRQ 0</div></li><li><div class="item-name"><a class="type" href="type.INTE1.html" title="type rp2040_pac::dma::INTE1">INTE1</a></div><div class="desc docblock-short">INTE1 (rw) register accessor: Interrupt Enables for IRQ 1</div></li><li><div class="item-name"><a class="type" href="type.INTF0.html" title="type rp2040_pac::dma::INTF0">INTF0</a></div><div class="desc docblock-short">INTF0 (rw) register accessor: Force Interrupts</div></li><li><div class="item-name"><a class="type" href="type.INTF1.html" title="type rp2040_pac::dma::INTF1">INTF1</a></div><div class="desc docblock-short">INTF1 (rw) register accessor: Force Interrupts for IRQ 1</div></li><li><div class="item-name"><a class="type" href="type.INTR.html" title="type rp2040_pac::dma::INTR">INTR</a></div><div class="desc docblock-short">INTR (rw) register accessor: Interrupt Status (raw)</div></li><li><div class="item-name"><a class="type" href="type.INTS0.html" title="type rp2040_pac::dma::INTS0">INTS0</a></div><div class="desc docblock-short">INTS0 (rw) register accessor: Interrupt Status for IRQ 0</div></li><li><div class="item-name"><a class="type" href="type.INTS1.html" title="type rp2040_pac::dma::INTS1">INTS1</a></div><div class="desc docblock-short">INTS1 (rw) register accessor: Interrupt Status (masked) for IRQ 1</div></li><li><div class="item-name"><a class="type" href="type.MULTI_CHAN_TRIGGER.html" title="type rp2040_pac::dma::MULTI_CHAN_TRIGGER">MULT<wbr>I_<wbr>CHAN_<wbr>TRIGGER</a></div><div class="desc docblock-short">MULTI_CHAN_TRIGGER (rw) register accessor: Trigger one or more channels simultaneously</div></li><li><div class="item-name"><a class="type" href="type.N_CHANNELS.html" title="type rp2040_pac::dma::N_CHANNELS">N_<wbr>CHANNELS</a></div><div class="desc docblock-short">N_CHANNELS (r) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.</div></li><li><div class="item-name"><a class="type" href="type.SNIFF_CTRL.html" title="type rp2040_pac::dma::SNIFF_CTRL">SNIF<wbr>F_<wbr>CTRL</a></div><div class="desc docblock-short">SNIFF_CTRL (rw) register accessor: Sniffer Control</div></li><li><div class="item-name"><a class="type" href="type.SNIFF_DATA.html" title="type rp2040_pac::dma::SNIFF_DATA">SNIF<wbr>F_<wbr>DATA</a></div><div class="desc docblock-short">SNIFF_DATA (rw) register accessor: Data accumulator for sniff hardware<br />
Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.</div></li><li><div class="item-name"><a class="type" href="type.TIMER0.html" title="type rp2040_pac::dma::TIMER0">TIMER0</a></div><div class="desc docblock-short">TIMER0 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="type" href="type.TIMER1.html" title="type rp2040_pac::dma::TIMER1">TIMER1</a></div><div class="desc docblock-short">TIMER1 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="type" href="type.TIMER2.html" title="type rp2040_pac::dma::TIMER2">TIMER2</a></div><div class="desc docblock-short">TIMER2 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li><li><div class="item-name"><a class="type" href="type.TIMER3.html" title="type rp2040_pac::dma::TIMER3">TIMER3</a></div><div class="desc docblock-short">TIMER3 (rw) register accessor: Pacing (X/Y) Fractional Timer<br />
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.</div></li></ul></section></div></main></body></html>
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