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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect."><title>rp2040_pac::i2c0::ic_con - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module ic_con</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#structs">Structs</a></li><li><a href="#enums">Enums</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>i2c0</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">i2c0</a>::<wbr><a class="mod" href="#">ic_con</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../../src/rp2040_pac/i2c0/ic_con.rs.html#1-779">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0]
register being set to 0. Writes at other times have no effect.</p>
<p>Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.</p>
</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.IC_CON_SPEC.html" title="struct rp2040_pac::i2c0::ic_con::IC_CON_SPEC">IC_<wbr>CON_<wbr>SPEC</a></div><div class="desc docblock-short">I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0]
register being set to 0. Writes at other times have no effect.</div></li></ul><h2 id="enums" class="section-header">Enums<a href="#enums" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="enum" href="enum.IC_10BITADDR_MASTER_A.html" title="enum rp2040_pac::i2c0::ic_con::IC_10BITADDR_MASTER_A">IC_<wbr>10BITADD<wbr>R_<wbr>MASTE<wbr>R_<wbr>A</a></div><div class="desc docblock-short">Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</div></li><li><div class="item-name"><a class="enum" href="enum.IC_10BITADDR_SLAVE_A.html" title="enum rp2040_pac::i2c0::ic_con::IC_10BITADDR_SLAVE_A">IC_<wbr>10BITADD<wbr>R_<wbr>SLAV<wbr>E_<wbr>A</a></div><div class="desc docblock-short">When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</div></li><li><div class="item-name"><a class="enum" href="enum.IC_RESTART_EN_A.html" title="enum rp2040_pac::i2c0::ic_con::IC_RESTART_EN_A">IC_<wbr>RESTAR<wbr>T_<wbr>EN_<wbr>A</a></div><div class="desc docblock-short">Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.</div></li><li><div class="item-name"><a class="enum" href="enum.IC_SLAVE_DISABLE_A.html" title="enum rp2040_pac::i2c0::ic_con::IC_SLAVE_DISABLE_A">IC_<wbr>SLAV<wbr>E_<wbr>DISABL<wbr>E_<wbr>A</a></div><div class="desc docblock-short">This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.</div></li><li><div class="item-name"><a class="enum" href="enum.MASTER_MODE_A.html" title="enum rp2040_pac::i2c0::ic_con::MASTER_MODE_A">MASTE<wbr>R_<wbr>MODE_<wbr>A</a></div><div class="desc docblock-short">This bit controls whether the DW_apb_i2c master is enabled.</div></li><li><div class="item-name"><a class="enum" href="enum.RX_FIFO_FULL_HLD_CTRL_A.html" title="enum rp2040_pac::i2c0::ic_con::RX_FIFO_FULL_HLD_CTRL_A">RX_<wbr>FIFO_<wbr>FULL_<wbr>HLD_<wbr>CTRL_<wbr>A</a></div><div class="desc docblock-short">This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.</div></li><li><div class="item-name"><a class="enum" href="enum.SPEED_A.html" title="enum rp2040_pac::i2c0::ic_con::SPEED_A">SPEED_A</a></div><div class="desc docblock-short">These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.</div></li><li><div class="item-name"><a class="enum" href="enum.STOP_DET_IFADDRESSED_A.html" title="enum rp2040_pac::i2c0::ic_con::STOP_DET_IFADDRESSED_A">STOP_<wbr>DET_<wbr>IFADDRESSE<wbr>D_<wbr>A</a></div><div class="desc docblock-short">In slave mode: - 1’b1: issues the STOP_DET interrupt only when it is addressed. - 1’b0: issues the STOP_DET irrespective of whether it’s addressed or not. Reset value: 0x0</div></li><li><div class="item-name"><a class="enum" href="enum.TX_EMPTY_CTRL_A.html" title="enum rp2040_pac::i2c0::ic_con::TX_EMPTY_CTRL_A">TX_<wbr>EMPT<wbr>Y_<wbr>CTRL_<wbr>A</a></div><div class="desc docblock-short">This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.IC_10BITADDR_MASTER_R.html" title="type rp2040_pac::i2c0::ic_con::IC_10BITADDR_MASTER_R">IC_<wbr>10BITADD<wbr>R_<wbr>MASTE<wbr>R_<wbr>R</a></div><div class="desc docblock-short">Field <code>IC_10BITADDR_MASTER</code> reader - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</div></li><li><div class="item-name"><a class="type" href="type.IC_10BITADDR_MASTER_W.html" title="type rp2040_pac::i2c0::ic_con::IC_10BITADDR_MASTER_W">IC_<wbr>10BITADD<wbr>R_<wbr>MASTE<wbr>R_<wbr>W</a></div><div class="desc docblock-short">Field <code>IC_10BITADDR_MASTER</code> writer - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing</div></li><li><div class="item-name"><a class="type" href="type.IC_10BITADDR_SLAVE_R.html" title="type rp2040_pac::i2c0::ic_con::IC_10BITADDR_SLAVE_R">IC_<wbr>10BITADD<wbr>R_<wbr>SLAV<wbr>E_<wbr>R</a></div><div class="desc docblock-short">Field <code>IC_10BITADDR_SLAVE</code> reader - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</div></li><li><div class="item-name"><a class="type" href="type.IC_10BITADDR_SLAVE_W.html" title="type rp2040_pac::i2c0::ic_con::IC_10BITADDR_SLAVE_W">IC_<wbr>10BITADD<wbr>R_<wbr>SLAV<wbr>E_<wbr>W</a></div><div class="desc docblock-short">Field <code>IC_10BITADDR_SLAVE</code> writer - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.</div></li><li><div class="item-name"><a class="type" href="type.IC_RESTART_EN_R.html" title="type rp2040_pac::i2c0::ic_con::IC_RESTART_EN_R">IC_<wbr>RESTAR<wbr>T_<wbr>EN_<wbr>R</a></div><div class="desc docblock-short">Field <code>IC_RESTART_EN</code> reader - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.</div></li><li><div class="item-name"><a class="type" href="type.IC_RESTART_EN_W.html" title="type rp2040_pac::i2c0::ic_con::IC_RESTART_EN_W">IC_<wbr>RESTAR<wbr>T_<wbr>EN_<wbr>W</a></div><div class="desc docblock-short">Field <code>IC_RESTART_EN</code> writer - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.</div></li><li><div class="item-name"><a class="type" href="type.IC_SLAVE_DISABLE_R.html" title="type rp2040_pac::i2c0::ic_con::IC_SLAVE_DISABLE_R">IC_<wbr>SLAV<wbr>E_<wbr>DISABL<wbr>E_<wbr>R</a></div><div class="desc docblock-short">Field <code>IC_SLAVE_DISABLE</code> reader - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.</div></li><li><div class="item-name"><a class="type" href="type.IC_SLAVE_DISABLE_W.html" title="type rp2040_pac::i2c0::ic_con::IC_SLAVE_DISABLE_W">IC_<wbr>SLAV<wbr>E_<wbr>DISABL<wbr>E_<wbr>W</a></div><div class="desc docblock-short">Field <code>IC_SLAVE_DISABLE</code> writer - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.</div></li><li><div class="item-name"><a class="type" href="type.MASTER_MODE_R.html" title="type rp2040_pac::i2c0::ic_con::MASTER_MODE_R">MASTE<wbr>R_<wbr>MODE_<wbr>R</a></div><div class="desc docblock-short">Field <code>MASTER_MODE</code> reader - This bit controls whether the DW_apb_i2c master is enabled.</div></li><li><div class="item-name"><a class="type" href="type.MASTER_MODE_W.html" title="type rp2040_pac::i2c0::ic_con::MASTER_MODE_W">MASTE<wbr>R_<wbr>MODE_<wbr>W</a></div><div class="desc docblock-short">Field <code>MASTER_MODE</code> writer - This bit controls whether the DW_apb_i2c master is enabled.</div></li><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::i2c0::ic_con::R">R</a></div><div class="desc docblock-short">Register <code>IC_CON</code> reader</div></li><li><div class="item-name"><a class="type" href="type.RX_FIFO_FULL_HLD_CTRL_R.html" title="type rp2040_pac::i2c0::ic_con::RX_FIFO_FULL_HLD_CTRL_R">RX_<wbr>FIFO_<wbr>FULL_<wbr>HLD_<wbr>CTRL_<wbr>R</a></div><div class="desc docblock-short">Field <code>RX_FIFO_FULL_HLD_CTRL</code> reader - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.</div></li><li><div class="item-name"><a class="type" href="type.RX_FIFO_FULL_HLD_CTRL_W.html" title="type rp2040_pac::i2c0::ic_con::RX_FIFO_FULL_HLD_CTRL_W">RX_<wbr>FIFO_<wbr>FULL_<wbr>HLD_<wbr>CTRL_<wbr>W</a></div><div class="desc docblock-short">Field <code>RX_FIFO_FULL_HLD_CTRL</code> writer - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.</div></li><li><div class="item-name"><a class="type" href="type.SPEED_R.html" title="type rp2040_pac::i2c0::ic_con::SPEED_R">SPEED_R</a></div><div class="desc docblock-short">Field <code>SPEED</code> reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.</div></li><li><div class="item-name"><a class="type" href="type.SPEED_W.html" title="type rp2040_pac::i2c0::ic_con::SPEED_W">SPEED_W</a></div><div class="desc docblock-short">Field <code>SPEED</code> writer - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.</div></li><li><div class="item-name"><a class="type" href="type.STOP_DET_IFADDRESSED_R.html" title="type rp2040_pac::i2c0::ic_con::STOP_DET_IFADDRESSED_R">STOP_<wbr>DET_<wbr>IFADDRESSE<wbr>D_<wbr>R</a></div><div class="desc docblock-short">Field <code>STOP_DET_IFADDRESSED</code> reader - In slave mode: - 1’b1: issues the STOP_DET interrupt only when it is addressed. - 1’b0: issues the STOP_DET irrespective of whether it’s addressed or not. Reset value: 0x0</div></li><li><div class="item-name"><a class="type" href="type.STOP_DET_IFADDRESSED_W.html" title="type rp2040_pac::i2c0::ic_con::STOP_DET_IFADDRESSED_W">STOP_<wbr>DET_<wbr>IFADDRESSE<wbr>D_<wbr>W</a></div><div class="desc docblock-short">Field <code>STOP_DET_IFADDRESSED</code> writer - In slave mode: - 1’b1: issues the STOP_DET interrupt only when it is addressed. - 1’b0: issues the STOP_DET irrespective of whether it’s addressed or not. Reset value: 0x0</div></li><li><div class="item-name"><a class="type" href="type.STOP_DET_IF_MASTER_ACTIVE_R.html" title="type rp2040_pac::i2c0::ic_con::STOP_DET_IF_MASTER_ACTIVE_R">STOP_<wbr>DET_<wbr>IF_<wbr>MASTE<wbr>R_<wbr>ACTIV<wbr>E_<wbr>R</a></div><div class="desc docblock-short">Field <code>STOP_DET_IF_MASTER_ACTIVE</code> reader - Master issues the STOP_DET interrupt irrespective of whether master is active or not</div></li><li><div class="item-name"><a class="type" href="type.TX_EMPTY_CTRL_R.html" title="type rp2040_pac::i2c0::ic_con::TX_EMPTY_CTRL_R">TX_<wbr>EMPT<wbr>Y_<wbr>CTRL_<wbr>R</a></div><div class="desc docblock-short">Field <code>TX_EMPTY_CTRL</code> reader - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.</div></li><li><div class="item-name"><a class="type" href="type.TX_EMPTY_CTRL_W.html" title="type rp2040_pac::i2c0::ic_con::TX_EMPTY_CTRL_W">TX_<wbr>EMPT<wbr>Y_<wbr>CTRL_<wbr>W</a></div><div class="desc docblock-short">Field <code>TX_EMPTY_CTRL</code> writer - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::i2c0::ic_con::W">W</a></div><div class="desc docblock-short">Register <code>IC_CON</code> writer</div></li></ul></section></div></main></body></html>
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