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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception."><title>rp2040_pac::ppb::icsr - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module icsr</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#structs">Structs</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>ppb</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">ppb</a>::<wbr><a class="mod" href="#">icsr</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../../src/rp2040_pac/ppb/icsr.rs.html#1-263">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</p>
</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.ICSR_SPEC.html" title="struct rp2040_pac::ppb::icsr::ICSR_SPEC">ICSR_<wbr>SPEC</a></div><div class="desc docblock-short">Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.ISRPENDING_R.html" title="type rp2040_pac::ppb::icsr::ISRPENDING_R">ISRPENDIN<wbr>G_<wbr>R</a></div><div class="desc docblock-short">Field <code>ISRPENDING</code> reader - External interrupt pending flag</div></li><li><div class="item-name"><a class="type" href="type.ISRPREEMPT_R.html" title="type rp2040_pac::ppb::icsr::ISRPREEMPT_R">ISRPREEMP<wbr>T_<wbr>R</a></div><div class="desc docblock-short">Field <code>ISRPREEMPT</code> reader - The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.</div></li><li><div class="item-name"><a class="type" href="type.NMIPENDSET_R.html" title="type rp2040_pac::ppb::icsr::NMIPENDSET_R">NMIPENDSE<wbr>T_<wbr>R</a></div><div class="desc docblock-short">Field <code>NMIPENDSET</code> reader - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.<br />
NMI set-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Changes NMI exception state to pending.<br />
Read:<br />
0 = NMI exception is not pending.<br />
1 = NMI exception is pending.<br />
Because NMI is the highest-priority exception, normally the processor enters the NMI<br />
exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears<br />
this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the<br />
NMI signal is reasserted while the processor is executing that handler.</div></li><li><div class="item-name"><a class="type" href="type.NMIPENDSET_W.html" title="type rp2040_pac::ppb::icsr::NMIPENDSET_W">NMIPENDSE<wbr>T_<wbr>W</a></div><div class="desc docblock-short">Field <code>NMIPENDSET</code> writer - Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.<br />
NMI set-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Changes NMI exception state to pending.<br />
Read:<br />
0 = NMI exception is not pending.<br />
1 = NMI exception is pending.<br />
Because NMI is the highest-priority exception, normally the processor enters the NMI<br />
exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears<br />
this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the<br />
NMI signal is reasserted while the processor is executing that handler.</div></li><li><div class="item-name"><a class="type" href="type.PENDSTCLR_R.html" title="type rp2040_pac::ppb::icsr::PENDSTCLR_R">PENDSTCL<wbr>R_<wbr>R</a></div><div class="desc docblock-short">Field <code>PENDSTCLR</code> reader - SysTick exception clear-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Removes the pending state from the SysTick exception.<br />
This bit is WO. On a register read its value is Unknown.</div></li><li><div class="item-name"><a class="type" href="type.PENDSTCLR_W.html" title="type rp2040_pac::ppb::icsr::PENDSTCLR_W">PENDSTCL<wbr>R_<wbr>W</a></div><div class="desc docblock-short">Field <code>PENDSTCLR</code> writer - SysTick exception clear-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Removes the pending state from the SysTick exception.<br />
This bit is WO. On a register read its value is Unknown.</div></li><li><div class="item-name"><a class="type" href="type.PENDSTSET_R.html" title="type rp2040_pac::ppb::icsr::PENDSTSET_R">PENDSTSE<wbr>T_<wbr>R</a></div><div class="desc docblock-short">Field <code>PENDSTSET</code> reader - SysTick exception set-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Changes SysTick exception state to pending.<br />
Read:<br />
0 = SysTick exception is not pending.<br />
1 = SysTick exception is pending.</div></li><li><div class="item-name"><a class="type" href="type.PENDSTSET_W.html" title="type rp2040_pac::ppb::icsr::PENDSTSET_W">PENDSTSE<wbr>T_<wbr>W</a></div><div class="desc docblock-short">Field <code>PENDSTSET</code> writer - SysTick exception set-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Changes SysTick exception state to pending.<br />
Read:<br />
0 = SysTick exception is not pending.<br />
1 = SysTick exception is pending.</div></li><li><div class="item-name"><a class="type" href="type.PENDSVCLR_R.html" title="type rp2040_pac::ppb::icsr::PENDSVCLR_R">PENDSVCL<wbr>R_<wbr>R</a></div><div class="desc docblock-short">Field <code>PENDSVCLR</code> reader - PendSV clear-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Removes the pending state from the PendSV exception.</div></li><li><div class="item-name"><a class="type" href="type.PENDSVCLR_W.html" title="type rp2040_pac::ppb::icsr::PENDSVCLR_W">PENDSVCL<wbr>R_<wbr>W</a></div><div class="desc docblock-short">Field <code>PENDSVCLR</code> writer - PendSV clear-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Removes the pending state from the PendSV exception.</div></li><li><div class="item-name"><a class="type" href="type.PENDSVSET_R.html" title="type rp2040_pac::ppb::icsr::PENDSVSET_R">PENDSVSE<wbr>T_<wbr>R</a></div><div class="desc docblock-short">Field <code>PENDSVSET</code> reader - PendSV set-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Changes PendSV exception state to pending.<br />
Read:<br />
0 = PendSV exception is not pending.<br />
1 = PendSV exception is pending.<br />
Writing 1 to this bit is the only way to set the PendSV exception state to pending.</div></li><li><div class="item-name"><a class="type" href="type.PENDSVSET_W.html" title="type rp2040_pac::ppb::icsr::PENDSVSET_W">PENDSVSE<wbr>T_<wbr>W</a></div><div class="desc docblock-short">Field <code>PENDSVSET</code> writer - PendSV set-pending bit.<br />
Write:<br />
0 = No effect.<br />
1 = Changes PendSV exception state to pending.<br />
Read:<br />
0 = PendSV exception is not pending.<br />
1 = PendSV exception is pending.<br />
Writing 1 to this bit is the only way to set the PendSV exception state to pending.</div></li><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::ppb::icsr::R">R</a></div><div class="desc docblock-short">Register <code>ICSR</code> reader</div></li><li><div class="item-name"><a class="type" href="type.VECTACTIVE_R.html" title="type rp2040_pac::ppb::icsr::VECTACTIVE_R">VECTACTIV<wbr>E_<wbr>R</a></div><div class="desc docblock-short">Field <code>VECTACTIVE</code> reader - Active exception number field. Reset clears the VECTACTIVE field.</div></li><li><div class="item-name"><a class="type" href="type.VECTPENDING_R.html" title="type rp2040_pac::ppb::icsr::VECTPENDING_R">VECTPENDIN<wbr>G_<wbr>R</a></div><div class="desc docblock-short">Field <code>VECTPENDING</code> reader - Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::ppb::icsr::W">W</a></div><div class="desc docblock-short">Register <code>ICSR</code> writer</div></li></ul></section></div></main></body></html>
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