mirror of
https://github.com/rtic-rs/rtic.git
synced 2024-11-25 21:19:35 +01:00
4060c3def8
* Rebase to master * using interrupt_mod * bug fixes * fix other backends * Add changelog * forgot about rtic-macros * backend-specific configuration * core peripherals optional over macro argument * pre_init_preprocessing binding * CI for RISC-V (WIP) * separation of concerns * add targets for RISC-V examples * remove qemu feature * prepare examples folder * move examples all together * move ci out of examples * minor changes * add cortex-m * new xtask: proof of concept * fix build.yml * feature typo * clean rtic examples * reproduce weird issue * remove unsafe code in user app * update dependencies * allow builds on riscv32imc * let's fix QEMU * Update .github/workflows/build.yml Co-authored-by: Henrik Tjäder <henrik@tjaders.com> * New build.rs * removing test features * adapt ui test to new version of clippy * add more examples to RISC-V backend * proper configuration of heapless for riscv32imc * opt-out examples for riscv32imc * point to new version of riscv-slic * adapt new macro bindings * adapt examples and CI to stable * fix cortex-m CI * Review --------- Co-authored-by: Henrik Tjäder <henrik@tjaders.com>
11 lines
473 B
TOML
11 lines
473 B
TOML
[target.'cfg(all(target_arch = "riscv32", target_os = "none"))']
|
|
runner = "qemu-system-riscv32 -machine sifive_e,revb=true -nographic -semihosting-config enable=on,target=native -kernel"
|
|
# runner = "riscv64-unknown-elf-gdb -q -x gdb_init"
|
|
rustflags = [
|
|
"-C", "link-arg=-Thifive1-link.x",
|
|
]
|
|
|
|
[build]
|
|
# Pick ONE of these compilation targets
|
|
# target = "riscv32imc-unknown-none-elf" # non-atomic support
|
|
target = "riscv32imac-unknown-none-elf" # atomic support (partial)
|