rtic/2/api/rp2040_pac/clocks/wake_en0/sidebar-items.js

window.SIDEBAR_ITEMS = {"struct":["WAKE_EN0_SPEC"],"type":["CLK_ADC_ADC_R","CLK_ADC_ADC_W","CLK_PERI_SPI0_R","CLK_PERI_SPI0_W","CLK_PERI_SPI1_R","CLK_PERI_SPI1_W","CLK_RTC_RTC_R","CLK_RTC_RTC_W","CLK_SYS_ADC_R","CLK_SYS_ADC_W","CLK_SYS_BUSCTRL_R","CLK_SYS_BUSCTRL_W","CLK_SYS_BUSFABRIC_R","CLK_SYS_BUSFABRIC_W","CLK_SYS_CLOCKS_R","CLK_SYS_CLOCKS_W","CLK_SYS_DMA_R","CLK_SYS_DMA_W","CLK_SYS_I2C0_R","CLK_SYS_I2C0_W","CLK_SYS_I2C1_R","CLK_SYS_I2C1_W","CLK_SYS_IO_R","CLK_SYS_IO_W","CLK_SYS_JTAG_R","CLK_SYS_JTAG_W","CLK_SYS_PADS_R","CLK_SYS_PADS_W","CLK_SYS_PIO0_R","CLK_SYS_PIO0_W","CLK_SYS_PIO1_R","CLK_SYS_PIO1_W","CLK_SYS_PLL_SYS_R","CLK_SYS_PLL_SYS_W","CLK_SYS_PLL_USB_R","CLK_SYS_PLL_USB_W","CLK_SYS_PSM_R","CLK_SYS_PSM_W","CLK_SYS_PWM_R","CLK_SYS_PWM_W","CLK_SYS_RESETS_R","CLK_SYS_RESETS_W","CLK_SYS_ROM_R","CLK_SYS_ROM_W","CLK_SYS_ROSC_R","CLK_SYS_ROSC_W","CLK_SYS_RTC_R","CLK_SYS_RTC_W","CLK_SYS_SIO_R","CLK_SYS_SIO_W","CLK_SYS_SPI0_R","CLK_SYS_SPI0_W","CLK_SYS_SPI1_R","CLK_SYS_SPI1_W","CLK_SYS_SRAM0_R","CLK_SYS_SRAM0_W","CLK_SYS_SRAM1_R","CLK_SYS_SRAM1_W","CLK_SYS_SRAM2_R","CLK_SYS_SRAM2_W","CLK_SYS_SRAM3_R","CLK_SYS_SRAM3_W","CLK_SYS_VREG_AND_CHIP_RESET_R","CLK_SYS_VREG_AND_CHIP_RESET_W","R","W"]};