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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="API documentation for the Rust `regs` mod in crate `stm32_metapac`."><title>stm32_metapac::otg::regs - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="stm32_metapac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../stm32_metapac/index.html">stm32_<wbr>metapac</a><span class="version">15.0.0</span></h2></div><h2 class="location"><a href="#">Module regs</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#structs">Structs</a></li></ul></section><h2><a href="../index.html">In stm32_<wbr>metapac::<wbr>otg</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../../index.html">stm32_metapac</a>::<wbr><a href="../index.html">otg</a>::<wbr><a class="mod" href="#">regs</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.Cid.html" title="struct stm32_metapac::otg::regs::Cid">Cid</a></div><div class="desc docblock-short">Core ID register</div></li><li><div class="item-name"><a class="struct" href="struct.Daint.html" title="struct stm32_metapac::otg::regs::Daint">Daint</a></div><div class="desc docblock-short">Device all endpoints interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.Daintmsk.html" title="struct stm32_metapac::otg::regs::Daintmsk">Daintmsk</a></div><div class="desc docblock-short">All endpoints interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Dcfg.html" title="struct stm32_metapac::otg::regs::Dcfg">Dcfg</a></div><div class="desc docblock-short">Device configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.Dctl.html" title="struct stm32_metapac::otg::regs::Dctl">Dctl</a></div><div class="desc docblock-short">Device control register</div></li><li><div class="item-name"><a class="struct" href="struct.Diepctl.html" title="struct stm32_metapac::otg::regs::Diepctl">Diepctl</a></div><div class="desc docblock-short">Device endpoint control register</div></li><li><div class="item-name"><a class="struct" href="struct.Diepempmsk.html" title="struct stm32_metapac::otg::regs::Diepempmsk">Diepempmsk</a></div><div class="desc docblock-short">Device IN endpoint FIFO empty interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Diepint.html" title="struct stm32_metapac::otg::regs::Diepint">Diepint</a></div><div class="desc docblock-short">Device endpoint interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.Diepmsk.html" title="struct stm32_metapac::otg::regs::Diepmsk">Diepmsk</a></div><div class="desc docblock-short">Device IN endpoint common interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Dieptsiz.html" title="struct stm32_metapac::otg::regs::Dieptsiz">Dieptsiz</a></div><div class="desc docblock-short">Device endpoint transfer size register</div></li><li><div class="item-name"><a class="struct" href="struct.Doepctl.html" title="struct stm32_metapac::otg::regs::Doepctl">Doepctl</a></div><div class="desc docblock-short">Device endpoint control register</div></li><li><div class="item-name"><a class="struct" href="struct.Doepint.html" title="struct stm32_metapac::otg::regs::Doepint">Doepint</a></div><div class="desc docblock-short">Device endpoint interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.Doepmsk.html" title="struct stm32_metapac::otg::regs::Doepmsk">Doepmsk</a></div><div class="desc docblock-short">Device OUT endpoint common interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Doeptsiz.html" title="struct stm32_metapac::otg::regs::Doeptsiz">Doeptsiz</a></div><div class="desc docblock-short">Device OUT endpoint transfer size register</div></li><li><div class="item-name"><a class="struct" href="struct.Dsts.html" title="struct stm32_metapac::otg::regs::Dsts">Dsts</a></div><div class="desc docblock-short">Device status register</div></li><li><div class="item-name"><a class="struct" href="struct.Dtxfsts.html" title="struct stm32_metapac::otg::regs::Dtxfsts">Dtxfsts</a></div><div class="desc docblock-short">Device IN endpoint transmit FIFO status register</div></li><li><div class="item-name"><a class="struct" href="struct.Dvbusdis.html" title="struct stm32_metapac::otg::regs::Dvbusdis">Dvbusdis</a></div><div class="desc docblock-short">Device VBUS discharge time register</div></li><li><div class="item-name"><a class="struct" href="struct.Dvbuspulse.html" title="struct stm32_metapac::otg::regs::Dvbuspulse">Dvbuspulse</a></div><div class="desc docblock-short">Device VBUS pulsing time register</div></li><li><div class="item-name"><a class="struct" href="struct.Fifo.html" title="struct stm32_metapac::otg::regs::Fifo">Fifo</a></div><div class="desc docblock-short">FIFO register</div></li><li><div class="item-name"><a class="struct" href="struct.Fsiz.html" title="struct stm32_metapac::otg::regs::Fsiz">Fsiz</a></div><div class="desc docblock-short">FIFO size register</div></li><li><div class="item-name"><a class="struct" href="struct.Gahbcfg.html" title="struct stm32_metapac::otg::regs::Gahbcfg">Gahbcfg</a></div><div class="desc docblock-short">AHB configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.GccfgV1.html" title="struct stm32_metapac::otg::regs::GccfgV1">GccfgV1</a></div><div class="desc docblock-short">General core configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.GccfgV2.html" title="struct stm32_metapac::otg::regs::GccfgV2">GccfgV2</a></div><div class="desc docblock-short">General core configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.Gi2cctl.html" title="struct stm32_metapac::otg::regs::Gi2cctl">Gi2cctl</a></div><div class="desc docblock-short">I2C access register</div></li><li><div class="item-name"><a class="struct" href="struct.Gintmsk.html" title="struct stm32_metapac::otg::regs::Gintmsk">Gintmsk</a></div><div class="desc docblock-short">Interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Gintsts.html" title="struct stm32_metapac::otg::regs::Gintsts">Gintsts</a></div><div class="desc docblock-short">Core interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.Glpmcfg.html" title="struct stm32_metapac::otg::regs::Glpmcfg">Glpmcfg</a></div><div class="desc docblock-short">Core LPM configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.Gotgctl.html" title="struct stm32_metapac::otg::regs::Gotgctl">Gotgctl</a></div><div class="desc docblock-short">Control and status register</div></li><li><div class="item-name"><a class="struct" href="struct.Gotgint.html" title="struct stm32_metapac::otg::regs::Gotgint">Gotgint</a></div><div class="desc docblock-short">Interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.Grstctl.html" title="struct stm32_metapac::otg::regs::Grstctl">Grstctl</a></div><div class="desc docblock-short">Reset register</div></li><li><div class="item-name"><a class="struct" href="struct.Grxfsiz.html" title="struct stm32_metapac::otg::regs::Grxfsiz">Grxfsiz</a></div><div class="desc docblock-short">Receive FIFO size register</div></li><li><div class="item-name"><a class="struct" href="struct.Grxsts.html" title="struct stm32_metapac::otg::regs::Grxsts">Grxsts</a></div><div class="desc docblock-short">Status read and pop register</div></li><li><div class="item-name"><a class="struct" href="struct.Gusbcfg.html" title="struct stm32_metapac::otg::regs::Gusbcfg">Gusbcfg</a></div><div class="desc docblock-short">USB configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.Haint.html" title="struct stm32_metapac::otg::regs::Haint">Haint</a></div><div class="desc docblock-short">Host all channels interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.Haintmsk.html" title="struct stm32_metapac::otg::regs::Haintmsk">Haintmsk</a></div><div class="desc docblock-short">Host all channels interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Hcchar.html" title="struct stm32_metapac::otg::regs::Hcchar">Hcchar</a></div><div class="desc docblock-short">Host channel characteristics register</div></li><li><div class="item-name"><a class="struct" href="struct.Hcfg.html" title="struct stm32_metapac::otg::regs::Hcfg">Hcfg</a></div><div class="desc docblock-short">Host configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.Hcint.html" title="struct stm32_metapac::otg::regs::Hcint">Hcint</a></div><div class="desc docblock-short">Host channel interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.Hcintmsk.html" title="struct stm32_metapac::otg::regs::Hcintmsk">Hcintmsk</a></div><div class="desc docblock-short">Host channel mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Hctsiz.html" title="struct stm32_metapac::otg::regs::Hctsiz">Hctsiz</a></div><div class="desc docblock-short">Host channel transfer size register</div></li><li><div class="item-name"><a class="struct" href="struct.Hfir.html" title="struct stm32_metapac::otg::regs::Hfir">Hfir</a></div><div class="desc docblock-short">Host frame interval register</div></li><li><div class="item-name"><a class="struct" href="struct.Hfnum.html" title="struct stm32_metapac::otg::regs::Hfnum">Hfnum</a></div><div class="desc docblock-short">Host frame number/frame time remaining register</div></li><li><div class="item-name"><a class="struct" href="struct.Hnptxsts.html" title="struct stm32_metapac::otg::regs::Hnptxsts">Hnptxsts</a></div><div class="desc docblock-short">Non-periodic transmit FIFO/queue status register</div></li><li><div class="item-name"><a class="struct" href="struct.Hprt.html" title="struct stm32_metapac::otg::regs::Hprt">Hprt</a></div><div class="desc docblock-short">Host port control and status register</div></li><li><div class="item-name"><a class="struct" href="struct.Hptxsts.html" title="struct stm32_metapac::otg::regs::Hptxsts">Hptxsts</a></div><div class="desc docblock-short">Periodic transmit FIFO/queue status register</div></li><li><div class="item-name"><a class="struct" href="struct.Pcgcctl.html" title="struct stm32_metapac::otg::regs::Pcgcctl">Pcgcctl</a></div><div class="desc docblock-short">Power and clock gating control register</div></li></ul></section></div></main></body></html>
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