mirror/rtic
1
0
Fork 0
mirror of https://github.com/rtic-rs/rtic.git synced 2024-11-29 23:14:34 +01:00
Code Issues Projects Releases Packages Wiki Activity
rtic/dev/api/search.desc/rp2040_pac/rp2040_pac-desc-3-.js
github-merge-queue[bot] 5b32b958a3 deploy: f17915842f
2024-11-27 19:34:22 +00:00

1 line
No EOL
131 KiB
JavaScript
Raw Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

searchState.loadedDescShard("rp2040_pac", 3, "For a detailed description see freqa register\n0x08 - For a detailed description see freqa register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nControls the phase shifted output\n0x14 - Controls the phase shifted output\nThis just reads the state of the oscillator output so …\n0x1c - This just reads the state of the oscillator output …\nRing Oscillator Status\n0x18 - Ring Oscillator Status\nRing Oscillator control\n3358: <code>110100011110</code>\n4011: <code>111110101011</code>\nOn power-up this field is initialised to ENABLE The system …\nField <code>ENABLE</code> reader - On power-up this field is …\nField <code>ENABLE</code> writer - On power-up this field is …\nControls the number of delay stages in the ROSC ring LOW …\nField <code>FREQ_RANGE</code> reader - Controls the number of delay …\nField <code>FREQ_RANGE</code> writer - Controls the number of delay …\n4007: <code>111110100111</code>\n4004: <code>111110100100</code>\n4005: <code>111110100101</code>\nRegister <code>CTRL</code> reader\n4006: <code>111110100110</code>\nRegister <code>CTRL</code> writer\nWrites raw bits to the register.\n<code>110100011110</code>\nBits 12:23 - On power-up this field is initialised to …\nBits 12:23 - On power-up this field is initialised to …\n<code>111110101011</code>\nBits 0:11 - Controls the number of delay stages in the …\nBits 0:11 - Controls the number of delay stages in the …\nReturns the argument unchanged.\nReturns the argument unchanged.\nReturns the argument unchanged.\n<code>111110100111</code>\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>110100011110</code>\n<code>111110101011</code>\n<code>111110100111</code>\n<code>111110100100</code>\n<code>111110100101</code>\n<code>111110100110</code>\n<code>111110100100</code>\n<code>111110100101</code>\n<code>111110100110</code>\nGet enumerated values variant\nGet enumerated values variant\nset to 0xaa0 + div where div = 0 divides by 32 div = 1-31 …\nField <code>DIV</code> reader - set to 0xaa0 + div where div = 0 …\nControls the output divider\nField <code>DIV</code> writer - set to 0xaa0 + div where div = 0 …\n2720: <code>101010100000</code>\nRegister <code>DIV</code> reader\nRegister <code>DIV</code> writer\nWrites raw bits to the register.\nBits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 …\nBits 0:11 - set to 0xaa0 + div where div = 0 divides by 32 …\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>101010100000</code>\n<code>101010100000</code>\nGet enumerated values variant\nRing Oscillator pause control This is used to save power …\nRegister <code>DORMANT</code> reader\nRegister <code>DORMANT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DS0</code> reader - Stage 0 drive strength\nField <code>DS0</code> writer - Stage 0 drive strength\nField <code>DS1</code> reader - Stage 1 drive strength\nField <code>DS1</code> writer - Stage 1 drive strength\nField <code>DS2</code> reader - Stage 2 drive strength\nField <code>DS2</code> writer - Stage 2 drive strength\nField <code>DS3</code> reader - Stage 3 drive strength\nField <code>DS3</code> writer - Stage 3 drive strength\nThe FREQA &amp; FREQB registers control the frequency by …\n38550: <code>1001011010010110</code>\nSet to 0x9696 to apply the settings Any other value in …\nField <code>PASSWD</code> reader - Set to 0x9696 to apply the settings …\nField <code>PASSWD</code> writer - Set to 0x9696 to apply the settings …\nRegister <code>FREQA</code> reader\nRegister <code>FREQA</code> writer\nWrites raw bits to the register.\nBits 0:2 - Stage 0 drive strength\nBits 0:2 - Stage 0 drive strength\nBits 4:6 - Stage 1 drive strength\nBits 4:6 - Stage 1 drive strength\nBits 8:10 - Stage 2 drive strength\nBits 8:10 - Stage 2 drive strength\nBits 12:14 - Stage 3 drive strength\nBits 12:14 - Stage 3 drive strength\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>1001011010010110</code>\n<code>1001011010010110</code>\nBits 16:31 - Set to 0x9696 to apply the settings Any other …\nBits 16:31 - Set to 0x9696 to apply the settings Any other …\nGet enumerated values variant\nField <code>DS4</code> reader - Stage 4 drive strength\nField <code>DS4</code> writer - Stage 4 drive strength\nField <code>DS5</code> reader - Stage 5 drive strength\nField <code>DS5</code> writer - Stage 5 drive strength\nField <code>DS6</code> reader - Stage 6 drive strength\nField <code>DS6</code> writer - Stage 6 drive strength\nField <code>DS7</code> reader - Stage 7 drive strength\nField <code>DS7</code> writer - Stage 7 drive strength\nFor a detailed description see freqa register\n38550: <code>1001011010010110</code>\nSet to 0x9696 to apply the settings Any other value in …\nField <code>PASSWD</code> reader - Set to 0x9696 to apply the settings …\nField <code>PASSWD</code> writer - Set to 0x9696 to apply the settings …\nRegister <code>FREQB</code> reader\nRegister <code>FREQB</code> writer\nWrites raw bits to the register.\nBits 0:2 - Stage 4 drive strength\nBits 0:2 - Stage 4 drive strength\nBits 4:6 - Stage 5 drive strength\nBits 4:6 - Stage 5 drive strength\nBits 8:10 - Stage 6 drive strength\nBits 8:10 - Stage 6 drive strength\nBits 12:14 - Stage 7 drive strength\nBits 12:14 - Stage 7 drive strength\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>1001011010010110</code>\n<code>1001011010010110</code>\nBits 16:31 - Set to 0x9696 to apply the settings Any other …\nBits 16:31 - Set to 0x9696 to apply the settings Any other …\nGet enumerated values variant\nField <code>ENABLE</code> reader - enable the phase-shifted output this …\nField <code>ENABLE</code> writer - enable the phase-shifted output this …\nField <code>FLIP</code> reader - invert the phase-shifted output this …\nField <code>FLIP</code> writer - invert the phase-shifted output this …\nField <code>PASSWD</code> reader - set to 0xaa any other value enables …\nField <code>PASSWD</code> writer - set to 0xaa any other value enables …\nControls the phase shifted output\nRegister <code>PHASE</code> reader\nField <code>SHIFT</code> reader - phase shift the phase-shifted output …\nField <code>SHIFT</code> writer - phase shift the phase-shifted output …\nRegister <code>PHASE</code> writer\nWrites raw bits to the register.\nBit 3 - enable the phase-shifted output this can be …\nBit 3 - enable the phase-shifted output this can be …\nBit 2 - invert the phase-shifted output this is ignored …\nBit 2 - invert the phase-shifted output this is ignored …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 4:11 - set to 0xaa any other value enables the output …\nBits 4:11 - set to 0xaa any other value enables the output …\nBits 0:1 - phase shift the phase-shifted output by SHIFT …\nBits 0:1 - phase shift the phase-shifted output by SHIFT …\nRegister <code>RANDOMBIT</code> reader\nField <code>RANDOMBIT</code> reader -\nThis just reads the state of the oscillator output so …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0\nField <code>DIV_RUNNING</code> reader - post-divider is running this …\nField <code>ENABLED</code> reader - Oscillator is enabled but not …\nRegister <code>STATUS</code> reader\nField <code>STABLE</code> reader - Oscillator is running and stable\nRing Oscillator Status\nBit 16 - post-divider is running this resets to 0 but …\nBit 12 - Oscillator is enabled but not necessarily running …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 31 - Oscillator is running and stable\nCLKDIV_M1 (rw) register accessor: Divider minus 1 for the …\nCTRL (rw) register accessor: RTC Control and status\nINTE (rw) register accessor: Interrupt Enable\nINTF (rw) register accessor: Interrupt Force\nINTR (r) register accessor: Raw Interrupts\nINTS (r) register accessor: Interrupt status after masking …\nIRQ_SETUP_0 (rw) register accessor: Interrupt setup …\nIRQ_SETUP_1 (rw) register accessor: Interrupt setup …\nRTC_0 (r) register accessor: RTC register 0 Read this …\nRTC_1 (r) register accessor: RTC register 1.\nRegister block\nSETUP_0 (rw) register accessor: RTC setup register 0\nSETUP_1 (rw) register accessor: RTC setup register 1\nDivider minus 1 for the 1 second counter. Safe to change …\n0x00 - Divider minus 1 for the 1 second counter. Safe to …\nRTC Control and status\n0x0c - RTC Control and status\nReturns the argument unchanged.\nInterrupt Enable\n0x24 - Interrupt Enable\nInterrupt Force\n0x28 - Interrupt Force\nCalls <code>U::from(self)</code>.\nRaw Interrupts\n0x20 - Raw Interrupts\nInterrupt status after masking &amp; forcing\n0x2c - Interrupt status after masking &amp; forcing\nInterrupt setup register 0\n0x10 - Interrupt setup register 0\nInterrupt setup register 1\n0x14 - Interrupt setup register 1\nRTC register 0 Read this before RTC 1!\n0x1c - RTC register 0 Read this before RTC 1!\nRTC register 1.\n0x18 - RTC register 1.\nRTC setup register 0\n0x04 - RTC setup register 0\nRTC setup register 1\n0x08 - RTC setup register 1\nField <code>CLKDIV_M1</code> reader -\nDivider minus 1 for the 1 second counter. Safe to change …\nField <code>CLKDIV_M1</code> writer -\nRegister <code>CLKDIV_M1</code> reader\nRegister <code>CLKDIV_M1</code> writer\nWrites raw bits to the register.\nBits 0:15\nBits 0:15\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRTC Control and status\nField <code>FORCE_NOTLEAPYEAR</code> reader - If set, leapyear is …\nField <code>FORCE_NOTLEAPYEAR</code> writer - If set, leapyear is …\nField <code>LOAD</code> reader - Load RTC\nField <code>LOAD</code> writer - Load RTC\nRegister <code>CTRL</code> reader\nField <code>RTC_ACTIVE</code> reader - RTC enabled (running)\nField <code>RTC_ENABLE</code> reader - Enable RTC\nField <code>RTC_ENABLE</code> writer - Enable RTC\nRegister <code>CTRL</code> writer\nWrites raw bits to the register.\nBit 8 - If set, leapyear is forced off. Useful for years …\nBit 8 - If set, leapyear is forced off. Useful for years …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 4 - Load RTC\nBit 4 - Load RTC\nBit 1 - RTC enabled (running)\nBit 0 - Enable RTC\nBit 0 - Enable RTC\nInterrupt Enable\nRegister <code>INTE</code> reader\nField <code>RTC</code> reader -\nField <code>RTC</code> writer -\nRegister <code>INTE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0\nBit 0\nInterrupt Force\nRegister <code>INTF</code> reader\nField <code>RTC</code> reader -\nField <code>RTC</code> writer -\nRegister <code>INTF</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0\nBit 0\nRaw Interrupts\nRegister <code>INTR</code> reader\nField <code>RTC</code> reader -\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0\nInterrupt status after masking &amp; forcing\nRegister <code>INTS</code> reader\nField <code>RTC</code> reader -\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0\nField <code>DAY_ENA</code> reader - Enable day matching\nField <code>DAY_ENA</code> writer - Enable day matching\nField <code>DAY</code> reader - Day of the month (1..31)\nField <code>DAY</code> writer - Day of the month (1..31)\nInterrupt setup register 0\nField <code>MATCH_ACTIVE</code> reader -\nField <code>MATCH_ENA</code> reader - Global match enable. Don’t …\nField <code>MATCH_ENA</code> writer - Global match enable. Don’t …\nField <code>MONTH_ENA</code> reader - Enable month matching\nField <code>MONTH_ENA</code> writer - Enable month matching\nField <code>MONTH</code> reader - Month (1..12)\nField <code>MONTH</code> writer - Month (1..12)\nRegister <code>IRQ_SETUP_0</code> reader\nRegister <code>IRQ_SETUP_0</code> writer\nField <code>YEAR_ENA</code> reader - Enable year matching\nField <code>YEAR_ENA</code> writer - Enable year matching\nField <code>YEAR</code> reader - Year\nField <code>YEAR</code> writer - Year\nWrites raw bits to the register.\nBits 0:4 - Day of the month (1..31)\nBits 0:4 - Day of the month (1..31)\nBit 24 - Enable day matching\nBit 24 - Enable day matching\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 29\nBit 28 - Global match enable. Don’t change any other …\nBit 28 - Global match enable. Don’t change any other …\nBits 8:11 - Month (1..12)\nBits 8:11 - Month (1..12)\nBit 25 - Enable month matching\nBit 25 - Enable month matching\nBits 12:23 - Year\nBits 12:23 - Year\nBit 26 - Enable year matching\nBit 26 - Enable year matching\nField <code>DOTW_ENA</code> reader - Enable day of the week matching\nField <code>DOTW_ENA</code> writer - Enable day of the week matching\nField <code>DOTW</code> reader - Day of the week\nField <code>DOTW</code> writer - Day of the week\nField <code>HOUR_ENA</code> reader - Enable hour matching\nField <code>HOUR_ENA</code> writer - Enable hour matching\nField <code>HOUR</code> reader - Hours\nField <code>HOUR</code> writer - Hours\nInterrupt setup register 1\nField <code>MIN_ENA</code> reader - Enable minute matching\nField <code>MIN_ENA</code> writer - Enable minute matching\nField <code>MIN</code> reader - Minutes\nField <code>MIN</code> writer - Minutes\nRegister <code>IRQ_SETUP_1</code> reader\nField <code>SEC_ENA</code> reader - Enable second matching\nField <code>SEC_ENA</code> writer - Enable second matching\nField <code>SEC</code> reader - Seconds\nField <code>SEC</code> writer - Seconds\nRegister <code>IRQ_SETUP_1</code> writer\nWrites raw bits to the register.\nBits 24:26 - Day of the week\nBits 24:26 - Day of the week\nBit 31 - Enable day of the week matching\nBit 31 - Enable day of the week matching\nReturns the argument unchanged.\nBits 16:20 - Hours\nBits 16:20 - Hours\nBit 30 - Enable hour matching\nBit 30 - Enable hour matching\nCalls <code>U::from(self)</code>.\nBits 8:13 - Minutes\nBits 8:13 - Minutes\nBit 29 - Enable minute matching\nBit 29 - Enable minute matching\nBits 0:5 - Seconds\nBits 0:5 - Seconds\nBit 28 - Enable second matching\nBit 28 - Enable second matching\nField <code>DOTW</code> reader - Day of the week\nField <code>HOUR</code> reader - Hours\nField <code>MIN</code> reader - Minutes\nRegister <code>RTC_0</code> reader\nRTC register 0 Read this before RTC 1!\nField <code>SEC</code> reader - Seconds\nBits 24:26 - Day of the week\nReturns the argument unchanged.\nBits 16:20 - Hours\nCalls <code>U::from(self)</code>.\nBits 8:13 - Minutes\nBits 0:5 - Seconds\nField <code>DAY</code> reader - Day of the month (1..31)\nField <code>MONTH</code> reader - Month (1..12)\nRegister <code>RTC_1</code> reader\nRTC register 1.\nField <code>YEAR</code> reader - Year\nBits 0:4 - Day of the month (1..31)\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 8:11 - Month (1..12)\nBits 12:23 - Year\nField <code>DAY</code> reader - Day of the month (1..31)\nField <code>DAY</code> writer - Day of the month (1..31)\nField <code>MONTH</code> reader - Month (1..12)\nField <code>MONTH</code> writer - Month (1..12)\nRegister <code>SETUP_0</code> reader\nRTC setup register 0\nRegister <code>SETUP_0</code> writer\nField <code>YEAR</code> reader - Year\nField <code>YEAR</code> writer - Year\nWrites raw bits to the register.\nBits 0:4 - Day of the month (1..31)\nBits 0:4 - Day of the month (1..31)\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 8:11 - Month (1..12)\nBits 8:11 - Month (1..12)\nBits 12:23 - Year\nBits 12:23 - Year\nField <code>DOTW</code> reader - Day of the week: 1-Monday…0-Sunday …\nField <code>DOTW</code> writer - Day of the week: 1-Monday…0-Sunday …\nField <code>HOUR</code> reader - Hours\nField <code>HOUR</code> writer - Hours\nField <code>MIN</code> reader - Minutes\nField <code>MIN</code> writer - Minutes\nRegister <code>SETUP_1</code> reader\nField <code>SEC</code> reader - Seconds\nField <code>SEC</code> writer - Seconds\nRTC setup register 1\nRegister <code>SETUP_1</code> writer\nWrites raw bits to the register.\nBits 24:26 - Day of the week: 1-Monday…0-Sunday ISO 8601 …\nBits 24:26 - Day of the week: 1-Monday…0-Sunday ISO 8601 …\nReturns the argument unchanged.\nBits 16:20 - Hours\nBits 16:20 - Hours\nCalls <code>U::from(self)</code>.\nBits 8:13 - Minutes\nBits 8:13 - Minutes\nBits 0:5 - Seconds\nBits 0:5 - Seconds\nCPUID (r) register accessor: Processor core identifier …\nDIV_CSR (r) register accessor: Control and status register …\nDIV_QUOTIENT (rw) register accessor: Divider result …\nDIV_REMAINDER (rw) register accessor: Divider result …\nDIV_SDIVIDEND (rw) register accessor: Divider signed …\nDIV_SDIVISOR (rw) register accessor: Divider signed divisor\nDIV_UDIVIDEND (rw) register accessor: Divider unsigned …\nDIV_UDIVISOR (rw) register accessor: Divider unsigned …\nFIFO_RD (r) register accessor: Read access to this core’…\nFIFO_ST (rw) register accessor: Status register for …\nFIFO_WR (w) register accessor: Write access to this core’…\nGPIO_HI_IN (r) register accessor: Input value for QSPI pins\nGPIO_HI_OE (rw) register accessor: QSPI output enable\nGPIO_HI_OE_CLR (w) register accessor: QSPI output enable …\nGPIO_HI_OE_SET (w) register accessor: QSPI output enable …\nGPIO_HI_OE_XOR (w) register accessor: QSPI output enable …\nGPIO_HI_OUT (rw) register accessor: QSPI output value\nGPIO_HI_OUT_CLR (w) register accessor: QSPI output value …\nGPIO_HI_OUT_SET (w) register accessor: QSPI output value …\nGPIO_HI_OUT_XOR (w) register accessor: QSPI output value …\nGPIO_IN (r) register accessor: Input value for GPIO pins\nGPIO_OE (rw) register accessor: GPIO output enable\nGPIO_OE_CLR (w) register accessor: GPIO output enable clear\nGPIO_OE_SET (w) register accessor: GPIO output enable set\nGPIO_OE_XOR (w) register accessor: GPIO output enable XOR\nGPIO_OUT (rw) register accessor: GPIO output value\nGPIO_OUT_CLR (w) register accessor: GPIO output value clear\nGPIO_OUT_SET (w) register accessor: GPIO output value set\nGPIO_OUT_XOR (w) register accessor: GPIO output value XOR\nINTERP0_ACCUM0 (rw) register accessor: Read/write access …\nINTERP0_ACCUM0_ADD (rw) register accessor: Values written …\nINTERP0_ACCUM1 (rw) register accessor: Read/write access …\nINTERP0_ACCUM1_ADD (rw) register accessor: Values written …\nINTERP0_BASE0 (rw) register accessor: Read/write access to …\nINTERP0_BASE1 (rw) register accessor: Read/write access to …\nINTERP0_BASE2 (rw) register accessor: Read/write access to …\nINTERP0_BASE_1AND0 (w) register accessor: On write, the …\nINTERP0_CTRL_LANE0 (rw) register accessor: Control …\nINTERP0_CTRL_LANE1 (rw) register accessor: Control …\nINTERP0_PEEK_FULL (r) register accessor: Read FULL result, …\nINTERP0_PEEK_LANE0 (r) register accessor: Read LANE0 …\nINTERP0_PEEK_LANE1 (r) register accessor: Read LANE1 …\nINTERP0_POP_FULL (r) register accessor: Read FULL result, …\nINTERP0_POP_LANE0 (r) register accessor: Read LANE0 …\nINTERP0_POP_LANE1 (r) register accessor: Read LANE1 …\nINTERP1_ACCUM0 (rw) register accessor: Read/write access …\nINTERP1_ACCUM0_ADD (rw) register accessor: Values written …\nINTERP1_ACCUM1 (rw) register accessor: Read/write access …\nINTERP1_ACCUM1_ADD (rw) register accessor: Values written …\nINTERP1_BASE0 (rw) register accessor: Read/write access to …\nINTERP1_BASE1 (rw) register accessor: Read/write access to …\nINTERP1_BASE2 (rw) register accessor: Read/write access to …\nINTERP1_BASE_1AND0 (w) register accessor: On write, the …\nINTERP1_CTRL_LANE0 (rw) register accessor: Control …\nINTERP1_CTRL_LANE1 (rw) register accessor: Control …\nINTERP1_PEEK_FULL (r) register accessor: Read FULL result, …\nINTERP1_PEEK_LANE0 (r) register accessor: Read LANE0 …\nINTERP1_PEEK_LANE1 (r) register accessor: Read LANE1 …\nINTERP1_POP_FULL (r) register accessor: Read FULL result, …\nINTERP1_POP_LANE0 (r) register accessor: Read LANE0 …\nINTERP1_POP_LANE1 (r) register accessor: Read LANE1 …\nRegister block\nSPINLOCK (rw) register accessor: Reading from a spinlock …\nSPINLOCK_ST (r) register accessor: Spinlock state A bitmap …\nProcessor core identifier Value is 0 when read from …\n0x00 - Processor core identifier Value is 0 when read from …\nControl and status register for divider.\n0x78 - Control and status register for divider.\nDivider result quotient The result of <code>DIVIDEND / DIVISOR</code> …\n0x70 - Divider result quotient The result of …\nDivider result remainder The result of <code>DIVIDEND % DIVISOR</code> …\n0x74 - Divider result remainder The result of …\nDivider signed dividend The same as UDIVIDEND, but starts …\n0x68 - Divider signed dividend The same as UDIVIDEND, but …\nDivider signed divisor The same as UDIVISOR, but starts a …\n0x6c - Divider signed divisor The same as UDIVISOR, but …\nDivider unsigned dividend Write to the DIVIDEND operand of …\n0x60 - Divider unsigned dividend Write to the DIVIDEND …\nDivider unsigned divisor Write to the DIVISOR operand of …\n0x64 - Divider unsigned divisor Write to the DIVISOR …\nRead access to this core’s RX FIFO\n0x58 - Read access to this core’s RX FIFO\nStatus register for inter-core FIFOs (mailboxes). There is …\n0x50 - Status register for inter-core FIFOs (mailboxes). …\nWrite access to this core’s TX FIFO\n0x54 - Write access to this core’s TX FIFO\nReturns the argument unchanged.\nInput value for QSPI pins\n0x08 - Input value for QSPI pins\nQSPI output enable\n0x40 - QSPI output enable\nQSPI output enable clear\n0x48 - QSPI output enable clear\nQSPI output enable set\n0x44 - QSPI output enable set\nQSPI output enable XOR\n0x4c - QSPI output enable XOR\nQSPI output value\n0x30 - QSPI output value\nQSPI output value clear\n0x38 - QSPI output value clear\nQSPI output value set\n0x34 - QSPI output value set\nQSPI output value XOR\n0x3c - QSPI output value XOR\nInput value for GPIO pins\n0x04 - Input value for GPIO pins\nGPIO output enable\n0x20 - GPIO output enable\nGPIO output enable clear\n0x28 - GPIO output enable clear\nGPIO output enable set\n0x24 - GPIO output enable set\nGPIO output enable XOR\n0x2c - GPIO output enable XOR\nGPIO output value\n0x10 - GPIO output value\nGPIO output value clear\n0x18 - GPIO output value clear\nGPIO output value set\n0x14 - GPIO output value set\nGPIO output value XOR\n0x1c - GPIO output value XOR\nRead/write access to accumulator 0\n0x80 - Read/write access to accumulator 0\nValues written here are atomically added to ACCUM0 Reading …\n0xb4 - Values written here are atomically added to ACCUM0 …\nRead/write access to accumulator 1\n0x84 - Read/write access to accumulator 1\nValues written here are atomically added to ACCUM1 Reading …\n0xb8 - Values written here are atomically added to ACCUM1 …\nRead/write access to BASE0 register.\n0x88 - Read/write access to BASE0 register.\nRead/write access to BASE1 register.\n0x8c - Read/write access to BASE1 register.\nRead/write access to BASE2 register.\n0x90 - Read/write access to BASE2 register.\nOn write, the lower 16 bits go to BASE0, upper bits to …\n0xbc - On write, the lower 16 bits go to BASE0, upper bits …\nControl register for lane 0\n0xac - Control register for lane 0\nControl register for lane 1\n0xb0 - Control register for lane 1\nRead FULL result, without altering any internal state …\n0xa8 - Read FULL result, without altering any internal …\nRead LANE0 result, without altering any internal state …\n0xa0 - Read LANE0 result, without altering any internal …\nRead LANE1 result, without altering any internal state …\n0xa4 - Read LANE1 result, without altering any internal …\nRead FULL result, and simultaneously write lane results to …\n0x9c - Read FULL result, and simultaneously write lane …\nRead LANE0 result, and simultaneously write lane results …\n0x94 - Read LANE0 result, and simultaneously write lane …\nRead LANE1 result, and simultaneously write lane results …\n0x98 - Read LANE1 result, and simultaneously write lane …\nRead/write access to accumulator 0\n0xc0 - Read/write access to accumulator 0\nValues written here are atomically added to ACCUM0 Reading …\n0xf4 - Values written here are atomically added to ACCUM0 …\nRead/write access to accumulator 1\n0xc4 - Read/write access to accumulator 1\nValues written here are atomically added to ACCUM1 Reading …\n0xf8 - Values written here are atomically added to ACCUM1 …\nRead/write access to BASE0 register.\n0xc8 - Read/write access to BASE0 register.\nRead/write access to BASE1 register.\n0xcc - Read/write access to BASE1 register.\nRead/write access to BASE2 register.\n0xd0 - Read/write access to BASE2 register.\nOn write, the lower 16 bits go to BASE0, upper bits to …\n0xfc - On write, the lower 16 bits go to BASE0, upper bits …\nControl register for lane 0\n0xec - Control register for lane 0\nControl register for lane 1\n0xf0 - Control register for lane 1\nRead FULL result, without altering any internal state …\n0xe8 - Read FULL result, without altering any internal …\nRead LANE0 result, without altering any internal state …\n0xe0 - Read LANE0 result, without altering any internal …\nRead LANE1 result, without altering any internal state …\n0xe4 - Read LANE1 result, without altering any internal …\nRead FULL result, and simultaneously write lane results to …\n0xdc - Read FULL result, and simultaneously write lane …\nRead LANE0 result, and simultaneously write lane results …\n0xd4 - Read LANE0 result, and simultaneously write lane …\nRead LANE1 result, and simultaneously write lane results …\n0xd8 - Read LANE1 result, and simultaneously write lane …\nCalls <code>U::from(self)</code>.\nReading from a spinlock address will:\n0x100..0x180 - Reading from a spinlock address will:\nIterator for array of: 0x100..0x180 - Reading from a …\nSpinlock state A bitmap containing the state of all 32 …\n0x5c - Spinlock state A bitmap containing the state of all …\nProcessor core identifier Value is 0 when read from …\nRegister <code>CPUID</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DIRTY</code> reader - Changes to 1 when any register is …\nControl and status register for divider.\nRegister <code>DIV_CSR</code> reader\nField <code>READY</code> reader - Reads as 0 when a calculation is in …\nBit 1 - Changes to 1 when any register is written, and …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Reads as 0 when a calculation is in progress, 1 …\nDivider result quotient The result of <code>DIVIDEND / DIVISOR</code> …\nRegister <code>DIV_QUOTIENT</code> reader\nRegister <code>DIV_QUOTIENT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDivider result remainder The result of <code>DIVIDEND % DIVISOR</code> …\nRegister <code>DIV_REMAINDER</code> reader\nRegister <code>DIV_REMAINDER</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDivider signed dividend The same as UDIVIDEND, but starts …\nRegister <code>DIV_SDIVIDEND</code> reader\nRegister <code>DIV_SDIVIDEND</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDivider signed divisor The same as UDIVISOR, but starts a …\nRegister <code>DIV_SDIVISOR</code> reader\nRegister <code>DIV_SDIVISOR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDivider unsigned dividend Write to the DIVIDEND operand of …\nRegister <code>DIV_UDIVIDEND</code> reader\nRegister <code>DIV_UDIVIDEND</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nDivider unsigned divisor Write to the DIVISOR operand of …\nRegister <code>DIV_UDIVISOR</code> reader\nRegister <code>DIV_UDIVISOR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead access to this core’s RX FIFO\nRegister <code>FIFO_RD</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nStatus register for inter-core FIFOs (mailboxes). There is …\nRegister <code>FIFO_ST</code> reader\nField <code>RDY</code> reader - Value is 1 if this core’s TX FIFO is …\nField <code>ROE</code> reader - Sticky flag indicating the RX FIFO was …\nField <code>ROE</code> writer - Sticky flag indicating the RX FIFO was …\nField <code>VLD</code> reader - Value is 1 if this core’s RX FIFO is …\nRegister <code>FIFO_ST</code> writer\nField <code>WOF</code> reader - Sticky flag indicating the TX FIFO was …\nField <code>WOF</code> writer - Sticky flag indicating the TX FIFO was …\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 1 - Value is 1 if this core’s TX FIFO is not full …\nBit 3 - Sticky flag indicating the RX FIFO was read when …\nBit 3 - Sticky flag indicating the RX FIFO was read when …\nBit 0 - Value is 1 if this core’s RX FIFO is not empty …\nBit 2 - Sticky flag indicating the TX FIFO was written …\nBit 2 - Sticky flag indicating the TX FIFO was written …\nWrite access to this core’s TX FIFO\nRegister <code>FIFO_WR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>GPIO_HI_IN</code> reader - Input value on QSPI IO in order …\nInput value for QSPI pins\nRegister <code>GPIO_HI_IN</code> reader\nReturns the argument unchanged.\nBits 0:5 - Input value on QSPI IO in order 0..5: SCLK, …\nCalls <code>U::from(self)</code>.\nField <code>GPIO_HI_OE</code> reader - Set output enable (1/0 -&gt; …\nQSPI output enable\nField <code>GPIO_HI_OE</code> writer - Set output enable (1/0 -&gt; …\nRegister <code>GPIO_HI_OE</code> reader\nRegister <code>GPIO_HI_OE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Set output enable (1/0 -&gt; output/input) for …\nBits 0:5 - Set output enable (1/0 -&gt; output/input) for …\nCalls <code>U::from(self)</code>.\nQSPI output enable clear\nField <code>GPIO_HI_OE_CLR</code> writer - Perform an atomic bit-clear …\nRegister <code>GPIO_HI_OE_CLR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Perform an atomic bit-clear on GPIO_HI_OE, i.e. …\nCalls <code>U::from(self)</code>.\nQSPI output enable set\nField <code>GPIO_HI_OE_SET</code> writer - Perform an atomic bit-set on …\nRegister <code>GPIO_HI_OE_SET</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Perform an atomic bit-set on GPIO_HI_OE, i.e. …\nCalls <code>U::from(self)</code>.\nQSPI output enable XOR\nField <code>GPIO_HI_OE_XOR</code> writer - Perform an atomic bitwise …\nRegister <code>GPIO_HI_OE_XOR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OE, …\nCalls <code>U::from(self)</code>.\nField <code>GPIO_HI_OUT</code> reader - Set output level (1/0 -&gt; …\nQSPI output value\nField <code>GPIO_HI_OUT</code> writer - Set output level (1/0 -&gt; …\nRegister <code>GPIO_HI_OUT</code> reader\nRegister <code>GPIO_HI_OUT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Set output level (1/0 -&gt; high/low) for QSPI IO0…\nBits 0:5 - Set output level (1/0 -&gt; high/low) for QSPI IO0…\nCalls <code>U::from(self)</code>.\nQSPI output value clear\nField <code>GPIO_HI_OUT_CLR</code> writer - Perform an atomic bit-clear …\nRegister <code>GPIO_HI_OUT_CLR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Perform an atomic bit-clear on GPIO_HI_OUT, …\nCalls <code>U::from(self)</code>.\nQSPI output value set\nField <code>GPIO_HI_OUT_SET</code> writer - Perform an atomic bit-set …\nRegister <code>GPIO_HI_OUT_SET</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Perform an atomic bit-set on GPIO_HI_OUT, i.e. …\nCalls <code>U::from(self)</code>.\nQSPI output value XOR\nField <code>GPIO_HI_OUT_XOR</code> writer - Perform an atomic bitwise …\nRegister <code>GPIO_HI_OUT_XOR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:5 - Perform an atomic bitwise XOR on GPIO_HI_OUT, …\nCalls <code>U::from(self)</code>.\nField <code>GPIO_IN</code> reader - Input value for GPIO0…29\nInput value for GPIO pins\nRegister <code>GPIO_IN</code> reader\nReturns the argument unchanged.\nBits 0:29 - Input value for GPIO0…29\nCalls <code>U::from(self)</code>.\nField <code>GPIO_OE</code> reader - Set output enable (1/0 -&gt; …\nGPIO output enable\nField <code>GPIO_OE</code> writer - Set output enable (1/0 -&gt; …\nRegister <code>GPIO_OE</code> reader\nRegister <code>GPIO_OE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Set output enable (1/0 -&gt; output/input) for …\nBits 0:29 - Set output enable (1/0 -&gt; output/input) for …\nCalls <code>U::from(self)</code>.\nGPIO output enable clear\nField <code>GPIO_OE_CLR</code> writer - Perform an atomic bit-clear on …\nRegister <code>GPIO_OE_CLR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Perform an atomic bit-clear on GPIO_OE, i.e. …\nCalls <code>U::from(self)</code>.\nGPIO output enable set\nField <code>GPIO_OE_SET</code> writer - Perform an atomic bit-set on …\nRegister <code>GPIO_OE_SET</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Perform an atomic bit-set on GPIO_OE, i.e. …\nCalls <code>U::from(self)</code>.\nGPIO output enable XOR\nField <code>GPIO_OE_XOR</code> writer - Perform an atomic bitwise XOR …\nRegister <code>GPIO_OE_XOR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Perform an atomic bitwise XOR on GPIO_OE, i.e. …\nCalls <code>U::from(self)</code>.\nField <code>GPIO_OUT</code> reader - Set output level (1/0 -&gt; high/low) …\nGPIO output value\nField <code>GPIO_OUT</code> writer - Set output level (1/0 -&gt; high/low) …\nRegister <code>GPIO_OUT</code> reader\nRegister <code>GPIO_OUT</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Set output level (1/0 -&gt; high/low) for GPIO0……\nBits 0:29 - Set output level (1/0 -&gt; high/low) for GPIO0……\nCalls <code>U::from(self)</code>.\nGPIO output value clear\nField <code>GPIO_OUT_CLR</code> writer - Perform an atomic bit-clear on …\nRegister <code>GPIO_OUT_CLR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Perform an atomic bit-clear on GPIO_OUT, i.e. …\nCalls <code>U::from(self)</code>.\nGPIO output value set\nField <code>GPIO_OUT_SET</code> writer - Perform an atomic bit-set on …\nRegister <code>GPIO_OUT_SET</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Perform an atomic bit-set on GPIO_OUT, i.e. …\nCalls <code>U::from(self)</code>.\nGPIO output value XOR\nField <code>GPIO_OUT_XOR</code> writer - Perform an atomic bitwise XOR …\nRegister <code>GPIO_OUT_XOR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:29 - Perform an atomic bitwise XOR on GPIO_OUT, …\nCalls <code>U::from(self)</code>.\nRead/write access to accumulator 0\nRegister <code>INTERP0_ACCUM0</code> reader\nRegister <code>INTERP0_ACCUM0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>INTERP0_ACCUM0_ADD</code> reader -\nValues written here are atomically added to ACCUM0 Reading …\nField <code>INTERP0_ACCUM0_ADD</code> writer -\nRegister <code>INTERP0_ACCUM0_ADD</code> reader\nRegister <code>INTERP0_ACCUM0_ADD</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:23\nBits 0:23\nCalls <code>U::from(self)</code>.\nRead/write access to accumulator 1\nRegister <code>INTERP0_ACCUM1</code> reader\nRegister <code>INTERP0_ACCUM1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>INTERP0_ACCUM1_ADD</code> reader -\nValues written here are atomically added to ACCUM1 Reading …\nField <code>INTERP0_ACCUM1_ADD</code> writer -\nRegister <code>INTERP0_ACCUM1_ADD</code> reader\nRegister <code>INTERP0_ACCUM1_ADD</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:23\nBits 0:23\nCalls <code>U::from(self)</code>.\nRead/write access to BASE0 register.\nRegister <code>INTERP0_BASE0</code> reader\nRegister <code>INTERP0_BASE0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead/write access to BASE1 register.\nRegister <code>INTERP0_BASE1</code> reader\nRegister <code>INTERP0_BASE1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead/write access to BASE2 register.\nRegister <code>INTERP0_BASE2</code> reader\nRegister <code>INTERP0_BASE2</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nOn write, the lower 16 bits go to BASE0, upper bits to …\nRegister <code>INTERP0_BASE_1AND0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ADD_RAW</code> reader - If 1, mask + shift is bypassed for …\nField <code>ADD_RAW</code> writer - If 1, mask + shift is bypassed for …\nField <code>BLEND</code> reader - Only present on INTERP0 on each core. …\nField <code>BLEND</code> writer - Only present on INTERP0 on each core. …\nField <code>CROSS_INPUT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_INPUT</code> writer - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> writer - If 1, feed the opposite lane’…\nField <code>FORCE_MSB</code> reader - ORed into bits 29:28 of the lane …\nField <code>FORCE_MSB</code> writer - ORed into bits 29:28 of the lane …\nControl register for lane 0\nField <code>MASK_LSB</code> reader - The least-significant bit allowed …\nField <code>MASK_LSB</code> writer - The least-significant bit allowed …\nField <code>MASK_MSB</code> reader - The most-significant bit allowed …\nField <code>MASK_MSB</code> writer - The most-significant bit allowed …\nField <code>OVERF0</code> reader - Indicates if any masked-off MSBs in …\nField <code>OVERF1</code> reader - Indicates if any masked-off MSBs in …\nField <code>OVERF</code> reader - Set if either OVERF0 or OVERF1 is set.\nRegister <code>INTERP0_CTRL_LANE0</code> reader\nField <code>SHIFT</code> reader - Logical right-shift applied to …\nField <code>SHIFT</code> writer - Logical right-shift applied to …\nField <code>SIGNED</code> reader - If SIGNED is set, the shifted and …\nField <code>SIGNED</code> writer - If SIGNED is set, the shifted and …\nRegister <code>INTERP0_CTRL_LANE0</code> writer\nBit 18 - If 1, mask + shift is bypassed for LANE0 result. …\nBit 18 - If 1, mask + shift is bypassed for LANE0 result. …\nWrites raw bits to the register.\nBit 21 - Only present on INTERP0 on each core. If BLEND …\nBit 21 - Only present on INTERP0 on each core. If BLEND …\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBit 25 - Set if either OVERF0 or OVERF1 is set.\nBit 23 - Indicates if any masked-off MSBs in ACCUM0 are …\nBit 24 - Indicates if any masked-off MSBs in ACCUM1 are …\nBits 0:4 - Logical right-shift applied to accumulator …\nBits 0:4 - Logical right-shift applied to accumulator …\nBit 15 - If SIGNED is set, the shifted and masked …\nBit 15 - If SIGNED is set, the shifted and masked …\nField <code>ADD_RAW</code> reader - If 1, mask + shift is bypassed for …\nField <code>ADD_RAW</code> writer - If 1, mask + shift is bypassed for …\nField <code>CROSS_INPUT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_INPUT</code> writer - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> writer - If 1, feed the opposite lane’…\nField <code>FORCE_MSB</code> reader - ORed into bits 29:28 of the lane …\nField <code>FORCE_MSB</code> writer - ORed into bits 29:28 of the lane …\nControl register for lane 1\nField <code>MASK_LSB</code> reader - The least-significant bit allowed …\nField <code>MASK_LSB</code> writer - The least-significant bit allowed …\nField <code>MASK_MSB</code> reader - The most-significant bit allowed …\nField <code>MASK_MSB</code> writer - The most-significant bit allowed …\nRegister <code>INTERP0_CTRL_LANE1</code> reader\nField <code>SHIFT</code> reader - Logical right-shift applied to …\nField <code>SHIFT</code> writer - Logical right-shift applied to …\nField <code>SIGNED</code> reader - If SIGNED is set, the shifted and …\nField <code>SIGNED</code> writer - If SIGNED is set, the shifted and …\nRegister <code>INTERP0_CTRL_LANE1</code> writer\nBit 18 - If 1, mask + shift is bypassed for LANE1 result. …\nBit 18 - If 1, mask + shift is bypassed for LANE1 result. …\nWrites raw bits to the register.\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBits 0:4 - Logical right-shift applied to accumulator …\nBits 0:4 - Logical right-shift applied to accumulator …\nBit 15 - If SIGNED is set, the shifted and masked …\nBit 15 - If SIGNED is set, the shifted and masked …\nRead FULL result, without altering any internal state …\nRegister <code>INTERP0_PEEK_FULL</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE0 result, without altering any internal state …\nRegister <code>INTERP0_PEEK_LANE0</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE1 result, without altering any internal state …\nRegister <code>INTERP0_PEEK_LANE1</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead FULL result, and simultaneously write lane results to …\nRegister <code>INTERP0_POP_FULL</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE0 result, and simultaneously write lane results …\nRegister <code>INTERP0_POP_LANE0</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE1 result, and simultaneously write lane results …\nRegister <code>INTERP0_POP_LANE1</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead/write access to accumulator 0\nRegister <code>INTERP1_ACCUM0</code> reader\nRegister <code>INTERP1_ACCUM0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>INTERP1_ACCUM0_ADD</code> reader -\nValues written here are atomically added to ACCUM0 Reading …\nField <code>INTERP1_ACCUM0_ADD</code> writer -\nRegister <code>INTERP1_ACCUM0_ADD</code> reader\nRegister <code>INTERP1_ACCUM0_ADD</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:23\nBits 0:23\nCalls <code>U::from(self)</code>.\nRead/write access to accumulator 1\nRegister <code>INTERP1_ACCUM1</code> reader\nRegister <code>INTERP1_ACCUM1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>INTERP1_ACCUM1_ADD</code> reader -\nValues written here are atomically added to ACCUM1 Reading …\nField <code>INTERP1_ACCUM1_ADD</code> writer -\nRegister <code>INTERP1_ACCUM1_ADD</code> reader\nRegister <code>INTERP1_ACCUM1_ADD</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:23\nBits 0:23\nCalls <code>U::from(self)</code>.\nRead/write access to BASE0 register.\nRegister <code>INTERP1_BASE0</code> reader\nRegister <code>INTERP1_BASE0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead/write access to BASE1 register.\nRegister <code>INTERP1_BASE1</code> reader\nRegister <code>INTERP1_BASE1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead/write access to BASE2 register.\nRegister <code>INTERP1_BASE2</code> reader\nRegister <code>INTERP1_BASE2</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nOn write, the lower 16 bits go to BASE0, upper bits to …\nRegister <code>INTERP1_BASE_1AND0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ADD_RAW</code> reader - If 1, mask + shift is bypassed for …\nField <code>ADD_RAW</code> writer - If 1, mask + shift is bypassed for …\nField <code>CLAMP</code> reader - Only present on INTERP1 on each core. …\nField <code>CLAMP</code> writer - Only present on INTERP1 on each core. …\nField <code>CROSS_INPUT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_INPUT</code> writer - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> writer - If 1, feed the opposite lane’…\nField <code>FORCE_MSB</code> reader - ORed into bits 29:28 of the lane …\nField <code>FORCE_MSB</code> writer - ORed into bits 29:28 of the lane …\nControl register for lane 0\nField <code>MASK_LSB</code> reader - The least-significant bit allowed …\nField <code>MASK_LSB</code> writer - The least-significant bit allowed …\nField <code>MASK_MSB</code> reader - The most-significant bit allowed …\nField <code>MASK_MSB</code> writer - The most-significant bit allowed …\nField <code>OVERF0</code> reader - Indicates if any masked-off MSBs in …\nField <code>OVERF1</code> reader - Indicates if any masked-off MSBs in …\nField <code>OVERF</code> reader - Set if either OVERF0 or OVERF1 is set.\nRegister <code>INTERP1_CTRL_LANE0</code> reader\nField <code>SHIFT</code> reader - Logical right-shift applied to …\nField <code>SHIFT</code> writer - Logical right-shift applied to …\nField <code>SIGNED</code> reader - If SIGNED is set, the shifted and …\nField <code>SIGNED</code> writer - If SIGNED is set, the shifted and …\nRegister <code>INTERP1_CTRL_LANE0</code> writer\nBit 18 - If 1, mask + shift is bypassed for LANE0 result. …\nBit 18 - If 1, mask + shift is bypassed for LANE0 result. …\nWrites raw bits to the register.\nBit 22 - Only present on INTERP1 on each core. If CLAMP …\nBit 22 - Only present on INTERP1 on each core. If CLAMP …\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBit 25 - Set if either OVERF0 or OVERF1 is set.\nBit 23 - Indicates if any masked-off MSBs in ACCUM0 are …\nBit 24 - Indicates if any masked-off MSBs in ACCUM1 are …\nBits 0:4 - Logical right-shift applied to accumulator …\nBits 0:4 - Logical right-shift applied to accumulator …\nBit 15 - If SIGNED is set, the shifted and masked …\nBit 15 - If SIGNED is set, the shifted and masked …\nField <code>ADD_RAW</code> reader - If 1, mask + shift is bypassed for …\nField <code>ADD_RAW</code> writer - If 1, mask + shift is bypassed for …\nField <code>CROSS_INPUT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_INPUT</code> writer - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> reader - If 1, feed the opposite lane’…\nField <code>CROSS_RESULT</code> writer - If 1, feed the opposite lane’…\nField <code>FORCE_MSB</code> reader - ORed into bits 29:28 of the lane …\nField <code>FORCE_MSB</code> writer - ORed into bits 29:28 of the lane …\nControl register for lane 1\nField <code>MASK_LSB</code> reader - The least-significant bit allowed …\nField <code>MASK_LSB</code> writer - The least-significant bit allowed …\nField <code>MASK_MSB</code> reader - The most-significant bit allowed …\nField <code>MASK_MSB</code> writer - The most-significant bit allowed …\nRegister <code>INTERP1_CTRL_LANE1</code> reader\nField <code>SHIFT</code> reader - Logical right-shift applied to …\nField <code>SHIFT</code> writer - Logical right-shift applied to …\nField <code>SIGNED</code> reader - If SIGNED is set, the shifted and …\nField <code>SIGNED</code> writer - If SIGNED is set, the shifted and …\nRegister <code>INTERP1_CTRL_LANE1</code> writer\nBit 18 - If 1, mask + shift is bypassed for LANE1 result. …\nBit 18 - If 1, mask + shift is bypassed for LANE1 result. …\nWrites raw bits to the register.\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 16 - If 1, feed the opposite lane’s accumulator into …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBit 17 - If 1, feed the opposite lane’s result into this …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nBits 19:20 - ORed into bits 29:28 of the lane result …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 5:9 - The least-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBits 10:14 - The most-significant bit allowed to pass by …\nBits 0:4 - Logical right-shift applied to accumulator …\nBits 0:4 - Logical right-shift applied to accumulator …\nBit 15 - If SIGNED is set, the shifted and masked …\nBit 15 - If SIGNED is set, the shifted and masked …\nRead FULL result, without altering any internal state …\nRegister <code>INTERP1_PEEK_FULL</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE0 result, without altering any internal state …\nRegister <code>INTERP1_PEEK_LANE0</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE1 result, without altering any internal state …\nRegister <code>INTERP1_PEEK_LANE1</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead FULL result, and simultaneously write lane results to …\nRegister <code>INTERP1_POP_FULL</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE0 result, and simultaneously write lane results …\nRegister <code>INTERP1_POP_LANE0</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRead LANE1 result, and simultaneously write lane results …\nRegister <code>INTERP1_POP_LANE1</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SPINLOCK%s</code> reader\nReading from a spinlock address will:\nRegister <code>SPINLOCK%s</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SPINLOCK_ST</code> reader\nSpinlock state A bitmap containing the state of all 32 …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister block\nSSPCPSR (rw) register accessor: Clock prescale register, …\nSSPCR0 (rw) register accessor: Control register 0, SSPCR0 …\nSSPCR1 (rw) register accessor: Control register 1, SSPCR1 …\nSSPDMACR (rw) register accessor: DMA control register, …\nSSPDR (rw) register accessor: Data register, SSPDR on page …\nSSPICR (rw) register accessor: Interrupt clear register, …\nSSPIMSC (rw) register accessor: Interrupt mask set or …\nSSPMIS (r) register accessor: Masked interrupt status …\nSSPPCELLID0 (r) register accessor: PrimeCell …\nSSPPCELLID1 (r) register accessor: PrimeCell …\nSSPPCELLID2 (r) register accessor: PrimeCell …\nSSPPCELLID3 (r) register accessor: PrimeCell …\nSSPPERIPHID0 (r) register accessor: Peripheral …\nSSPPERIPHID1 (r) register accessor: Peripheral …\nSSPPERIPHID2 (r) register accessor: Peripheral …\nSSPPERIPHID3 (r) register accessor: Peripheral …\nSSPRIS (r) register accessor: Raw interrupt status …\nSSPSR (r) register accessor: Status register, SSPSR on …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nClock prescale register, SSPCPSR on page 3-8\n0x10 - Clock prescale register, SSPCPSR on page 3-8\nControl register 0, SSPCR0 on page 3-4\n0x00 - Control register 0, SSPCR0 on page 3-4\nControl register 1, SSPCR1 on page 3-5\n0x04 - Control register 1, SSPCR1 on page 3-5\nDMA control register, SSPDMACR on page 3-12\n0x24 - DMA control register, SSPDMACR on page 3-12\nData register, SSPDR on page 3-6\n0x08 - Data register, SSPDR on page 3-6\nInterrupt clear register, SSPICR on page 3-11\n0x20 - Interrupt clear register, SSPICR on page 3-11\nInterrupt mask set or clear register, SSPIMSC on page 3-9\n0x14 - Interrupt mask set or clear register, SSPIMSC on …\nMasked interrupt status register, SSPMIS on page 3-11\n0x1c - Masked interrupt status register, SSPMIS on page …\nPrimeCell identification registers, SSPPCellID0-3 on page …\n0xff0 - PrimeCell identification registers, SSPPCellID0-3 …\nPrimeCell identification registers, SSPPCellID0-3 on page …\n0xff4 - PrimeCell identification registers, SSPPCellID0-3 …\nPrimeCell identification registers, SSPPCellID0-3 on page …\n0xff8 - PrimeCell identification registers, SSPPCellID0-3 …\nPrimeCell identification registers, SSPPCellID0-3 on page …\n0xffc - PrimeCell identification registers, SSPPCellID0-3 …\nPeripheral identification registers, SSPPeriphID0-3 on …\n0xfe0 - Peripheral identification registers, …\nPeripheral identification registers, SSPPeriphID0-3 on …\n0xfe4 - Peripheral identification registers, …\nPeripheral identification registers, SSPPeriphID0-3 on …\n0xfe8 - Peripheral identification registers, …\nPeripheral identification registers, SSPPeriphID0-3 on …\n0xfec - Peripheral identification registers, …\nRaw interrupt status register, SSPRIS on page 3-10\n0x18 - Raw interrupt status register, SSPRIS on page 3-10\nStatus register, SSPSR on page 3-7\n0x0c - Status register, SSPSR on page 3-7\nField <code>CPSDVSR</code> reader - Clock prescale divisor. Must be an …\nField <code>CPSDVSR</code> writer - Clock prescale divisor. Must be an …\nRegister <code>SSPCPSR</code> reader\nClock prescale register, SSPCPSR on page 3-8\nRegister <code>SSPCPSR</code> writer\nWrites raw bits to the register.\nBits 0:7 - Clock prescale divisor. Must be an even number …\nBits 0:7 - Clock prescale divisor. Must be an even number …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DSS</code> reader - Data Size Select: 0000 Reserved, …\nField <code>DSS</code> writer - Data Size Select: 0000 Reserved, …\nFrame format.\nField <code>FRF</code> reader - Frame format.\nField <code>FRF</code> writer - Frame format.\n0: Motorola SPI frame format\n2: National Semiconductor Microwire frame format\nRegister <code>SSPCR0</code> reader\nField <code>SCR</code> reader - Serial clock rate. The value SCR is …\nField <code>SCR</code> writer - Serial clock rate. The value SCR is …\nField <code>SPH</code> reader - SSPCLKOUT phase, applicable to Motorola …\nField <code>SPH</code> writer - SSPCLKOUT phase, applicable to Motorola …\nField <code>SPO</code> reader - SSPCLKOUT polarity, applicable to …\nField <code>SPO</code> writer - SSPCLKOUT polarity, applicable to …\nControl register 0, SSPCR0 on page 3-4\n1: Texas Instruments synchronous serial frame format\nRegister <code>SSPCR0</code> writer\nWrites raw bits to the register.\nBits 0:3 - Data Size Select: 0000 Reserved, undefined …\nBits 0:3 - Data Size Select: 0000 Reserved, undefined …\nBits 4:5 - Frame format.\nBits 4:5 - Frame format.\nReturns the argument unchanged.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\nMotorola SPI frame format\nNational Semiconductor Microwire frame format\nTexas Instruments synchronous serial frame format\nMotorola SPI frame format\nNational Semiconductor Microwire frame format\nBits 8:15 - Serial clock rate. The value SCR is used to …\nBits 8:15 - Serial clock rate. The value SCR is used to …\nBit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame …\nBit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame …\nBit 6 - SSPCLKOUT polarity, applicable to Motorola SPI …\nBit 6 - SSPCLKOUT polarity, applicable to Motorola SPI …\nTexas Instruments synchronous serial frame format\nGet enumerated values variant\nField <code>LBM</code> reader - Loop back mode: 0 Normal serial port …\nField <code>LBM</code> writer - Loop back mode: 0 Normal serial port …\nField <code>MS</code> reader - Master or slave mode select. This bit …\nField <code>MS</code> writer - Master or slave mode select. This bit …\nRegister <code>SSPCR1</code> reader\nField <code>SOD</code> reader - Slave-mode output disable. This bit is …\nField <code>SOD</code> writer - Slave-mode output disable. This bit is …\nField <code>SSE</code> reader - Synchronous serial port enable: 0 SSP …\nField <code>SSE</code> writer - Synchronous serial port enable: 0 SSP …\nControl register 1, SSPCR1 on page 3-5\nRegister <code>SSPCR1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Loop back mode: 0 Normal serial port operation …\nBit 0 - Loop back mode: 0 Normal serial port operation …\nBit 2 - Master or slave mode select. This bit can be …\nBit 2 - Master or slave mode select. This bit can be …\nBit 3 - Slave-mode output disable. This bit is relevant …\nBit 3 - Slave-mode output disable. This bit is relevant …\nBit 1 - Synchronous serial port enable: 0 SSP operation …\nBit 1 - Synchronous serial port enable: 0 SSP operation …\nRegister <code>SSPDMACR</code> reader\nField <code>RXDMAE</code> reader - Receive DMA Enable. If this bit is …\nField <code>RXDMAE</code> writer - Receive DMA Enable. If this bit is …\nDMA control register, SSPDMACR on page 3-12\nField <code>TXDMAE</code> reader - Transmit DMA Enable. If this bit is …\nField <code>TXDMAE</code> writer - Transmit DMA Enable. If this bit is …\nRegister <code>SSPDMACR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Receive DMA Enable. If this bit is set to 1, DMA …\nBit 0 - Receive DMA Enable. If this bit is set to 1, DMA …\nBit 1 - Transmit DMA Enable. If this bit is set to 1, DMA …\nBit 1 - Transmit DMA Enable. If this bit is set to 1, DMA …\nField <code>DATA</code> reader - Transmit/Receive FIFO: Read Receive …\nField <code>DATA</code> writer - Transmit/Receive FIFO: Read Receive …\nRegister <code>SSPDR</code> reader\nData register, SSPDR on page 3-6\nRegister <code>SSPDR</code> writer\nWrites raw bits to the register.\nBits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. …\nBits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SSPICR</code> reader\nField <code>RORIC</code> reader - Clears the SSPRORINTR interrupt\nField <code>RORIC</code> writer - Clears the SSPRORINTR interrupt\nField <code>RTIC</code> reader - Clears the SSPRTINTR interrupt\nField <code>RTIC</code> writer - Clears the SSPRTINTR interrupt\nInterrupt clear register, SSPICR on page 3-11\nRegister <code>SSPICR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Clears the SSPRORINTR interrupt\nBit 0 - Clears the SSPRORINTR interrupt\nBit 1 - Clears the SSPRTINTR interrupt\nBit 1 - Clears the SSPRTINTR interrupt\nRegister <code>SSPIMSC</code> reader\nField <code>RORIM</code> reader - Receive overrun interrupt mask: 0 …\nField <code>RORIM</code> writer - Receive overrun interrupt mask: 0 …\nField <code>RTIM</code> reader - Receive timeout interrupt mask: 0 …\nField <code>RTIM</code> writer - Receive timeout interrupt mask: 0 …\nField <code>RXIM</code> reader - Receive FIFO interrupt mask: 0 Receive …\nField <code>RXIM</code> writer - Receive FIFO interrupt mask: 0 Receive …\nInterrupt mask set or clear register, SSPIMSC on page 3-9\nField <code>TXIM</code> reader - Transmit FIFO interrupt mask: 0 …\nField <code>TXIM</code> writer - Transmit FIFO interrupt mask: 0 …\nRegister <code>SSPIMSC</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Receive overrun interrupt mask: 0 Receive FIFO …\nBit 0 - Receive overrun interrupt mask: 0 Receive FIFO …\nBit 1 - Receive timeout interrupt mask: 0 Receive FIFO not …\nBit 1 - Receive timeout interrupt mask: 0 Receive FIFO not …\nBit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half …\nBit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half …\nBit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half …\nBit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half …\nRegister <code>SSPMIS</code> reader\nField <code>RORMIS</code> reader - Gives the receive over run masked …\nField <code>RTMIS</code> reader - Gives the receive timeout masked …\nField <code>RXMIS</code> reader - Gives the receive FIFO masked …\nMasked interrupt status register, SSPMIS on page 3-11\nField <code>TXMIS</code> reader - Gives the transmit FIFO masked …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Gives the receive over run masked interrupt …\nBit 1 - Gives the receive timeout masked interrupt state, …\nBit 2 - Gives the receive FIFO masked interrupt state, …\nBit 3 - Gives the transmit FIFO masked interrupt state, …\nRegister <code>SSPPCELLID0</code> reader\nField <code>SSPPCELLID0</code> reader - These bits read back as 0x0D\nPrimeCell identification registers, SSPPCellID0-3 on page …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0x0D\nRegister <code>SSPPCELLID1</code> reader\nField <code>SSPPCELLID1</code> reader - These bits read back as 0xF0\nPrimeCell identification registers, SSPPCellID0-3 on page …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0xF0\nRegister <code>SSPPCELLID2</code> reader\nField <code>SSPPCELLID2</code> reader - These bits read back as 0x05\nPrimeCell identification registers, SSPPCellID0-3 on page …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0x05\nRegister <code>SSPPCELLID3</code> reader\nField <code>SSPPCELLID3</code> reader - These bits read back as 0xB1\nPrimeCell identification registers, SSPPCellID0-3 on page …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0xB1\nField <code>PARTNUMBER0</code> reader - These bits read back as 0x22\nRegister <code>SSPPERIPHID0</code> reader\nPeripheral identification registers, SSPPeriphID0-3 on …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0x22\nField <code>DESIGNER0</code> reader - These bits read back as 0x1\nField <code>PARTNUMBER1</code> reader - These bits read back as 0x0\nRegister <code>SSPPERIPHID1</code> reader\nPeripheral identification registers, SSPPeriphID0-3 on …\nBits 4:7 - These bits read back as 0x1\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:3 - These bits read back as 0x0\nField <code>DESIGNER1</code> reader - These bits read back as 0x4\nRegister <code>SSPPERIPHID2</code> reader\nField <code>REVISION</code> reader - These bits return the peripheral …\nPeripheral identification registers, SSPPeriphID0-3 on …\nBits 0:3 - These bits read back as 0x4\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 4:7 - These bits return the peripheral revision\nField <code>CONFIGURATION</code> reader - These bits read back as 0x00\nRegister <code>SSPPERIPHID3</code> reader\nPeripheral identification registers, SSPPeriphID0-3 on …\nBits 0:7 - These bits read back as 0x00\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>SSPRIS</code> reader\nField <code>RORRIS</code> reader - Gives the raw interrupt state, prior …\nField <code>RTRIS</code> reader - Gives the raw interrupt state, prior …\nField <code>RXRIS</code> reader - Gives the raw interrupt state, prior …\nRaw interrupt status register, SSPRIS on page 3-10\nField <code>TXRIS</code> reader - Gives the raw interrupt state, prior …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Gives the raw interrupt state, prior to masking, …\nBit 1 - Gives the raw interrupt state, prior to masking, …\nBit 2 - Gives the raw interrupt state, prior to masking, …\nBit 3 - Gives the raw interrupt state, prior to masking, …\nField <code>BSY</code> reader - PrimeCell SSP busy flag, RO: 0 SSP is …\nRegister <code>SSPSR</code> reader\nField <code>RFF</code> reader - Receive FIFO full, RO: 0 Receive FIFO …\nField <code>RNE</code> reader - Receive FIFO not empty, RO: 0 Receive …\nStatus register, SSPSR on page 3-7\nField <code>TFE</code> reader - Transmit FIFO empty, RO: 0 Transmit …\nField <code>TNF</code> reader - Transmit FIFO not full, RO: 0 Transmit …\nBit 4 - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 3 - Receive FIFO full, RO: 0 Receive FIFO is not full. …\nBit 2 - Receive FIFO not empty, RO: 0 Receive FIFO is …\nBit 0 - Transmit FIFO empty, RO: 0 Transmit FIFO is not …\nBit 1 - Transmit FIFO not full, RO: 0 Transmit FIFO is …\nDBGFORCE (rw) register accessor: Directly control the SWD …\nMEMPOWERDOWN (rw) register accessor: Control power downs …\nPROC0_NMI_MASK (rw) register accessor: Processor core 0 …\nPROC1_NMI_MASK (rw) register accessor: Processor core 1 …\nPROC_CONFIG (rw) register accessor: Configuration for …\nPROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, …\nPROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each …\nRegister block\nDirectly control the SWD debug port of either processor\n0x14 - Directly control the SWD debug port of either …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nControl power downs to memories. Set high to power down …\n0x18 - Control power downs to memories. Set high to power …\nProcessor core 0 NMI source mask Set a bit high to enable …\n0x00 - Processor core 0 NMI source mask Set a bit high to …\nProcessor core 1 NMI source mask Set a bit high to enable …\n0x04 - Processor core 1 NMI source mask Set a bit high to …\nConfiguration for processors\n0x08 - Configuration for processors\nFor each bit, if 1, bypass the input synchronizer between …\n0x0c - For each bit, if 1, bypass the input synchronizer …\nFor each bit, if 1, bypass the input synchronizer between …\n0x10 - For each bit, if 1, bypass the input synchronizer …\nDirectly control the SWD debug port of either processor\nField <code>PROC0_ATTACH</code> reader - Attach processor 0 debug port …\nField <code>PROC0_ATTACH</code> writer - Attach processor 0 debug port …\nField <code>PROC0_SWCLK</code> reader - Directly drive processor 0 …\nField <code>PROC0_SWCLK</code> writer - Directly drive processor 0 …\nField <code>PROC0_SWDI</code> reader - Directly drive processor 0 SWDIO …\nField <code>PROC0_SWDI</code> writer - Directly drive processor 0 SWDIO …\nField <code>PROC0_SWDO</code> reader - Observe the value of processor 0 …\nField <code>PROC1_ATTACH</code> reader - Attach processor 1 debug port …\nField <code>PROC1_ATTACH</code> writer - Attach processor 1 debug port …\nField <code>PROC1_SWCLK</code> reader - Directly drive processor 1 …\nField <code>PROC1_SWCLK</code> writer - Directly drive processor 1 …\nField <code>PROC1_SWDI</code> reader - Directly drive processor 1 SWDIO …\nField <code>PROC1_SWDI</code> writer - Directly drive processor 1 SWDIO …\nField <code>PROC1_SWDO</code> reader - Observe the value of processor 1 …\nRegister <code>DBGFORCE</code> reader\nRegister <code>DBGFORCE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 3 - Attach processor 0 debug port to syscfg controls, …\nBit 3 - Attach processor 0 debug port to syscfg controls, …\nBit 2 - Directly drive processor 0 SWCLK, if PROC0_ATTACH …\nBit 2 - Directly drive processor 0 SWCLK, if PROC0_ATTACH …\nBit 1 - Directly drive processor 0 SWDIO input, if …\nBit 1 - Directly drive processor 0 SWDIO input, if …\nBit 0 - Observe the value of processor 0 SWDIO output.\nBit 7 - Attach processor 1 debug port to syscfg controls, …\nBit 7 - Attach processor 1 debug port to syscfg controls, …\nBit 6 - Directly drive processor 1 SWCLK, if PROC1_ATTACH …\nBit 6 - Directly drive processor 1 SWCLK, if PROC1_ATTACH …\nBit 5 - Directly drive processor 1 SWDIO input, if …\nBit 5 - Directly drive processor 1 SWDIO input, if …\nBit 4 - Observe the value of processor 1 SWDIO output.\nControl power downs to memories. Set high to power down …\nRegister <code>MEMPOWERDOWN</code> reader\nField <code>ROM</code> reader -\nField <code>ROM</code> writer -\nField <code>SRAM0</code> reader -\nField <code>SRAM0</code> writer -\nField <code>SRAM1</code> reader -\nField <code>SRAM1</code> writer -\nField <code>SRAM2</code> reader -\nField <code>SRAM2</code> writer -\nField <code>SRAM3</code> reader -\nField <code>SRAM3</code> writer -\nField <code>SRAM4</code> reader -\nField <code>SRAM4</code> writer -\nField <code>SRAM5</code> reader -\nField <code>SRAM5</code> writer -\nField <code>USB</code> reader -\nField <code>USB</code> writer -\nRegister <code>MEMPOWERDOWN</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 7\nBit 7\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nProcessor core 0 NMI source mask Set a bit high to enable …\nRegister <code>PROC0_NMI_MASK</code> reader\nRegister <code>PROC0_NMI_MASK</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nProcessor core 1 NMI source mask Set a bit high to enable …\nRegister <code>PROC1_NMI_MASK</code> reader\nRegister <code>PROC1_NMI_MASK</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>PROC0_DAP_INSTID</code> reader - Configure proc0 DAP …\nField <code>PROC0_DAP_INSTID</code> writer - Configure proc0 DAP …\nField <code>PROC0_HALTED</code> reader - Indication that proc0 has …\nField <code>PROC1_DAP_INSTID</code> reader - Configure proc1 DAP …\nField <code>PROC1_DAP_INSTID</code> writer - Configure proc1 DAP …\nField <code>PROC1_HALTED</code> reader - Indication that proc1 has …\nConfiguration for processors\nRegister <code>PROC_CONFIG</code> reader\nRegister <code>PROC_CONFIG</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 24:27 - Configure proc0 DAP instance ID. Recommend …\nBits 24:27 - Configure proc0 DAP instance ID. Recommend …\nBit 0 - Indication that proc0 has halted\nBits 28:31 - Configure proc1 DAP instance ID. Recommend …\nBits 28:31 - Configure proc1 DAP instance ID. Recommend …\nBit 1 - Indication that proc1 has halted\nField <code>PROC_IN_SYNC_BYPASS</code> reader -\nFor each bit, if 1, bypass the input synchronizer between …\nField <code>PROC_IN_SYNC_BYPASS</code> writer -\nRegister <code>PROC_IN_SYNC_BYPASS</code> reader\nRegister <code>PROC_IN_SYNC_BYPASS</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:29\nBits 0:29\nField <code>PROC_IN_SYNC_BYPASS_HI</code> reader -\nFor each bit, if 1, bypass the input synchronizer between …\nField <code>PROC_IN_SYNC_BYPASS_HI</code> writer -\nRegister <code>PROC_IN_SYNC_BYPASS_HI</code> reader\nRegister <code>PROC_IN_SYNC_BYPASS_HI</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:5\nBits 0:5\nCHIP_ID (r) register accessor: JEDEC JEP-106 compliant …\nGITREF_RP2040 (r) register accessor: Git hash of the chip …\nPLATFORM (r) register accessor: Platform register. Allows …\nRegister block\nJEDEC JEP-106 compliant chip identifier.\n0x00 - JEDEC JEP-106 compliant chip identifier.\nReturns the argument unchanged.\nGit hash of the chip source. Used to identify chip version.\n0x40 - Git hash of the chip source. Used to identify chip …\nCalls <code>U::from(self)</code>.\nPlatform register. Allows software to know what …\n0x04 - Platform register. Allows software to know what …\nJEDEC JEP-106 compliant chip identifier.\nField <code>MANUFACTURER</code> reader -\nField <code>PART</code> reader -\nRegister <code>CHIP_ID</code> reader\nField <code>REVISION</code> reader -\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:11\nBits 12:27\nBits 28:31\nGit hash of the chip source. Used to identify chip version.\nRegister <code>GITREF_RP2040</code> reader\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ASIC</code> reader -\nField <code>FPGA</code> reader -\nPlatform register. Allows software to know what …\nRegister <code>PLATFORM</code> reader\nBit 1\nBit 0\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nPLATFORM (r) register accessor: Indicates the type of …\nRegister block\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nIndicates the type of platform in use\n0x00 - Indicates the type of platform in use\nField <code>ASIC</code> reader - Indicates the platform is an ASIC\nField <code>FPGA</code> reader - Indicates the platform is an FPGA\nIndicates the type of platform in use\nRegister <code>PLATFORM</code> reader\nBit 0 - Indicates the platform is an ASIC\nBit 1 - Indicates the platform is an FPGA\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nALARM0 (rw) register accessor: Arm alarm 0, and configure …\nALARM1 (rw) register accessor: Arm alarm 1, and configure …\nALARM2 (rw) register accessor: Arm alarm 2, and configure …\nALARM3 (rw) register accessor: Arm alarm 3, and configure …\nARMED (rw) register accessor: Indicates the armed/disarmed …\nDBGPAUSE (rw) register accessor: Set bits high to enable …\nINTE (rw) register accessor: Interrupt Enable\nINTF (rw) register accessor: Interrupt Force\nINTR (rw) register accessor: Raw Interrupts\nINTS (r) register accessor: Interrupt status after masking …\nPAUSE (rw) register accessor: Set high to pause the timer\nRegister block\nTIMEHR (r) register accessor: Read from bits 63:32 of time …\nTIMEHW (w) register accessor: Write to bits 63:32 of time …\nTIMELR (r) register accessor: Read from bits 31:0 of time\nTIMELW (w) register accessor: Write to bits 31:0 of time …\nTIMERAWH (r) register accessor: Raw read from bits 63:32 …\nTIMERAWL (r) register accessor: Raw read from bits 31:0 of …\nArm alarm 0, and configure the time it will fire. Once …\n0x10 - Arm alarm 0, and configure the time it will fire. …\nArm alarm 1, and configure the time it will fire. Once …\n0x14 - Arm alarm 1, and configure the time it will fire. …\nArm alarm 2, and configure the time it will fire. Once …\n0x18 - Arm alarm 2, and configure the time it will fire. …\nArm alarm 3, and configure the time it will fire. Once …\n0x1c - Arm alarm 3, and configure the time it will fire. …\nIndicates the armed/disarmed status of each alarm. A write …\n0x20 - Indicates the armed/disarmed status of each alarm. …\nSet bits high to enable pause when the corresponding debug …\n0x2c - Set bits high to enable pause when the …\nReturns the argument unchanged.\nInterrupt Enable\n0x38 - Interrupt Enable\nInterrupt Force\n0x3c - Interrupt Force\nCalls <code>U::from(self)</code>.\nRaw Interrupts\n0x34 - Raw Interrupts\nInterrupt status after masking &amp; forcing\n0x40 - Interrupt status after masking &amp; forcing\nSet high to pause the timer\n0x30 - Set high to pause the timer\nRead from bits 63:32 of time always read timelr before …\n0x08 - Read from bits 63:32 of time always read timelr …\nWrite to bits 63:32 of time always write timelw before …\n0x00 - Write to bits 63:32 of time always write timelw …\nRead from bits 31:0 of time\n0x0c - Read from bits 31:0 of time\nWrite to bits 31:0 of time writes do not get copied to …\n0x04 - Write to bits 31:0 of time writes do not get copied …\nRaw read from bits 63:32 of time (no side effects)\n0x24 - Raw read from bits 63:32 of time (no side effects)\nRaw read from bits 31:0 of time (no side effects)\n0x28 - Raw read from bits 31:0 of time (no side effects)\nArm alarm 0, and configure the time it will fire. Once …\nRegister <code>ALARM0</code> reader\nRegister <code>ALARM0</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nArm alarm 1, and configure the time it will fire. Once …\nRegister <code>ALARM1</code> reader\nRegister <code>ALARM1</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nArm alarm 2, and configure the time it will fire. Once …\nRegister <code>ALARM2</code> reader\nRegister <code>ALARM2</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nArm alarm 3, and configure the time it will fire. Once …\nRegister <code>ALARM3</code> reader\nRegister <code>ALARM3</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ARMED</code> reader -\nIndicates the armed/disarmed status of each alarm. A write …\nField <code>ARMED</code> writer -\nRegister <code>ARMED</code> reader\nRegister <code>ARMED</code> writer\nBits 0:3\nBits 0:3\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>DBG0</code> reader - Pause when processor 0 is in debug mode\nField <code>DBG0</code> writer - Pause when processor 0 is in debug mode\nField <code>DBG1</code> reader - Pause when processor 1 is in debug mode\nField <code>DBG1</code> writer - Pause when processor 1 is in debug mode\nSet bits high to enable pause when the corresponding debug …\nRegister <code>DBGPAUSE</code> reader\nRegister <code>DBGPAUSE</code> writer\nWrites raw bits to the register.\nBit 1 - Pause when processor 0 is in debug mode\nBit 1 - Pause when processor 0 is in debug mode\nBit 2 - Pause when processor 1 is in debug mode\nBit 2 - Pause when processor 1 is in debug mode\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ALARM_0</code> reader -\nField <code>ALARM_0</code> writer -\nField <code>ALARM_1</code> reader -\nField <code>ALARM_1</code> writer -\nField <code>ALARM_2</code> reader -\nField <code>ALARM_2</code> writer -\nField <code>ALARM_3</code> reader -\nField <code>ALARM_3</code> writer -\nInterrupt Enable\nRegister <code>INTE</code> reader\nRegister <code>INTE</code> writer\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ALARM_0</code> reader -\nField <code>ALARM_0</code> writer -\nField <code>ALARM_1</code> reader -\nField <code>ALARM_1</code> writer -\nField <code>ALARM_2</code> reader -\nField <code>ALARM_2</code> writer -\nField <code>ALARM_3</code> reader -\nField <code>ALARM_3</code> writer -\nInterrupt Force\nRegister <code>INTF</code> reader\nRegister <code>INTF</code> writer\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ALARM_0</code> reader -\nField <code>ALARM_0</code> writer -\nField <code>ALARM_1</code> reader -\nField <code>ALARM_1</code> writer -\nField <code>ALARM_2</code> reader -\nField <code>ALARM_2</code> writer -\nField <code>ALARM_3</code> reader -\nField <code>ALARM_3</code> writer -\nRaw Interrupts\nRegister <code>INTR</code> reader\nRegister <code>INTR</code> writer\nBit 0\nBit 0\nBit 1\nBit 1\nBit 2\nBit 2\nBit 3\nBit 3\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>ALARM_0</code> reader -\nField <code>ALARM_1</code> reader -\nField <code>ALARM_2</code> reader -\nField <code>ALARM_3</code> reader -\nInterrupt status after masking &amp; forcing\nRegister <code>INTS</code> reader\nBit 0\nBit 1\nBit 2\nBit 3\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>PAUSE</code> reader -\nSet high to pause the timer\nField <code>PAUSE</code> writer -\nRegister <code>PAUSE</code> reader\nRegister <code>PAUSE</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0\nBit 0\nRegister <code>TIMEHR</code> reader\nRead from bits 63:32 of time always read timelr before …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nWrite to bits 63:32 of time always write timelw before …\nRegister <code>TIMEHW</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>TIMELR</code> reader\nRead from bits 31:0 of time\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nWrite to bits 31:0 of time writes do not get copied to …\nRegister <code>TIMELW</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>TIMERAWH</code> reader\nRaw read from bits 63:32 of time (no side effects)\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister <code>TIMERAWL</code> reader\nRaw read from bits 31:0 of time (no side effects)\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nRegister block\nUARTCR (rw) register accessor: Control Register, UARTCR\nUARTDMACR (rw) register accessor: DMA Control Register, …\nUARTDR (rw) register accessor: Data Register, UARTDR\nUARTFBRD (rw) register accessor: Fractional Baud Rate …\nUARTFR (r) register accessor: Flag Register, UARTFR\nUARTIBRD (rw) register accessor: Integer Baud Rate …\nUARTICR (rw) register accessor: Interrupt Clear Register, …\nUARTIFLS (rw) register accessor: Interrupt FIFO Level …\nUARTILPR (rw) register accessor: IrDA Low-Power Counter …\nUARTIMSC (rw) register accessor: Interrupt Mask Set/Clear …\nUARTLCR_H (rw) register accessor: Line Control Register, …\nUARTMIS (r) register accessor: Masked Interrupt Status …\nUARTPCELLID0 (r) register accessor: UARTPCellID0 Register\nUARTPCELLID1 (r) register accessor: UARTPCellID1 Register\nUARTPCELLID2 (r) register accessor: UARTPCellID2 Register\nUARTPCELLID3 (r) register accessor: UARTPCellID3 Register\nUARTPERIPHID0 (r) register accessor: UARTPeriphID0 Register\nUARTPERIPHID1 (r) register accessor: UARTPeriphID1 Register\nUARTPERIPHID2 (r) register accessor: UARTPeriphID2 Register\nUARTPERIPHID3 (r) register accessor: UARTPeriphID3 Register\nUARTRIS (r) register accessor: Raw Interrupt Status …\nUARTRSR (rw) register accessor: Receive Status …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nControl Register, UARTCR\n0x30 - Control Register, UARTCR\nDMA Control Register, UARTDMACR\n0x48 - DMA Control Register, UARTDMACR\nData Register, UARTDR\n0x00 - Data Register, UARTDR\nFractional Baud Rate Register, UARTFBRD\n0x28 - Fractional Baud Rate Register, UARTFBRD\nFlag Register, UARTFR\n0x18 - Flag Register, UARTFR\nInteger Baud Rate Register, UARTIBRD\n0x24 - Integer Baud Rate Register, UARTIBRD\nInterrupt Clear Register, UARTICR\n0x44 - Interrupt Clear Register, UARTICR\nInterrupt FIFO Level Select Register, UARTIFLS\n0x34 - Interrupt FIFO Level Select Register, UARTIFLS\nIrDA Low-Power Counter Register, UARTILPR\n0x20 - IrDA Low-Power Counter Register, UARTILPR\nInterrupt Mask Set/Clear Register, UARTIMSC\n0x38 - Interrupt Mask Set/Clear Register, UARTIMSC\nLine Control Register, UARTLCR_H\n0x2c - Line Control Register, UARTLCR_H\nMasked Interrupt Status Register, UARTMIS\n0x40 - Masked Interrupt Status Register, UARTMIS\nUARTPCellID0 Register\n0xff0 - UARTPCellID0 Register\nUARTPCellID1 Register\n0xff4 - UARTPCellID1 Register\nUARTPCellID2 Register\n0xff8 - UARTPCellID2 Register\nUARTPCellID3 Register\n0xffc - UARTPCellID3 Register\nUARTPeriphID0 Register\n0xfe0 - UARTPeriphID0 Register\nUARTPeriphID1 Register\n0xfe4 - UARTPeriphID1 Register\nUARTPeriphID2 Register\n0xfe8 - UARTPeriphID2 Register\nUARTPeriphID3 Register\n0xfec - UARTPeriphID3 Register\nRaw Interrupt Status Register, UARTRIS\n0x3c - Raw Interrupt Status Register, UARTRIS\nReceive Status Register/Error Clear Register, …\n0x04 - Receive Status Register/Error Clear Register, …\nField <code>CTSEN</code> reader - CTS hardware flow control enable. If …\nField <code>CTSEN</code> writer - CTS hardware flow control enable. If …\nField <code>DTR</code> reader - Data transmit ready. This bit is the …\nField <code>DTR</code> writer - Data transmit ready. This bit is the …\nField <code>LBE</code> reader - Loopback enable. If this bit is set to …\nField <code>LBE</code> writer - Loopback enable. If this bit is set to …\nField <code>OUT1</code> reader - This bit is the complement of the UART …\nField <code>OUT1</code> writer - This bit is the complement of the UART …\nField <code>OUT2</code> reader - This bit is the complement of the UART …\nField <code>OUT2</code> writer - This bit is the complement of the UART …\nRegister <code>UARTCR</code> reader\nField <code>RTSEN</code> reader - RTS hardware flow control enable. If …\nField <code>RTSEN</code> writer - RTS hardware flow control enable. If …\nField <code>RTS</code> reader - Request to send. This bit is the …\nField <code>RTS</code> writer - Request to send. This bit is the …\nField <code>RXE</code> reader - Receive enable. If this bit is set to …\nField <code>RXE</code> writer - Receive enable. If this bit is set to …\nField <code>SIREN</code> reader - SIR enable: 0 = IrDA SIR ENDEC is …\nField <code>SIREN</code> writer - SIR enable: 0 = IrDA SIR ENDEC is …\nField <code>SIRLP</code> reader - SIR low-power IrDA mode. This bit …\nField <code>SIRLP</code> writer - SIR low-power IrDA mode. This bit …\nField <code>TXE</code> reader - Transmit enable. If this bit is set to …\nField <code>TXE</code> writer - Transmit enable. If this bit is set to …\nControl Register, UARTCR\nField <code>UARTEN</code> reader - UART enable: 0 = UART is disabled. …\nField <code>UARTEN</code> writer - UART enable: 0 = UART is disabled. …\nRegister <code>UARTCR</code> writer\nWrites raw bits to the register.\nBit 15 - CTS hardware flow control enable. If this bit is …\nBit 15 - CTS hardware flow control enable. If this bit is …\nBit 10 - Data transmit ready. This bit is the complement …\nBit 10 - Data transmit ready. This bit is the complement …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 7 - Loopback enable. If this bit is set to 1 and the …\nBit 7 - Loopback enable. If this bit is set to 1 and the …\nBit 12 - This bit is the complement of the UART Out1 …\nBit 12 - This bit is the complement of the UART Out1 …\nBit 13 - This bit is the complement of the UART Out2 …\nBit 13 - This bit is the complement of the UART Out2 …\nBit 11 - Request to send. This bit is the complement of …\nBit 11 - Request to send. This bit is the complement of …\nBit 14 - RTS hardware flow control enable. If this bit is …\nBit 14 - RTS hardware flow control enable. If this bit is …\nBit 9 - Receive enable. If this bit is set to 1, the …\nBit 9 - Receive enable. If this bit is set to 1, the …\nBit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. …\nBit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. …\nBit 2 - SIR low-power IrDA mode. This bit selects the IrDA …\nBit 2 - SIR low-power IrDA mode. This bit selects the IrDA …\nBit 8 - Transmit enable. If this bit is set to 1, the …\nBit 8 - Transmit enable. If this bit is set to 1, the …\nBit 0 - UART enable: 0 = UART is disabled. If the UART is …\nBit 0 - UART enable: 0 = UART is disabled. If the UART is …\nField <code>DMAONERR</code> reader - DMA on error. If this bit is set …\nField <code>DMAONERR</code> writer - DMA on error. If this bit is set …\nRegister <code>UARTDMACR</code> reader\nField <code>RXDMAE</code> reader - Receive DMA enable. If this bit is …\nField <code>RXDMAE</code> writer - Receive DMA enable. If this bit is …\nField <code>TXDMAE</code> reader - Transmit DMA enable. If this bit is …\nField <code>TXDMAE</code> writer - Transmit DMA enable. If this bit is …\nDMA Control Register, UARTDMACR\nRegister <code>UARTDMACR</code> writer\nWrites raw bits to the register.\nBit 2 - DMA on error. If this bit is set to 1, the DMA …\nBit 2 - DMA on error. If this bit is set to 1, the DMA …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 0 - Receive DMA enable. If this bit is set to 1, DMA …\nBit 0 - Receive DMA enable. If this bit is set to 1, DMA …\nBit 1 - Transmit DMA enable. If this bit is set to 1, DMA …\nBit 1 - Transmit DMA enable. If this bit is set to 1, DMA …\nField <code>BE</code> reader - Break error. This bit is set to 1 if a …\nField <code>DATA</code> reader - Receive (read) data character. …\nField <code>DATA</code> writer - Receive (read) data character. …\nField <code>FE</code> reader - Framing error. When set to 1, it …\nField <code>OE</code> reader - Overrun error. This bit is set to 1 if …\nField <code>PE</code> reader - Parity error. When set to 1, it …\nRegister <code>UARTDR</code> reader\nData Register, UARTDR\nRegister <code>UARTDR</code> writer\nBit 10 - Break error. This bit is set to 1 if a break …\nWrites raw bits to the register.\nBits 0:7 - Receive (read) data character. Transmit (write) …\nBits 0:7 - Receive (read) data character. Transmit (write) …\nBit 8 - Framing error. When set to 1, it indicates that …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 11 - Overrun error. This bit is set to 1 if data is …\nBit 9 - Parity error. When set to 1, it indicates that the …\nField <code>BAUD_DIVFRAC</code> reader - The fractional baud rate …\nField <code>BAUD_DIVFRAC</code> writer - The fractional baud rate …\nRegister <code>UARTFBRD</code> reader\nFractional Baud Rate Register, UARTFBRD\nRegister <code>UARTFBRD</code> writer\nBits 0:5 - The fractional baud rate divisor. These bits …\nBits 0:5 - The fractional baud rate divisor. These bits …\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>BUSY</code> reader - UART busy. If this bit is set to 1, …\nField <code>CTS</code> reader - Clear to send. This bit is the …\nField <code>DCD</code> reader - Data carrier detect. This bit is the …\nField <code>DSR</code> reader - Data set ready. This bit is the …\nRegister <code>UARTFR</code> reader\nField <code>RI</code> reader - Ring indicator. This bit is the …\nField <code>RXFE</code> reader - Receive FIFO empty. The meaning of …\nField <code>RXFF</code> reader - Receive FIFO full. The meaning of this …\nField <code>TXFE</code> reader - Transmit FIFO empty. The meaning of …\nField <code>TXFF</code> reader - Transmit FIFO full. The meaning of …\nFlag Register, UARTFR\nBit 3 - UART busy. If this bit is set to 1, the UART is …\nBit 0 - Clear to send. This bit is the complement of the …\nBit 2 - Data carrier detect. This bit is the complement of …\nBit 1 - Data set ready. This bit is the complement of the …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 8 - Ring indicator. This bit is the complement of the …\nBit 4 - Receive FIFO empty. The meaning of this bit …\nBit 6 - Receive FIFO full. The meaning of this bit depends …\nBit 7 - Transmit FIFO empty. The meaning of this bit …\nBit 5 - Transmit FIFO full. The meaning of this bit …\nField <code>BAUD_DIVINT</code> reader - The integer baud rate divisor. …\nField <code>BAUD_DIVINT</code> writer - The integer baud rate divisor. …\nRegister <code>UARTIBRD</code> reader\nInteger Baud Rate Register, UARTIBRD\nRegister <code>UARTIBRD</code> writer\nBits 0:15 - The integer baud rate divisor. These bits are …\nBits 0:15 - The integer baud rate divisor. These bits are …\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>BEIC</code> reader - Break error interrupt clear. Clears …\nField <code>BEIC</code> writer - Break error interrupt clear. Clears …\nField <code>CTSMIC</code> reader - nUARTCTS modem interrupt clear. …\nField <code>CTSMIC</code> writer - nUARTCTS modem interrupt clear. …\nField <code>DCDMIC</code> reader - nUARTDCD modem interrupt clear. …\nField <code>DCDMIC</code> writer - nUARTDCD modem interrupt clear. …\nField <code>DSRMIC</code> reader - nUARTDSR modem interrupt clear. …\nField <code>DSRMIC</code> writer - nUARTDSR modem interrupt clear. …\nField <code>FEIC</code> reader - Framing error interrupt clear. Clears …\nField <code>FEIC</code> writer - Framing error interrupt clear. Clears …\nField <code>OEIC</code> reader - Overrun error interrupt clear. Clears …\nField <code>OEIC</code> writer - Overrun error interrupt clear. Clears …\nField <code>PEIC</code> reader - Parity error interrupt clear. Clears …\nField <code>PEIC</code> writer - Parity error interrupt clear. Clears …\nRegister <code>UARTICR</code> reader\nField <code>RIMIC</code> reader - nUARTRI modem interrupt clear. Clears …\nField <code>RIMIC</code> writer - nUARTRI modem interrupt clear. Clears …\nField <code>RTIC</code> reader - Receive timeout interrupt clear. …\nField <code>RTIC</code> writer - Receive timeout interrupt clear. …\nField <code>RXIC</code> reader - Receive interrupt clear. Clears the …\nField <code>RXIC</code> writer - Receive interrupt clear. Clears the …\nField <code>TXIC</code> reader - Transmit interrupt clear. Clears the …\nField <code>TXIC</code> writer - Transmit interrupt clear. Clears the …\nInterrupt Clear Register, UARTICR\nRegister <code>UARTICR</code> writer\nBit 9 - Break error interrupt clear. Clears the UARTBEINTR …\nBit 9 - Break error interrupt clear. Clears the UARTBEINTR …\nWrites raw bits to the register.\nBit 1 - nUARTCTS modem interrupt clear. Clears the …\nBit 1 - nUARTCTS modem interrupt clear. Clears the …\nBit 2 - nUARTDCD modem interrupt clear. Clears the …\nBit 2 - nUARTDCD modem interrupt clear. Clears the …\nBit 3 - nUARTDSR modem interrupt clear. Clears the …\nBit 3 - nUARTDSR modem interrupt clear. Clears the …\nBit 7 - Framing error interrupt clear. Clears the …\nBit 7 - Framing error interrupt clear. Clears the …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 10 - Overrun error interrupt clear. Clears the …\nBit 10 - Overrun error interrupt clear. Clears the …\nBit 8 - Parity error interrupt clear. Clears the …\nBit 8 - Parity error interrupt clear. Clears the …\nBit 0 - nUARTRI modem interrupt clear. Clears the …\nBit 0 - nUARTRI modem interrupt clear. Clears the …\nBit 6 - Receive timeout interrupt clear. Clears the …\nBit 6 - Receive timeout interrupt clear. Clears the …\nBit 4 - Receive interrupt clear. Clears the UARTRXINTR …\nBit 4 - Receive interrupt clear. Clears the UARTRXINTR …\nBit 5 - Transmit interrupt clear. Clears the UARTTXINTR …\nBit 5 - Transmit interrupt clear. Clears the UARTTXINTR …\nRegister <code>UARTIFLS</code> reader\nField <code>RXIFLSEL</code> reader - Receive interrupt FIFO level …\nField <code>RXIFLSEL</code> writer - Receive interrupt FIFO level …\nField <code>TXIFLSEL</code> reader - Transmit interrupt FIFO level …\nField <code>TXIFLSEL</code> writer - Transmit interrupt FIFO level …\nInterrupt FIFO Level Select Register, UARTIFLS\nRegister <code>UARTIFLS</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 3:5 - Receive interrupt FIFO level select. The …\nBits 3:5 - Receive interrupt FIFO level select. The …\nBits 0:2 - Transmit interrupt FIFO level select. The …\nBits 0:2 - Transmit interrupt FIFO level select. The …\nField <code>ILPDVSR</code> reader - 8-bit low-power divisor value. …\nField <code>ILPDVSR</code> writer - 8-bit low-power divisor value. …\nRegister <code>UARTILPR</code> reader\nIrDA Low-Power Counter Register, UARTILPR\nRegister <code>UARTILPR</code> writer\nWrites raw bits to the register.\nReturns the argument unchanged.\nBits 0:7 - 8-bit low-power divisor value. These bits are …\nBits 0:7 - 8-bit low-power divisor value. These bits are …\nCalls <code>U::from(self)</code>.\nField <code>BEIM</code> reader - Break error interrupt mask. A read …\nField <code>BEIM</code> writer - Break error interrupt mask. A read …\nField <code>CTSMIM</code> reader - nUARTCTS modem interrupt mask. A …\nField <code>CTSMIM</code> writer - nUARTCTS modem interrupt mask. A …\nField <code>DCDMIM</code> reader - nUARTDCD modem interrupt mask. A …\nField <code>DCDMIM</code> writer - nUARTDCD modem interrupt mask. A …\nField <code>DSRMIM</code> reader - nUARTDSR modem interrupt mask. A …\nField <code>DSRMIM</code> writer - nUARTDSR modem interrupt mask. A …\nField <code>FEIM</code> reader - Framing error interrupt mask. A read …\nField <code>FEIM</code> writer - Framing error interrupt mask. A read …\nField <code>OEIM</code> reader - Overrun error interrupt mask. A read …\nField <code>OEIM</code> writer - Overrun error interrupt mask. A read …\nField <code>PEIM</code> reader - Parity error interrupt mask. A read …\nField <code>PEIM</code> writer - Parity error interrupt mask. A read …\nRegister <code>UARTIMSC</code> reader\nField <code>RIMIM</code> reader - nUARTRI modem interrupt mask. A read …\nField <code>RIMIM</code> writer - nUARTRI modem interrupt mask. A read …\nField <code>RTIM</code> reader - Receive timeout interrupt mask. A read …\nField <code>RTIM</code> writer - Receive timeout interrupt mask. A read …\nField <code>RXIM</code> reader - Receive interrupt mask. A read returns …\nField <code>RXIM</code> writer - Receive interrupt mask. A read returns …\nField <code>TXIM</code> reader - Transmit interrupt mask. A read …\nField <code>TXIM</code> writer - Transmit interrupt mask. A read …\nInterrupt Mask Set/Clear Register, UARTIMSC\nRegister <code>UARTIMSC</code> writer\nBit 9 - Break error interrupt mask. A read returns the …\nBit 9 - Break error interrupt mask. A read returns the …\nWrites raw bits to the register.\nBit 1 - nUARTCTS modem interrupt mask. A read returns the …\nBit 1 - nUARTCTS modem interrupt mask. A read returns the …\nBit 2 - nUARTDCD modem interrupt mask. A read returns the …\nBit 2 - nUARTDCD modem interrupt mask. A read returns the …\nBit 3 - nUARTDSR modem interrupt mask. A read returns the …\nBit 3 - nUARTDSR modem interrupt mask. A read returns the …\nBit 7 - Framing error interrupt mask. A read returns the …\nBit 7 - Framing error interrupt mask. A read returns the …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 10 - Overrun error interrupt mask. A read returns the …\nBit 10 - Overrun error interrupt mask. A read returns the …\nBit 8 - Parity error interrupt mask. A read returns the …\nBit 8 - Parity error interrupt mask. A read returns the …\nBit 0 - nUARTRI modem interrupt mask. A read returns the …\nBit 0 - nUARTRI modem interrupt mask. A read returns the …\nBit 6 - Receive timeout interrupt mask. A read returns the …\nBit 6 - Receive timeout interrupt mask. A read returns the …\nBit 4 - Receive interrupt mask. A read returns the current …\nBit 4 - Receive interrupt mask. A read returns the current …\nBit 5 - Transmit interrupt mask. A read returns the …\nBit 5 - Transmit interrupt mask. A read returns the …\nField <code>BRK</code> reader - Send break. If this bit is set to 1, a …\nField <code>BRK</code> writer - Send break. If this bit is set to 1, a …\nField <code>EPS</code> reader - Even parity select. Controls the type …\nField <code>EPS</code> writer - Even parity select. Controls the type …\nField <code>FEN</code> reader - Enable FIFOs: 0 = FIFOs are disabled …\nField <code>FEN</code> writer - Enable FIFOs: 0 = FIFOs are disabled …\nField <code>PEN</code> reader - Parity enable: 0 = parity is disabled …\nField <code>PEN</code> writer - Parity enable: 0 = parity is disabled …\nRegister <code>UARTLCR_H</code> reader\nField <code>SPS</code> reader - Stick parity select. 0 = stick parity …\nField <code>SPS</code> writer - Stick parity select. 0 = stick parity …\nField <code>STP2</code> reader - Two stop bits select. If this bit is …\nField <code>STP2</code> writer - Two stop bits select. If this bit is …\nLine Control Register, UARTLCR_H\nRegister <code>UARTLCR_H</code> writer\nField <code>WLEN</code> reader - Word length. These bits indicate the …\nField <code>WLEN</code> writer - Word length. These bits indicate the …\nWrites raw bits to the register.\nBit 0 - Send break. If this bit is set to 1, a low-level …\nBit 0 - Send break. If this bit is set to 1, a low-level …\nBit 2 - Even parity select. Controls the type of parity …\nBit 2 - Even parity select. Controls the type of parity …\nBit 4 - Enable FIFOs: 0 = FIFOs are disabled (character …\nBit 4 - Enable FIFOs: 0 = FIFOs are disabled (character …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 1 - Parity enable: 0 = parity is disabled and no …\nBit 1 - Parity enable: 0 = parity is disabled and no …\nBit 7 - Stick parity select. 0 = stick parity is disabled …\nBit 7 - Stick parity select. 0 = stick parity is disabled …\nBit 3 - Two stop bits select. If this bit is set to 1, two …\nBit 3 - Two stop bits select. If this bit is set to 1, two …\nBits 5:6 - Word length. These bits indicate the number of …\nBits 5:6 - Word length. These bits indicate the number of …\nField <code>BEMIS</code> reader - Break error masked interrupt status. …\nField <code>CTSMMIS</code> reader - nUARTCTS modem masked interrupt …\nField <code>DCDMMIS</code> reader - nUARTDCD modem masked interrupt …\nField <code>DSRMMIS</code> reader - nUARTDSR modem masked interrupt …\nField <code>FEMIS</code> reader - Framing error masked interrupt …\nField <code>OEMIS</code> reader - Overrun error masked interrupt …\nField <code>PEMIS</code> reader - Parity error masked interrupt status. …\nRegister <code>UARTMIS</code> reader\nField <code>RIMMIS</code> reader - nUARTRI modem masked interrupt …\nField <code>RTMIS</code> reader - Receive timeout masked interrupt …\nField <code>RXMIS</code> reader - Receive masked interrupt status. …\nField <code>TXMIS</code> reader - Transmit masked interrupt status. …\nMasked Interrupt Status Register, UARTMIS\nBit 9 - Break error masked interrupt status. Returns the …\nBit 1 - nUARTCTS modem masked interrupt status. Returns …\nBit 2 - nUARTDCD modem masked interrupt status. Returns …\nBit 3 - nUARTDSR modem masked interrupt status. Returns …\nBit 7 - Framing error masked interrupt status. Returns the …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 10 - Overrun error masked interrupt status. Returns …\nBit 8 - Parity error masked interrupt status. Returns the …\nBit 0 - nUARTRI modem masked interrupt status. Returns the …\nBit 6 - Receive timeout masked interrupt status. Returns …\nBit 4 - Receive masked interrupt status. Returns the …\nBit 5 - Transmit masked interrupt status. Returns the …\nRegister <code>UARTPCELLID0</code> reader\nField <code>UARTPCELLID0</code> reader - These bits read back as 0x0D\nUARTPCellID0 Register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0x0D\nRegister <code>UARTPCELLID1</code> reader\nField <code>UARTPCELLID1</code> reader - These bits read back as 0xF0\nUARTPCellID1 Register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0xF0\nRegister <code>UARTPCELLID2</code> reader\nField <code>UARTPCELLID2</code> reader - These bits read back as 0x05\nUARTPCellID2 Register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0x05\nRegister <code>UARTPCELLID3</code> reader\nField <code>UARTPCELLID3</code> reader - These bits read back as 0xB1\nUARTPCellID3 Register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0xB1\nField <code>PARTNUMBER0</code> reader - These bits read back as 0x11\nRegister <code>UARTPERIPHID0</code> reader\nUARTPeriphID0 Register\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:7 - These bits read back as 0x11\nField <code>DESIGNER0</code> reader - These bits read back as 0x1\nField <code>PARTNUMBER1</code> reader - These bits read back as 0x0\nRegister <code>UARTPERIPHID1</code> reader\nUARTPeriphID1 Register\nBits 4:7 - These bits read back as 0x1\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:3 - These bits read back as 0x0\nField <code>DESIGNER1</code> reader - These bits read back as 0x4\nRegister <code>UARTPERIPHID2</code> reader\nField <code>REVISION</code> reader - This field depends on the revision …\nUARTPeriphID2 Register\nBits 0:3 - These bits read back as 0x4\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 4:7 - This field depends on the revision of the UART: …\nField <code>CONFIGURATION</code> reader - These bits read back as 0x00\nRegister <code>UARTPERIPHID3</code> reader\nUARTPeriphID3 Register\nBits 0:7 - These bits read back as 0x00\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>BERIS</code> reader - Break error interrupt status. Returns …\nField <code>CTSRMIS</code> reader - nUARTCTS modem interrupt status. …\nField <code>DCDRMIS</code> reader - nUARTDCD modem interrupt status. …\nField <code>DSRRMIS</code> reader - nUARTDSR modem interrupt status. …\nField <code>FERIS</code> reader - Framing error interrupt status. …\nField <code>OERIS</code> reader - Overrun error interrupt status. …\nField <code>PERIS</code> reader - Parity error interrupt status. …\nRegister <code>UARTRIS</code> reader\nField <code>RIRMIS</code> reader - nUARTRI modem interrupt status. …\nField <code>RTRIS</code> reader - Receive timeout interrupt status. …\nField <code>RXRIS</code> reader - Receive interrupt status. Returns the …\nField <code>TXRIS</code> reader - Transmit interrupt status. Returns …\nRaw Interrupt Status Register, UARTRIS\nBit 9 - Break error interrupt status. Returns the raw …\nBit 1 - nUARTCTS modem interrupt status. Returns the raw …\nBit 2 - nUARTDCD modem interrupt status. Returns the raw …\nBit 3 - nUARTDSR modem interrupt status. Returns the raw …\nBit 7 - Framing error interrupt status. Returns the raw …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 10 - Overrun error interrupt status. Returns the raw …\nBit 8 - Parity error interrupt status. Returns the raw …\nBit 0 - nUARTRI modem interrupt status. Returns the raw …\nBit 6 - Receive timeout interrupt status. Returns the raw …\nBit 4 - Receive interrupt status. Returns the raw …\nBit 5 - Transmit interrupt status. Returns the raw …\nField <code>BE</code> reader - Break error. This bit is set to 1 if a …\nField <code>BE</code> writer - Break error. This bit is set to 1 if a …\nField <code>FE</code> reader - Framing error. When set to 1, it …\nField <code>FE</code> writer - Framing error. When set to 1, it …\nField <code>OE</code> reader - Overrun error. This bit is set to 1 if …\nField <code>OE</code> writer - Overrun error. This bit is set to 1 if …\nField <code>PE</code> reader - Parity error. When set to 1, it …\nField <code>PE</code> writer - Parity error. When set to 1, it …\nRegister <code>UARTRSR</code> reader\nReceive Status Register/Error Clear Register, …\nRegister <code>UARTRSR</code> writer\nBit 2 - Break error. This bit is set to 1 if a break …\nBit 2 - Break error. This bit is set to 1 if a break …\nWrites raw bits to the register.\nBit 0 - Framing error. When set to 1, it indicates that …\nBit 0 - Framing error. When set to 1, it indicates that …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBit 3 - Overrun error. This bit is set to 1 if data is …\nBit 3 - Overrun error. This bit is set to 1 if data is …\nBit 1 - Parity error. When set to 1, it indicates that the …\nBit 1 - Parity error. When set to 1, it indicates that the …\nEPX_CONTROL (rw) register accessor: EPx Control (Host-mode …\nEP_BUFFER_CONTROL (rw) register accessor: -\nEP_CONTROL (rw) register accessor: -\nRegister block\nSETUP_PACKET_HIGH (rw) register accessor: Bytes 4-7 of the …\nSETUP_PACKET_LOW (rw) register accessor: Bytes 0-3 of the …\n0x80..0x100 - -\nIterator for array of: 0x80..0x100 - -\n0x08..0x80 - -\nIterator for array of: 0x08..0x80 - -\nEPx Control (Host-mode only!)\n0x100 - EPx Control (Host-mode only!)\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBytes 4-7 of the setup packet from the host.\n0x04 - Bytes 4-7 of the setup packet from the host.\nBytes 0-3 of the SETUP packet from the host.\n0x00 - Bytes 0-3 of the SETUP packet from the host.\nField <code>AVAILABLE_0</code> reader - Buffer 0 is available. This bit …\nField <code>AVAILABLE_0</code> writer - Buffer 0 is available. This bit …\nField <code>AVAILABLE_1</code> reader - Buffer 1 is available. This bit …\nField <code>AVAILABLE_1</code> writer - Buffer 1 is available. This bit …\nThe number of bytes buffer 1 is offset from buffer 0 in …\nField <code>DOUBLE_BUFFER_ISO_OFFSET</code> reader - The number of …\nField <code>DOUBLE_BUFFER_ISO_OFFSET</code> writer - The number of …\nYou can <code>read</code> this register and get <code>ep_buffer_control::R</code>. …\nField <code>FULL_0</code> reader - Buffer 0 is full. For an IN transfer …\nField <code>FULL_0</code> writer - Buffer 0 is full. For an IN transfer …\nField <code>FULL_1</code> reader - Buffer 1 is full. For an IN transfer …\nField <code>FULL_1</code> writer - Buffer 1 is full. For an IN transfer …\nField <code>LAST_0</code> reader - Buffer 0 is the last buffer of the …\nField <code>LAST_0</code> writer - Buffer 0 is the last buffer of the …\nField <code>LAST_1</code> reader - Buffer 1 is the last buffer of the …\nField <code>LAST_1</code> writer - Buffer 1 is the last buffer of the …\nField <code>LENGTH_0</code> reader - The length of the data in buffer 0.\nField <code>LENGTH_0</code> writer - The length of the data in buffer 0.\nField <code>LENGTH_1</code> reader - The length of the data in buffer 1.\nField <code>LENGTH_1</code> writer - The length of the data in buffer 1.\nField <code>PID_0</code> reader - The data pid of buffer 0.\nField <code>PID_0</code> writer - The data pid of buffer 0.\nField <code>PID_1</code> reader - The data pid of buffer 1.\nField <code>PID_1</code> writer - The data pid of buffer 1.\nRegister <code>EP_BUFFER_CONTROL%s</code> reader\nField <code>RESET</code> reader - Reset the buffer selector to buffer 0.\nField <code>RESET</code> writer - Reset the buffer selector to buffer 0.\nField <code>STALL</code> reader - Reply with a stall (valid for both …\nField <code>STALL</code> writer - Reply with a stall (valid for both …\nRegister <code>EP_BUFFER_CONTROL%s</code> writer\n<code>11</code>\n3: <code>11</code>\n<code>0</code>\n0: <code>0</code>\n<code>1</code>\n1: <code>1</code>\n<code>10</code>\n2: <code>10</code>\nBit 10 - Buffer 0 is available. This bit is set to …\nBit 10 - Buffer 0 is available. This bit is set to …\nBit 26 - Buffer 1 is available. This bit is set to …\nBit 26 - Buffer 1 is available. This bit is set to …\nWrites raw bits to the register.\nBits 27:28 - The number of bytes buffer 1 is offset from …\nBits 27:28 - The number of bytes buffer 1 is offset from …\nReturns the argument unchanged.\nReturns the argument unchanged.\nBit 15 - Buffer 0 is full. For an IN transfer (TX to the …\nBit 15 - Buffer 0 is full. For an IN transfer (TX to the …\nBit 31 - Buffer 1 is full. For an IN transfer (TX to the …\nBit 31 - Buffer 1 is full. For an IN transfer (TX to the …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>11</code>\n<code>0</code>\n<code>1</code>\n<code>10</code>\nBit 14 - Buffer 0 is the last buffer of the transfer.\nBit 14 - Buffer 0 is the last buffer of the transfer.\nBit 30 - Buffer 1 is the last buffer of the transfer.\nBit 30 - Buffer 1 is the last buffer of the transfer.\nBits 0:9 - The length of the data in buffer 0.\nBits 0:9 - The length of the data in buffer 0.\nBits 16:25 - The length of the data in buffer 1.\nBits 16:25 - The length of the data in buffer 1.\nBit 13 - The data pid of buffer 0.\nBit 13 - The data pid of buffer 0.\nBit 29 - The data pid of buffer 1.\nBit 29 - The data pid of buffer 1.\nBit 12 - Reset the buffer selector to buffer 0.\nBit 12 - Reset the buffer selector to buffer 0.\nBit 11 - Reply with a stall (valid for both buffers).\nBit 11 - Reply with a stall (valid for both buffers).\nGet enumerated values variant\nField <code>BUFFER_ADDRESS</code> reader - 64 byte aligned buffer …\nField <code>BUFFER_ADDRESS</code> writer - 64 byte aligned buffer …\n2: <code>10</code>\n0: <code>0</code>\nField <code>DOUBLE_BUFFERED</code> reader - This endpoint is double …\nField <code>DOUBLE_BUFFERED</code> writer - This endpoint is double …\nField <code>ENABLE</code> reader - Enable this endpoint. The device …\nField <code>ENABLE</code> writer - Enable this endpoint. The device …\nValue on reset: 0\nField <code>ENDPOINT_TYPE</code> reader -\nField <code>ENDPOINT_TYPE</code> writer -\nYou can <code>read</code> this register and get <code>ep_control::R</code>. You can …\nField <code>HOST_POLL_INTERVAL</code> reader - The interval the host …\nField <code>HOST_POLL_INTERVAL</code> writer - The interval the host …\n3: <code>11</code>\nField <code>INTERRUPT_ON_NAK</code> reader - Trigger an interrupt if a …\nField <code>INTERRUPT_ON_NAK</code> writer - Trigger an interrupt if a …\nField <code>INTERRUPT_ON_STALL</code> reader - Trigger an interrupt if …\nField <code>INTERRUPT_ON_STALL</code> writer - Trigger an interrupt if …\nField <code>INTERRUPT_PER_BUFF</code> reader - Trigger an interrupt …\nField <code>INTERRUPT_PER_BUFF</code> writer - Trigger an interrupt …\nField <code>INTERRUPT_PER_DOUBLE_BUFF</code> reader - Trigger an …\nField <code>INTERRUPT_PER_DOUBLE_BUFF</code> writer - Trigger an …\n1: <code>1</code>\nRegister <code>EP_CONTROL%s</code> reader\nRegister <code>EP_CONTROL%s</code> writer\nWrites raw bits to the register.\nBits 0:15 - 64 byte aligned buffer address for this EP …\nBits 0:15 - 64 byte aligned buffer address for this EP …\n<code>10</code>\n<code>0</code>\nBit 30 - This endpoint is double buffered.\nBit 30 - This endpoint is double buffered.\nBit 31 - Enable this endpoint. The device will not reply …\nBit 31 - Enable this endpoint. The device will not reply …\nBits 26:27\nBits 26:27\nReturns the argument unchanged.\nReturns the argument unchanged.\nBits 16:25 - The interval the host controller should poll …\nBits 16:25 - The interval the host controller should poll …\n<code>11</code>\nBit 16 - Trigger an interrupt if a NAK is sent. Intended …\nBit 16 - Trigger an interrupt if a NAK is sent. Intended …\nBit 17 - Trigger an interrupt if a STALL is sent. Intended …\nBit 17 - Trigger an interrupt if a STALL is sent. Intended …\nBit 29 - Trigger an interrupt each time a buffer is done.\nBit 29 - Trigger an interrupt each time a buffer is done.\nBit 28 - Trigger an interrupt each time both buffers are …\nBit 28 - Trigger an interrupt each time both buffers are …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>10</code>\n<code>0</code>\n<code>11</code>\n<code>1</code>\n<code>1</code>\nGet enumerated values variant\nField <code>BUFFER_ADDRESS</code> reader - 64 byte aligned buffer …\nField <code>BUFFER_ADDRESS</code> writer - 64 byte aligned buffer …\n2: <code>10</code>\n0: <code>0</code>\nField <code>DOUBLE_BUFFERED</code> reader - This endpoint is double …\nField <code>DOUBLE_BUFFERED</code> writer - This endpoint is double …\nField <code>ENABLE</code> reader - Enable this endpoint. The device …\nField <code>ENABLE</code> writer - Enable this endpoint. The device …\nValue on reset: 0\nField <code>ENDPOINT_TYPE</code> reader -\nField <code>ENDPOINT_TYPE</code> writer -\nEPx Control (Host-mode only!)\n3: <code>11</code>\nField <code>INTERRUPT_ON_NAK</code> reader - Trigger an interrupt if a …\nField <code>INTERRUPT_ON_NAK</code> writer - Trigger an interrupt if a …\nField <code>INTERRUPT_ON_STALL</code> reader - Trigger an interrupt if …\nField <code>INTERRUPT_ON_STALL</code> writer - Trigger an interrupt if …\nField <code>INTERRUPT_PER_BUFF</code> reader - Trigger an interrupt …\nField <code>INTERRUPT_PER_BUFF</code> writer - Trigger an interrupt …\nField <code>INTERRUPT_PER_DOUBLE_BUFF</code> reader - Trigger an …\nField <code>INTERRUPT_PER_DOUBLE_BUFF</code> writer - Trigger an …\n1: <code>1</code>\nRegister <code>EPX_CONTROL</code> reader\nRegister <code>EPX_CONTROL</code> writer\nWrites raw bits to the register.\nBits 0:15 - 64 byte aligned buffer address for this EP …\nBits 0:15 - 64 byte aligned buffer address for this EP …\n<code>10</code>\n<code>0</code>\nBit 30 - This endpoint is double buffered.\nBit 30 - This endpoint is double buffered.\nBit 31 - Enable this endpoint. The device will not reply …\nBit 31 - Enable this endpoint. The device will not reply …\nBits 26:27\nBits 26:27\nReturns the argument unchanged.\nReturns the argument unchanged.\n<code>11</code>\nBit 16 - Trigger an interrupt if a NAK is sent. Intended …\nBit 16 - Trigger an interrupt if a NAK is sent. Intended …\nBit 17 - Trigger an interrupt if a STALL is sent. Intended …\nBit 17 - Trigger an interrupt if a STALL is sent. Intended …\nBit 29 - Trigger an interrupt each time a buffer is done.\nBit 29 - Trigger an interrupt each time a buffer is done.\nBit 28 - Trigger an interrupt each time both buffers are …\nBit 28 - Trigger an interrupt each time both buffers are …\nCalls <code>U::from(self)</code>.\nCalls <code>U::from(self)</code>.\n<code>10</code>\n<code>0</code>\n<code>11</code>\n<code>1</code>\n<code>1</code>\nGet enumerated values variant\nRegister <code>SETUP_PACKET_HIGH</code> reader\nBytes 4-7 of the setup packet from the host.\nRegister <code>SETUP_PACKET_HIGH</code> writer\nField <code>WINDEX</code> reader -\nField <code>WINDEX</code> writer -\nField <code>WLENGTH</code> reader -\nField <code>WLENGTH</code> writer -\nWrites raw bits to the register.\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 0:15\nBits 0:15\nBits 16:31\nBits 16:31\nField <code>BMREQUESTTYPE</code> reader -\nField <code>BMREQUESTTYPE</code> writer -\nField <code>BREQUEST</code> reader -\nField <code>BREQUEST</code> writer -\nRegister <code>SETUP_PACKET_LOW</code> reader\nBytes 0-3 of the SETUP packet from the host.\nRegister <code>SETUP_PACKET_LOW</code> writer\nField <code>WVALUE</code> reader -\nField <code>WVALUE</code> writer -\nWrites raw bits to the register.\nBits 0:7\nBits 0:7\nBits 8:15\nBits 8:15\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBits 16:31\nBits 16:31\nADDR_ENDP (rw) register accessor: Device address and …\nBUFF_CPU_SHOULD_HANDLE (r) register accessor: Which of the …\nBUFF_STATUS (rw) register accessor: Buffer status …\nEP_ABORT (rw) register accessor: Device only: Can be set …\nEP_ABORT_DONE (rw) register accessor: Device only: Used in …\nEP_STALL_ARM (rw) register accessor: Device: this bit must …\nEP_STATUS_STALL_NAK (rw) register accessor: Device: bits …\nHOST_ADDR_ENDP (rw) register accessor: Interrupt …\nINTE (rw) register accessor: Interrupt Enable\nINTF (rw) register accessor: Interrupt Force\nINTR (r) register accessor: Raw Interrupts\nINTS (r) register accessor: Interrupt status after masking …\nINT_EP_CTRL (rw) register accessor: interrupt endpoint …\nMAIN_CTRL (rw) register accessor: Main control register\nNAK_POLL (rw) register accessor: Used by the host …\nRegister block\nSIE_CTRL (rw) register accessor: SIE control register\nSIE_STATUS (rw) register accessor: SIE status register\nSOF_RD (r) register accessor: Read the last SOF (Start of …\nSOF_WR (w) register accessor: Set the SOF (Start of Frame) …\nUSBPHY_DIRECT (rw) register accessor: This register allows …\nUSBPHY_DIRECT_OVERRIDE (rw) register accessor: Override …\nUSBPHY_TRIM (rw) register accessor: Used to adjust trim …\nUSB_MUXING (rw) register accessor: Where to connect the …\nUSB_PWR (rw) register accessor: Overrides for the power …\nDevice address and endpoint control\n0x00 - Device address and endpoint control\nWhich of the double buffers should be handled. Only valid …\n0x5c - Which of the double buffers should be handled. Only …\nBuffer status register. A bit set here indicates that a …\n0x58 - Buffer status register. A bit set here indicates …\nDevice only: Can be set to ignore the buffer control …\n0x60 - Device only: Can be set to ignore the buffer …\nDevice only: Used in conjunction with <code>EP_ABORT</code>. Set once …\n0x64 - Device only: Used in conjunction with <code>EP_ABORT</code>. Set …\nDevice: this bit must be set in conjunction with the <code>STALL</code> …\n0x68 - Device: this bit must be set in conjunction with …\nDevice: bits are set when the <code>IRQ_ON_NAK</code> or <code>IRQ_ON_STALL</code> …\n0x70 - Device: bits are set when the <code>IRQ_ON_NAK</code> or …\nReturns the argument unchanged.\nInterrupt endpoints. Only valid in HOST mode.\n0x04..0x40 - Interrupt endpoints. Only valid in HOST mode.\n0x04 - Interrupt endpoints. Only valid in HOST mode.\n0x28 - Interrupt endpoints. Only valid in HOST mode.\n0x2c - Interrupt endpoints. Only valid in HOST mode.\n0x30 - Interrupt endpoints. Only valid in HOST mode.\n0x34 - Interrupt endpoints. Only valid in HOST mode.\n0x38 - Interrupt endpoints. Only valid in HOST mode.\n0x3c - Interrupt endpoints. Only valid in HOST mode.\n0x08 - Interrupt endpoints. Only valid in HOST mode.\n0x0c - Interrupt endpoints. Only valid in HOST mode.\n0x10 - Interrupt endpoints. Only valid in HOST mode.\n0x14 - Interrupt endpoints. Only valid in HOST mode.\n0x18 - Interrupt endpoints. Only valid in HOST mode.\n0x1c - Interrupt endpoints. Only valid in HOST mode.\n0x20 - Interrupt endpoints. Only valid in HOST mode.\n0x24 - Interrupt endpoints. Only valid in HOST mode.\nIterator for array of: 0x04..0x40 - Interrupt endpoints. …\ninterrupt endpoint control register\n0x54 - interrupt endpoint control register\nInterrupt Enable\n0x90 - Interrupt Enable\nInterrupt Force\n0x94 - Interrupt Force\nCalls <code>U::from(self)</code>.\nRaw Interrupts\n0x8c - Raw Interrupts\nInterrupt status after masking &amp; forcing\n0x98 - Interrupt status after masking &amp; forcing\nMain control register\n0x40 - Main control register\nUsed by the host controller. Sets the wait time in …\n0x6c - Used by the host controller. Sets the wait time in …\nSIE control register\n0x4c - SIE control register\nSIE status register\n0x50 - SIE status register\nRead the last SOF (Start of Frame) frame number seen. In …\n0x48 - Read the last SOF (Start of Frame) frame number …\nSet the SOF (Start of Frame) frame number in the host …\n0x44 - Set the SOF (Start of Frame) frame number in the …\nWhere to connect the USB controller. Should be to_phy by …\n0x74 - Where to connect the USB controller. Should be …\nOverrides for the power signals in the event that the VBUS …\n0x78 - Overrides for the power signals in the event that …\nThis register allows for direct control of the USB phy. …\n0x7c - This register allows for direct control of the USB …\nOverride enable for each control in usbphy_direct\n0x80 - Override enable for each control in usbphy_direct\nUsed to adjust trim values of USB phy pull down resistors.\n0x84 - Used to adjust trim values of USB phy pull down …\nField <code>ADDRESS</code> reader - In device mode, the address that …\nField <code>ADDRESS</code> writer - In device mode, the address that …\nDevice address and endpoint control\nField <code>ENDPOINT</code> reader - Device endpoint to send data to. …\nField <code>ENDPOINT</code> writer - Device endpoint to send data to. …\nRegister <code>ADDR_ENDP</code> reader\nRegister <code>ADDR_ENDP</code> writer\nBits 0:6 - In device mode, the address that the device …\nBits 0:6 - In device mode, the address that the device …\nWrites raw bits to the register.\nBits 16:19 - Device endpoint to send data to. Only valid …\nBits 16:19 - Device endpoint to send data to. Only valid …\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nWhich of the double buffers should be handled. Only valid …\nField <code>EP0_IN</code> reader -\nField <code>EP0_OUT</code> reader -\nField <code>EP10_IN</code> reader -\nField <code>EP10_OUT</code> reader -\nField <code>EP11_IN</code> reader -\nField <code>EP11_OUT</code> reader -\nField <code>EP12_IN</code> reader -\nField <code>EP12_OUT</code> reader -\nField <code>EP13_IN</code> reader -\nField <code>EP13_OUT</code> reader -\nField <code>EP14_IN</code> reader -\nField <code>EP14_OUT</code> reader -\nField <code>EP15_IN</code> reader -\nField <code>EP15_OUT</code> reader -\nField <code>EP1_IN</code> reader -\nField <code>EP1_OUT</code> reader -\nField <code>EP2_IN</code> reader -\nField <code>EP2_OUT</code> reader -\nField <code>EP3_IN</code> reader -\nField <code>EP3_OUT</code> reader -\nField <code>EP4_IN</code> reader -\nField <code>EP4_OUT</code> reader -\nField <code>EP5_IN</code> reader -\nField <code>EP5_OUT</code> reader -\nField <code>EP6_IN</code> reader -\nField <code>EP6_OUT</code> reader -\nField <code>EP7_IN</code> reader -\nField <code>EP7_OUT</code> reader -\nField <code>EP8_IN</code> reader -\nField <code>EP8_OUT</code> reader -\nField <code>EP9_IN</code> reader -\nField <code>EP9_OUT</code> reader -\nRegister <code>BUFF_CPU_SHOULD_HANDLE</code> reader\nBit 0\nBit 1\nBit 20\nBit 21\nBit 22\nBit 23\nBit 24\nBit 25\nBit 26\nBit 27\nBit 28\nBit 29\nBit 30\nBit 31\nBit 2\nBit 3\nBit 4\nBit 5\nBit 6\nBit 7\nBit 8\nBit 9\nBit 10\nBit 11\nBit 12\nBit 13\nBit 14\nBit 15\nBit 16\nBit 17\nBit 18\nBit 19\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nBuffer status register. A bit set here indicates that a …\nField <code>EP0_IN</code> reader -\nField <code>EP0_IN</code> writer -\nField <code>EP0_OUT</code> reader -\nField <code>EP0_OUT</code> writer -\nField <code>EP10_IN</code> reader -\nField <code>EP10_IN</code> writer -\nField <code>EP10_OUT</code> reader -\nField <code>EP10_OUT</code> writer -\nField <code>EP11_IN</code> reader -\nField <code>EP11_IN</code> writer -\nField <code>EP11_OUT</code> reader -\nField <code>EP11_OUT</code> writer -\nField <code>EP12_IN</code> reader -\nField <code>EP12_IN</code> writer -\nField <code>EP12_OUT</code> reader -\nField <code>EP12_OUT</code> writer -\nField <code>EP13_IN</code> reader -\nField <code>EP13_IN</code> writer -\nField <code>EP13_OUT</code> reader -\nField <code>EP13_OUT</code> writer -\nField <code>EP14_IN</code> reader -\nField <code>EP14_IN</code> writer -\nField <code>EP14_OUT</code> reader -\nField <code>EP14_OUT</code> writer -\nField <code>EP15_IN</code> reader -\nField <code>EP15_IN</code> writer -\nField <code>EP15_OUT</code> reader -\nField <code>EP15_OUT</code> writer -\nField <code>EP1_IN</code> reader -\nField <code>EP1_IN</code> writer -\nField <code>EP1_OUT</code> reader -\nField <code>EP1_OUT</code> writer -\nField <code>EP2_IN</code> reader -\nField <code>EP2_IN</code> writer -\nField <code>EP2_OUT</code> reader -\nField <code>EP2_OUT</code> writer -\nField <code>EP3_IN</code> reader -\nField <code>EP3_IN</code> writer -\nField <code>EP3_OUT</code> reader -\nField <code>EP3_OUT</code> writer -\nField <code>EP4_IN</code> reader -\nField <code>EP4_IN</code> writer -\nField <code>EP4_OUT</code> reader -\nField <code>EP4_OUT</code> writer -\nField <code>EP5_IN</code> reader -\nField <code>EP5_IN</code> writer -\nField <code>EP5_OUT</code> reader -\nField <code>EP5_OUT</code> writer -\nField <code>EP6_IN</code> reader -\nField <code>EP6_IN</code> writer -\nField <code>EP6_OUT</code> reader -\nField <code>EP6_OUT</code> writer -\nField <code>EP7_IN</code> reader -\nField <code>EP7_IN</code> writer -\nField <code>EP7_OUT</code> reader -\nField <code>EP7_OUT</code> writer -\nField <code>EP8_IN</code> reader -\nField <code>EP8_IN</code> writer -\nField <code>EP8_OUT</code> reader -\nField <code>EP8_OUT</code> writer -\nField <code>EP9_IN</code> reader -\nField <code>EP9_IN</code> writer -\nField <code>EP9_OUT</code> reader -\nField <code>EP9_OUT</code> writer -\nRegister <code>BUFF_STATUS</code> reader\nRegister <code>BUFF_STATUS</code> writer\nWrites raw bits to the register.\nBit 0\nBit 0\nBit 1\nBit 1\nBit 20\nBit 20\nBit 21\nBit 21\nBit 22\nBit 22\nBit 23\nBit 23\nBit 24\nBit 24\nBit 25\nBit 25\nBit 26\nBit 26\nBit 27\nBit 27\nBit 28\nBit 28\nBit 29\nBit 29\nBit 30\nBit 30\nBit 31\nBit 31\nBit 2\nBit 2\nBit 3\nBit 3\nBit 4\nBit 4\nBit 5\nBit 5\nBit 6\nBit 6\nBit 7\nBit 7\nBit 8\nBit 8\nBit 9\nBit 9\nBit 10\nBit 10\nBit 11\nBit 11\nBit 12\nBit 12\nBit 13\nBit 13\nBit 14\nBit 14\nBit 15\nBit 15\nBit 16\nBit 16\nBit 17\nBit 17\nBit 18\nBit 18\nBit 19\nBit 19\nReturns the argument unchanged.\nCalls <code>U::from(self)</code>.\nField <code>EP0_IN</code> reader -\nField <code>EP0_IN</code> writer -\nField <code>EP0_OUT</code> reader -\nField <code>EP0_OUT</code> writer -\nField <code>EP10_IN</code> reader -\nField <code>EP10_IN</code> writer -\nField <code>EP10_OUT</code> reader -\nField <code>EP10_OUT</code> writer -\nField <code>EP11_IN</code> reader -\nField <code>EP11_IN</code> writer -\nField <code>EP11_OUT</code> reader -\nField <code>EP11_OUT</code> writer -\nField <code>EP12_IN</code> reader -\nField <code>EP12_IN</code> writer -\nField <code>EP12_OUT</code> reader -")
Reference in a new issue View git blame Copy permalink