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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Register block for various chip control signals"><title>rp2040_pac::syscfg - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module syscfg</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#modules">Modules</a></li><li><a href="#structs">Structs</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../index.html">rp2040_pac</a>::<wbr><a class="mod" href="#">syscfg</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../src/rp2040_pac/syscfg.rs.html#1-144">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Register block for various chip control signals</p>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="dbgforce/index.html" title="mod rp2040_pac::syscfg::dbgforce">dbgforce</a></div><div class="desc docblock-short">Directly control the SWD debug port of either processor</div></li><li><div class="item-name"><a class="mod" href="mempowerdown/index.html" title="mod rp2040_pac::syscfg::mempowerdown">mempowerdown</a></div><div class="desc docblock-short">Control power downs to memories. Set high to power down memories.<br />
Use with extreme caution</div></li><li><div class="item-name"><a class="mod" href="proc0_nmi_mask/index.html" title="mod rp2040_pac::syscfg::proc0_nmi_mask">proc0_<wbr>nmi_<wbr>mask</a></div><div class="desc docblock-short">Processor core 0 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</div></li><li><div class="item-name"><a class="mod" href="proc1_nmi_mask/index.html" title="mod rp2040_pac::syscfg::proc1_nmi_mask">proc1_<wbr>nmi_<wbr>mask</a></div><div class="desc docblock-short">Processor core 1 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</div></li><li><div class="item-name"><a class="mod" href="proc_config/index.html" title="mod rp2040_pac::syscfg::proc_config">proc_<wbr>config</a></div><div class="desc docblock-short">Configuration for processors</div></li><li><div class="item-name"><a class="mod" href="proc_in_sync_bypass/index.html" title="mod rp2040_pac::syscfg::proc_in_sync_bypass">proc_<wbr>in_<wbr>sync_<wbr>bypass</a></div><div class="desc docblock-short">For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If you’re feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 0…29.</div></li><li><div class="item-name"><a class="mod" href="proc_in_sync_bypass_hi/index.html" title="mod rp2040_pac::syscfg::proc_in_sync_bypass_hi">proc_<wbr>in_<wbr>sync_<wbr>bypass_<wbr>hi</a></div><div class="desc docblock-short">For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If you’re feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 30…35 (the QSPI IOs).</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::syscfg::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.DBGFORCE.html" title="type rp2040_pac::syscfg::DBGFORCE">DBGFORCE</a></div><div class="desc docblock-short">DBGFORCE (rw) register accessor: Directly control the SWD debug port of either processor</div></li><li><div class="item-name"><a class="type" href="type.MEMPOWERDOWN.html" title="type rp2040_pac::syscfg::MEMPOWERDOWN">MEMPOWERDOWN</a></div><div class="desc docblock-short">MEMPOWERDOWN (rw) register accessor: Control power downs to memories. Set high to power down memories.<br />
Use with extreme caution</div></li><li><div class="item-name"><a class="type" href="type.PROC0_NMI_MASK.html" title="type rp2040_pac::syscfg::PROC0_NMI_MASK">PROC0_<wbr>NMI_<wbr>MASK</a></div><div class="desc docblock-short">PROC0_NMI_MASK (rw) register accessor: Processor core 0 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</div></li><li><div class="item-name"><a class="type" href="type.PROC1_NMI_MASK.html" title="type rp2040_pac::syscfg::PROC1_NMI_MASK">PROC1_<wbr>NMI_<wbr>MASK</a></div><div class="desc docblock-short">PROC1_NMI_MASK (rw) register accessor: Processor core 1 NMI source mask<br />
Set a bit high to enable NMI from that IRQ</div></li><li><div class="item-name"><a class="type" href="type.PROC_CONFIG.html" title="type rp2040_pac::syscfg::PROC_CONFIG">PROC_<wbr>CONFIG</a></div><div class="desc docblock-short">PROC_CONFIG (rw) register accessor: Configuration for processors</div></li><li><div class="item-name"><a class="type" href="type.PROC_IN_SYNC_BYPASS.html" title="type rp2040_pac::syscfg::PROC_IN_SYNC_BYPASS">PROC_<wbr>IN_<wbr>SYNC_<wbr>BYPASS</a></div><div class="desc docblock-short">PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If you’re feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 0…29.</div></li><li><div class="item-name"><a class="type" href="type.PROC_IN_SYNC_BYPASS_HI.html" title="type rp2040_pac::syscfg::PROC_IN_SYNC_BYPASS_HI">PROC_<wbr>IN_<wbr>SYNC_<wbr>BYPAS<wbr>S_<wbr>HI</a></div><div class="desc docblock-short">PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO<br />
and the GPIO input register in the SIO. The input synchronizers should<br />
generally be unbypassed, to avoid injecting metastabilities into processors.<br />
If you’re feeling brave, you can bypass to save two cycles of input<br />
latency. This register applies to GPIO 30…35 (the QSPI IOs).</div></li></ul></section></div></main></body></html>
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