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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="API documentation for the Rust `regs` mod in crate `stm32_metapac`."><title>stm32_metapac::eth::regs - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="stm32_metapac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../stm32_metapac/index.html">stm32_<wbr>metapac</a><span class="version">15.0.0</span></h2></div><h2 class="location"><a href="#">Module regs</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#structs">Structs</a></li></ul></section><h2><a href="../index.html">In stm32_<wbr>metapac::<wbr>eth</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../../index.html">stm32_metapac</a>::<wbr><a href="../index.html">eth</a>::<wbr><a class="mod" href="#">regs</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.DmaccarxBr.html" title="struct stm32_metapac::eth::regs::DmaccarxBr">Dmaccarx<wbr>Br</a></div><div class="desc docblock-short">Channel current application receive buffer register</div></li><li><div class="item-name"><a class="struct" href="struct.DmaccarxDr.html" title="struct stm32_metapac::eth::regs::DmaccarxDr">Dmaccarx<wbr>Dr</a></div><div class="desc docblock-short">Channel current application receive descriptor register</div></li><li><div class="item-name"><a class="struct" href="struct.DmaccatxBr.html" title="struct stm32_metapac::eth::regs::DmaccatxBr">Dmaccatx<wbr>Br</a></div><div class="desc docblock-short">Channel current application transmit buffer register</div></li><li><div class="item-name"><a class="struct" href="struct.DmaccatxDr.html" title="struct stm32_metapac::eth::regs::DmaccatxDr">Dmaccatx<wbr>Dr</a></div><div class="desc docblock-short">Channel current application transmit descriptor register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmaccr.html" title="struct stm32_metapac::eth::regs::Dmaccr">Dmaccr</a></div><div class="desc docblock-short">Channel control register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmacier.html" title="struct stm32_metapac::eth::regs::Dmacier">Dmacier</a></div><div class="desc docblock-short">Channel interrupt enable register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmacmfcr.html" title="struct stm32_metapac::eth::regs::Dmacmfcr">Dmacmfcr</a></div><div class="desc docblock-short">Channel missed frame count register</div></li><li><div class="item-name"><a class="struct" href="struct.DmacrxCr.html" title="struct stm32_metapac::eth::regs::DmacrxCr">Dmacrx<wbr>Cr</a></div><div class="desc docblock-short">Channel receive control register</div></li><li><div class="item-name"><a class="struct" href="struct.DmacrxDlar.html" title="struct stm32_metapac::eth::regs::DmacrxDlar">Dmacrx<wbr>Dlar</a></div><div class="desc docblock-short">Channel Rx descriptor list address register</div></li><li><div class="item-name"><a class="struct" href="struct.DmacrxDtpr.html" title="struct stm32_metapac::eth::regs::DmacrxDtpr">Dmacrx<wbr>Dtpr</a></div><div class="desc docblock-short">Channel Rx descriptor tail pointer register</div></li><li><div class="item-name"><a class="struct" href="struct.DmacrxIwtr.html" title="struct stm32_metapac::eth::regs::DmacrxIwtr">Dmacrx<wbr>Iwtr</a></div><div class="desc docblock-short">Channel Rx interrupt watchdog timer register</div></li><li><div class="item-name"><a class="struct" href="struct.DmacrxRlr.html" title="struct stm32_metapac::eth::regs::DmacrxRlr">Dmacrx<wbr>Rlr</a></div><div class="desc docblock-short">Channel Rx descriptor ring length register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmacsr.html" title="struct stm32_metapac::eth::regs::Dmacsr">Dmacsr</a></div><div class="desc docblock-short">Channel status register</div></li><li><div class="item-name"><a class="struct" href="struct.DmactxCr.html" title="struct stm32_metapac::eth::regs::DmactxCr">Dmactx<wbr>Cr</a></div><div class="desc docblock-short">Channel transmit control register</div></li><li><div class="item-name"><a class="struct" href="struct.DmactxDlar.html" title="struct stm32_metapac::eth::regs::DmactxDlar">Dmactx<wbr>Dlar</a></div><div class="desc docblock-short">Channel Tx descriptor list address register</div></li><li><div class="item-name"><a class="struct" href="struct.DmactxDtpr.html" title="struct stm32_metapac::eth::regs::DmactxDtpr">Dmactx<wbr>Dtpr</a></div><div class="desc docblock-short">Channel Tx descriptor tail pointer register</div></li><li><div class="item-name"><a class="struct" href="struct.DmactxRlr.html" title="struct stm32_metapac::eth::regs::DmactxRlr">Dmactx<wbr>Rlr</a></div><div class="desc docblock-short">Channel Tx descriptor ring length register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmadsr.html" title="struct stm32_metapac::eth::regs::Dmadsr">Dmadsr</a></div><div class="desc docblock-short">Debug status register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmaisr.html" title="struct stm32_metapac::eth::regs::Dmaisr">Dmaisr</a></div><div class="desc docblock-short">Interrupt status register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmamr.html" title="struct stm32_metapac::eth::regs::Dmamr">Dmamr</a></div><div class="desc docblock-short">DMA mode register</div></li><li><div class="item-name"><a class="struct" href="struct.Dmasbmr.html" title="struct stm32_metapac::eth::regs::Dmasbmr">Dmasbmr</a></div><div class="desc docblock-short">System bus mode register</div></li><li><div class="item-name"><a class="struct" href="struct.Mac1ustcr.html" title="struct stm32_metapac::eth::regs::Mac1ustcr">Mac1ustcr</a></div><div class="desc docblock-short">1-microsecond-tick counter register</div></li><li><div class="item-name"><a class="struct" href="struct.Maca0hr.html" title="struct stm32_metapac::eth::regs::Maca0hr">Maca0hr</a></div><div class="desc docblock-short">Address 0 high register</div></li><li><div class="item-name"><a class="struct" href="struct.Maca0lr.html" title="struct stm32_metapac::eth::regs::Maca0lr">Maca0lr</a></div><div class="desc docblock-short">Address 0 low register</div></li><li><div class="item-name"><a class="struct" href="struct.Macacr.html" title="struct stm32_metapac::eth::regs::Macacr">Macacr</a></div><div class="desc docblock-short">Auxiliary control register</div></li><li><div class="item-name"><a class="struct" href="struct.Macahr.html" title="struct stm32_metapac::eth::regs::Macahr">Macahr</a></div><div class="desc docblock-short">Address 1/2/3 high register</div></li><li><div class="item-name"><a class="struct" href="struct.Macalr.html" title="struct stm32_metapac::eth::regs::Macalr">Macalr</a></div><div class="desc docblock-short">Address 1/2/3 low register</div></li><li><div class="item-name"><a class="struct" href="struct.Macarpar.html" title="struct stm32_metapac::eth::regs::Macarpar">Macarpar</a></div><div class="desc docblock-short">ARP address register</div></li><li><div class="item-name"><a class="struct" href="struct.Macatsnr.html" title="struct stm32_metapac::eth::regs::Macatsnr">Macatsnr</a></div><div class="desc docblock-short">Auxiliary timestamp nanoseconds register</div></li><li><div class="item-name"><a class="struct" href="struct.Macatssr.html" title="struct stm32_metapac::eth::regs::Macatssr">Macatssr</a></div><div class="desc docblock-short">Auxiliary timestamp seconds register</div></li><li><div class="item-name"><a class="struct" href="struct.Maccr.html" title="struct stm32_metapac::eth::regs::Maccr">Maccr</a></div><div class="desc docblock-short">Operating mode configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.Macdr.html" title="struct stm32_metapac::eth::regs::Macdr">Macdr</a></div><div class="desc docblock-short">Debug register</div></li><li><div class="item-name"><a class="struct" href="struct.Macecr.html" title="struct stm32_metapac::eth::regs::Macecr">Macecr</a></div><div class="desc docblock-short">Extended operating mode configuration register</div></li><li><div class="item-name"><a class="struct" href="struct.Machtr.html" title="struct stm32_metapac::eth::regs::Machtr">Machtr</a></div><div class="desc docblock-short">Hash Table 0/1 register</div></li><li><div class="item-name"><a class="struct" href="struct.Machwf1r.html" title="struct stm32_metapac::eth::regs::Machwf1r">Machwf1r</a></div><div class="desc docblock-short">HW feature 1 register</div></li><li><div class="item-name"><a class="struct" href="struct.Machwf2r.html" title="struct stm32_metapac::eth::regs::Machwf2r">Machwf2r</a></div><div class="desc docblock-short">HW feature 2 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macier.html" title="struct stm32_metapac::eth::regs::Macier">Macier</a></div><div class="desc docblock-short">Interrupt enable register</div></li><li><div class="item-name"><a class="struct" href="struct.Macisr.html" title="struct stm32_metapac::eth::regs::Macisr">Macisr</a></div><div class="desc docblock-short">Interrupt status register</div></li><li><div class="item-name"><a class="struct" href="struct.Macivir.html" title="struct stm32_metapac::eth::regs::Macivir">Macivir</a></div><div class="desc docblock-short">Inner VLAN inclusion register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a00r.html" title="struct stm32_metapac::eth::regs::Macl3a00r">Macl3a00r</a></div><div class="desc docblock-short">MACL3A00R</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a01r.html" title="struct stm32_metapac::eth::regs::Macl3a01r">Macl3a01r</a></div><div class="desc docblock-short">Layer3 address 0 filter 1 Register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a20.html" title="struct stm32_metapac::eth::regs::Macl3a20">Macl3a20</a></div><div class="desc docblock-short">Layer3 Address 2 filter 0 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a30.html" title="struct stm32_metapac::eth::regs::Macl3a30">Macl3a30</a></div><div class="desc docblock-short">Layer3 Address 3 filter 0 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a10r.html" title="struct stm32_metapac::eth::regs::Macl3a10r">Macl3a10r</a></div><div class="desc docblock-short">Layer3 address 1 filter 0 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a11r.html" title="struct stm32_metapac::eth::regs::Macl3a11r">Macl3a11r</a></div><div class="desc docblock-short">Layer3 address 1 filter 1 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a21r.html" title="struct stm32_metapac::eth::regs::Macl3a21r">Macl3a21r</a></div><div class="desc docblock-short">Layer3 address 2 filter 1 Register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3a31r.html" title="struct stm32_metapac::eth::regs::Macl3a31r">Macl3a31r</a></div><div class="desc docblock-short">Layer3 address 3 filter 1 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3l4c0r.html" title="struct stm32_metapac::eth::regs::Macl3l4c0r">Macl3l4c0r</a></div><div class="desc docblock-short">L3 and L4 control 0 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl3l4c1r.html" title="struct stm32_metapac::eth::regs::Macl3l4c1r">Macl3l4c1r</a></div><div class="desc docblock-short">L3 and L4 control 1 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl4a0r.html" title="struct stm32_metapac::eth::regs::Macl4a0r">Macl4a0r</a></div><div class="desc docblock-short">Layer4 address filter 0 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macl4a1r.html" title="struct stm32_metapac::eth::regs::Macl4a1r">Macl4a1r</a></div><div class="desc docblock-short">Layer 4 address filter 1 register</div></li><li><div class="item-name"><a class="struct" href="struct.Maclcsr.html" title="struct stm32_metapac::eth::regs::Maclcsr">Maclcsr</a></div><div class="desc docblock-short">LPI control status register</div></li><li><div class="item-name"><a class="struct" href="struct.Macletr.html" title="struct stm32_metapac::eth::regs::Macletr">Macletr</a></div><div class="desc docblock-short">LPI entry timer register</div></li><li><div class="item-name"><a class="struct" href="struct.Maclmir.html" title="struct stm32_metapac::eth::regs::Maclmir">Maclmir</a></div><div class="desc docblock-short">Log message interval register</div></li><li><div class="item-name"><a class="struct" href="struct.Macltcr.html" title="struct stm32_metapac::eth::regs::Macltcr">Macltcr</a></div><div class="desc docblock-short">LPI timers control register</div></li><li><div class="item-name"><a class="struct" href="struct.Macmdioar.html" title="struct stm32_metapac::eth::regs::Macmdioar">Macmdioar</a></div><div class="desc docblock-short">MDIO address register</div></li><li><div class="item-name"><a class="struct" href="struct.Macmdiodr.html" title="struct stm32_metapac::eth::regs::Macmdiodr">Macmdiodr</a></div><div class="desc docblock-short">MDIO data register</div></li><li><div class="item-name"><a class="struct" href="struct.Macpcsr.html" title="struct stm32_metapac::eth::regs::Macpcsr">Macpcsr</a></div><div class="desc docblock-short">PMT control status register</div></li><li><div class="item-name"><a class="struct" href="struct.Macpfr.html" title="struct stm32_metapac::eth::regs::Macpfr">Macpfr</a></div><div class="desc docblock-short">Packet filtering control register</div></li><li><div class="item-name"><a class="struct" href="struct.Macpocr.html" title="struct stm32_metapac::eth::regs::Macpocr">Macpocr</a></div><div class="desc docblock-short">PTP Offload control register</div></li><li><div class="item-name"><a class="struct" href="struct.Macppscr.html" title="struct stm32_metapac::eth::regs::Macppscr">Macppscr</a></div><div class="desc docblock-short">PPS control register</div></li><li><div class="item-name"><a class="struct" href="struct.Macppsir.html" title="struct stm32_metapac::eth::regs::Macppsir">Macppsir</a></div><div class="desc docblock-short">PPS interval register</div></li><li><div class="item-name"><a class="struct" href="struct.Macppsttnr.html" title="struct stm32_metapac::eth::regs::Macppsttnr">Macppsttnr</a></div><div class="desc docblock-short">PPS target time nanoseconds register</div></li><li><div class="item-name"><a class="struct" href="struct.Macppsttsr.html" title="struct stm32_metapac::eth::regs::Macppsttsr">Macppsttsr</a></div><div class="desc docblock-short">PPS target time seconds register</div></li><li><div class="item-name"><a class="struct" href="struct.Macppswr.html" title="struct stm32_metapac::eth::regs::Macppswr">Macppswr</a></div><div class="desc docblock-short">PPS width register</div></li><li><div class="item-name"><a class="struct" href="struct.MacqtxFcr.html" title="struct stm32_metapac::eth::regs::MacqtxFcr">Macqtx<wbr>Fcr</a></div><div class="desc docblock-short">Tx Queue flow control register</div></li><li><div class="item-name"><a class="struct" href="struct.Macrwkpfr.html" title="struct stm32_metapac::eth::regs::Macrwkpfr">Macrwkpfr</a></div><div class="desc docblock-short">Remove wakeup packet filter register</div></li><li><div class="item-name"><a class="struct" href="struct.MacrxFcr.html" title="struct stm32_metapac::eth::regs::MacrxFcr">Macrx<wbr>Fcr</a></div><div class="desc docblock-short">Rx flow control register</div></li><li><div class="item-name"><a class="struct" href="struct.MacrxTxSr.html" title="struct stm32_metapac::eth::regs::MacrxTxSr">Macrx<wbr>TxSr</a></div><div class="desc docblock-short">Rx Tx status register</div></li><li><div class="item-name"><a class="struct" href="struct.Macspi0r.html" title="struct stm32_metapac::eth::regs::Macspi0r">Macspi0r</a></div><div class="desc docblock-short">PTP Source Port Identity 0 Register</div></li><li><div class="item-name"><a class="struct" href="struct.Macspi1r.html" title="struct stm32_metapac::eth::regs::Macspi1r">Macspi1r</a></div><div class="desc docblock-short">PTP Source port identity 1 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macspi2r.html" title="struct stm32_metapac::eth::regs::Macspi2r">Macspi2r</a></div><div class="desc docblock-short">PTP Source port identity 2 register</div></li><li><div class="item-name"><a class="struct" href="struct.Macssir.html" title="struct stm32_metapac::eth::regs::Macssir">Macssir</a></div><div class="desc docblock-short">Sub-second increment register</div></li><li><div class="item-name"><a class="struct" href="struct.Macstnr.html" title="struct stm32_metapac::eth::regs::Macstnr">Macstnr</a></div><div class="desc docblock-short">System time nanoseconds register</div></li><li><div class="item-name"><a class="struct" href="struct.Macstnur.html" title="struct stm32_metapac::eth::regs::Macstnur">Macstnur</a></div><div class="desc docblock-short">System time nanoseconds update register</div></li><li><div class="item-name"><a class="struct" href="struct.Macstsr.html" title="struct stm32_metapac::eth::regs::Macstsr">Macstsr</a></div><div class="desc docblock-short">System time seconds register</div></li><li><div class="item-name"><a class="struct" href="struct.Macstsur.html" title="struct stm32_metapac::eth::regs::Macstsur">Macstsur</a></div><div class="desc docblock-short">System time seconds update register</div></li><li><div class="item-name"><a class="struct" href="struct.Mactsar.html" title="struct stm32_metapac::eth::regs::Mactsar">Mactsar</a></div><div class="desc docblock-short">Timestamp addend register</div></li><li><div class="item-name"><a class="struct" href="struct.Mactscr.html" title="struct stm32_metapac::eth::regs::Mactscr">Mactscr</a></div><div class="desc docblock-short">Timestamp control Register</div></li><li><div class="item-name"><a class="struct" href="struct.Mactseacr.html" title="struct stm32_metapac::eth::regs::Mactseacr">Mactseacr</a></div><div class="desc docblock-short">Timestamp Egress asymmetric correction register</div></li><li><div class="item-name"><a class="struct" href="struct.Mactsecnr.html" title="struct stm32_metapac::eth::regs::Mactsecnr">Mactsecnr</a></div><div class="desc docblock-short">Timestamp Egress correction nanosecond register</div></li><li><div class="item-name"><a class="struct" href="struct.Mactsiacr.html" title="struct stm32_metapac::eth::regs::Mactsiacr">Mactsiacr</a></div><div class="desc docblock-short">Timestamp Ingress asymmetric correction register</div></li><li><div class="item-name"><a class="struct" href="struct.Mactsicnr.html" title="struct stm32_metapac::eth::regs::Mactsicnr">Mactsicnr</a></div><div class="desc docblock-short">Timestamp Ingress correction nanosecond register</div></li><li><div class="item-name"><a class="struct" href="struct.Mactssr.html" title="struct stm32_metapac::eth::regs::Mactssr">Mactssr</a></div><div class="desc docblock-short">Timestamp status register</div></li><li><div class="item-name"><a class="struct" href="struct.MactxTssnr.html" title="struct stm32_metapac::eth::regs::MactxTssnr">Mactx<wbr>Tssnr</a></div><div class="desc docblock-short">Tx timestamp status nanoseconds register</div></li><li><div class="item-name"><a class="struct" href="struct.MactxTsssr.html" title="struct stm32_metapac::eth::regs::MactxTsssr">Mactx<wbr>Tsssr</a></div><div class="desc docblock-short">Tx timestamp status seconds register</div></li><li><div class="item-name"><a class="struct" href="struct.Macvhtr.html" title="struct stm32_metapac::eth::regs::Macvhtr">Macvhtr</a></div><div class="desc docblock-short">VLAN Hash table register</div></li><li><div class="item-name"><a class="struct" href="struct.Macvir.html" title="struct stm32_metapac::eth::regs::Macvir">Macvir</a></div><div class="desc docblock-short">VLAN inclusion register</div></li><li><div class="item-name"><a class="struct" href="struct.Macvr.html" title="struct stm32_metapac::eth::regs::Macvr">Macvr</a></div><div class="desc docblock-short">Version register</div></li><li><div class="item-name"><a class="struct" href="struct.Macvtr.html" title="struct stm32_metapac::eth::regs::Macvtr">Macvtr</a></div><div class="desc docblock-short">VLAN tag register</div></li><li><div class="item-name"><a class="struct" href="struct.Macwtr.html" title="struct stm32_metapac::eth::regs::Macwtr">Macwtr</a></div><div class="desc docblock-short">Watchdog timeout register</div></li><li><div class="item-name"><a class="struct" href="struct.MmcControl.html" title="struct stm32_metapac::eth::regs::MmcControl">MmcControl</a></div><div class="desc docblock-short">MMC control register</div></li><li><div class="item-name"><a class="struct" href="struct.MmcRxInterrupt.html" title="struct stm32_metapac::eth::regs::MmcRxInterrupt">MmcRx<wbr>Interrupt</a></div><div class="desc docblock-short">MMC Rx interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.MmcRxInterruptMask.html" title="struct stm32_metapac::eth::regs::MmcRxInterruptMask">MmcRx<wbr>Interrupt<wbr>Mask</a></div><div class="desc docblock-short">MMC Rx interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.MmcTxInterrupt.html" title="struct stm32_metapac::eth::regs::MmcTxInterrupt">MmcTx<wbr>Interrupt</a></div><div class="desc docblock-short">MMC Tx interrupt register</div></li><li><div class="item-name"><a class="struct" href="struct.MmcTxInterruptMask.html" title="struct stm32_metapac::eth::regs::MmcTxInterruptMask">MmcTx<wbr>Interrupt<wbr>Mask</a></div><div class="desc docblock-short">MMC Tx interrupt mask register</div></li><li><div class="item-name"><a class="struct" href="struct.Mtlisr.html" title="struct stm32_metapac::eth::regs::Mtlisr">Mtlisr</a></div><div class="desc docblock-short">Interrupt status Register</div></li><li><div class="item-name"><a class="struct" href="struct.Mtlomr.html" title="struct stm32_metapac::eth::regs::Mtlomr">Mtlomr</a></div><div class="desc docblock-short">Operating mode Register</div></li><li><div class="item-name"><a class="struct" href="struct.Mtlqicsr.html" title="struct stm32_metapac::eth::regs::Mtlqicsr">Mtlqicsr</a></div><div class="desc docblock-short">Queue interrupt control status Register</div></li><li><div class="item-name"><a class="struct" href="struct.MtlrxQdr.html" title="struct stm32_metapac::eth::regs::MtlrxQdr">Mtlrx<wbr>Qdr</a></div><div class="desc docblock-short">Rx queue debug register</div></li><li><div class="item-name"><a class="struct" href="struct.MtlrxQmpocr.html" title="struct stm32_metapac::eth::regs::MtlrxQmpocr">Mtlrx<wbr>Qmpocr</a></div><div class="desc docblock-short">Rx queue missed packet and overflow counter register</div></li><li><div class="item-name"><a class="struct" href="struct.MtlrxQomr.html" title="struct stm32_metapac::eth::regs::MtlrxQomr">Mtlrx<wbr>Qomr</a></div><div class="desc docblock-short">Rx queue operating mode register</div></li><li><div class="item-name"><a class="struct" href="struct.MtltxQdr.html" title="struct stm32_metapac::eth::regs::MtltxQdr">Mtltx<wbr>Qdr</a></div><div class="desc docblock-short">Tx queue debug Register</div></li><li><div class="item-name"><a class="struct" href="struct.MtltxQomr.html" title="struct stm32_metapac::eth::regs::MtltxQomr">Mtltx<wbr>Qomr</a></div><div class="desc docblock-short">Tx queue operating mode Register</div></li><li><div class="item-name"><a class="struct" href="struct.MtltxQur.html" title="struct stm32_metapac::eth::regs::MtltxQur">Mtltx<wbr>Qur</a></div><div class="desc docblock-short">Tx queue underflow register</div></li><li><div class="item-name"><a class="struct" href="struct.RxAlignmentErrorPackets.html" title="struct stm32_metapac::eth::regs::RxAlignmentErrorPackets">RxAlignment<wbr>Error<wbr>Packets</a></div><div class="desc docblock-short">Rx alignment error packets register</div></li><li><div class="item-name"><a class="struct" href="struct.RxCrcErrorPackets.html" title="struct stm32_metapac::eth::regs::RxCrcErrorPackets">RxCrc<wbr>Error<wbr>Packets</a></div><div class="desc docblock-short">Rx CRC error packets register</div></li><li><div class="item-name"><a class="struct" href="struct.RxLpiTranCntr.html" title="struct stm32_metapac::eth::regs::RxLpiTranCntr">RxLpi<wbr>Tran<wbr>Cntr</a></div><div class="desc docblock-short">Rx LPI transition counter register</div></li><li><div class="item-name"><a class="struct" href="struct.RxLpiUsecCntr.html" title="struct stm32_metapac::eth::regs::RxLpiUsecCntr">RxLpi<wbr>Usec<wbr>Cntr</a></div><div class="desc docblock-short">Rx LPI microsecond counter register</div></li><li><div class="item-name"><a class="struct" href="struct.RxUnicastPacketsGood.html" title="struct stm32_metapac::eth::regs::RxUnicastPacketsGood">RxUnicast<wbr>Packets<wbr>Good</a></div><div class="desc docblock-short">Rx unicast packets good register</div></li><li><div class="item-name"><a class="struct" href="struct.TxLpiTranCntr.html" title="struct stm32_metapac::eth::regs::TxLpiTranCntr">TxLpi<wbr>Tran<wbr>Cntr</a></div><div class="desc docblock-short">Tx LPI transition counter register</div></li><li><div class="item-name"><a class="struct" href="struct.TxLpiUsecCntr.html" title="struct stm32_metapac::eth::regs::TxLpiUsecCntr">TxLpi<wbr>Usec<wbr>Cntr</a></div><div class="desc docblock-short">Tx LPI microsecond timer register</div></li><li><div class="item-name"><a class="struct" href="struct.TxMultipleCollisionGoodPackets.html" title="struct stm32_metapac::eth::regs::TxMultipleCollisionGoodPackets">TxMultiple<wbr>Collision<wbr>Good<wbr>Packets</a></div><div class="desc docblock-short">Tx multiple collision good packets register</div></li><li><div class="item-name"><a class="struct" href="struct.TxPacketCountGood.html" title="struct stm32_metapac::eth::regs::TxPacketCountGood">TxPacket<wbr>Count<wbr>Good</a></div><div class="desc docblock-short">Tx packet count good register</div></li><li><div class="item-name"><a class="struct" href="struct.TxSingleCollisionGoodPackets.html" title="struct stm32_metapac::eth::regs::TxSingleCollisionGoodPackets">TxSingle<wbr>Collision<wbr>Good<wbr>Packets</a></div><div class="desc docblock-short">Tx single collision good packets register</div></li></ul></section></div></main></body></html>
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