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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Interrupt Enable Register"><title>imxrt_ral::usb::USBINTR - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="imxrt_ral" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../imxrt_ral/index.html">imxrt_<wbr>ral</a><span class="version">0.5.3</span></h2></div><h2 class="location"><a href="#">Module USBINTR</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#modules">Modules</a></li></ul></section><h2><a href="../index.html">In imxrt_<wbr>ral::<wbr>usb</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../../index.html">imxrt_ral</a>::<wbr><a href="../index.html">usb</a>::<wbr><a class="mod" href="#">USBINTR</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../../src/imxrt_ral/blocks/imxrt1011/usb.rs.html#847">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>−</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>Interrupt Enable Register</p>
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</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="AAE/index.html" title="mod imxrt_ral::usb::USBINTR::AAE">AAE</a></div><div class="desc docblock-short">Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="FRE/index.html" title="mod imxrt_ral::usb::USBINTR::FRE">FRE</a></div><div class="desc docblock-short">Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="NAKE/index.html" title="mod imxrt_ral::usb::USBINTR::NAKE">NAKE</a></div><div class="desc docblock-short">NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="PCE/index.html" title="mod imxrt_ral::usb::USBINTR::PCE">PCE</a></div><div class="desc docblock-short">Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="SEE/index.html" title="mod imxrt_ral::usb::USBINTR::SEE">SEE</a></div><div class="desc docblock-short">System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="SLE/index.html" title="mod imxrt_ral::usb::USBINTR::SLE">SLE</a></div><div class="desc docblock-short">Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="SRE/index.html" title="mod imxrt_ral::usb::USBINTR::SRE">SRE</a></div><div class="desc docblock-short">SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="TIE0/index.html" title="mod imxrt_ral::usb::USBINTR::TIE0">TIE0</a></div><div class="desc docblock-short">General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="TIE1/index.html" title="mod imxrt_ral::usb::USBINTR::TIE1">TIE1</a></div><div class="desc docblock-short">General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="UAIE/index.html" title="mod imxrt_ral::usb::USBINTR::UAIE">UAIE</a></div><div class="desc docblock-short">USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold</div></li><li><div class="item-name"><a class="mod" href="UE/index.html" title="mod imxrt_ral::usb::USBINTR::UE">UE</a></div><div class="desc docblock-short">USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="UEE/index.html" title="mod imxrt_ral::usb::USBINTR::UEE">UEE</a></div><div class="desc docblock-short">USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="ULPIE/index.html" title="mod imxrt_ral::usb::USBINTR::ULPIE">ULPIE</a></div><div class="desc docblock-short">ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt</div></li><li><div class="item-name"><a class="mod" href="UPIE/index.html" title="mod imxrt_ral::usb::USBINTR::UPIE">UPIE</a></div><div class="desc docblock-short">USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold</div></li><li><div class="item-name"><a class="mod" href="URE/index.html" title="mod imxrt_ral::usb::USBINTR::URE">URE</a></div><div class="desc docblock-short">USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt</div></li></ul></section></div></main></body></html> |