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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="I2C Enable Register"><title>rp2040_pac::i2c0::ic_enable - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../../" data-static-root-path="../../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module ic_<wbr>enable</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#structs">Structs</a></li><li><a href="#enums">Enums</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In rp2040_<wbr>pac::<wbr>i2c0</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../../index.html">rp2040_pac</a>::<wbr><a href="../index.html">i2c0</a>::<wbr><a class="mod" href="#">ic_enable</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../../src/rp2040_pac/i2c0/ic_enable.rs.html#1-289">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>I2C Enable Register</p>
</div></details><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.IC_ENABLE_SPEC.html" title="struct rp2040_pac::i2c0::ic_enable::IC_ENABLE_SPEC">IC_<wbr>ENABL<wbr>E_<wbr>SPEC</a></div><div class="desc docblock-short">I2C Enable Register</div></li></ul><h2 id="enums" class="section-header">Enums<a href="#enums" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="enum" href="enum.ABORT_A.html" title="enum rp2040_pac::i2c0::ic_enable::ABORT_A">ABORT_A</a></div><div class="desc docblock-short">When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.</div></li><li><div class="item-name"><a class="enum" href="enum.ENABLE_A.html" title="enum rp2040_pac::i2c0::ic_enable::ENABLE_A">ENABL<wbr>E_<wbr>A</a></div><div class="desc docblock-short">Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in ‘Disabling DW_apb_i2c’.</div></li><li><div class="item-name"><a class="enum" href="enum.TX_CMD_BLOCK_A.html" title="enum rp2040_pac::i2c0::ic_enable::TX_CMD_BLOCK_A">TX_<wbr>CMD_<wbr>BLOC<wbr>K_<wbr>A</a></div><div class="desc docblock-short">In Master mode: - 1’b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1’b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5]
== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.ABORT_R.html" title="type rp2040_pac::i2c0::ic_enable::ABORT_R">ABORT_R</a></div><div class="desc docblock-short">Field <code>ABORT</code> reader - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.</div></li><li><div class="item-name"><a class="type" href="type.ABORT_W.html" title="type rp2040_pac::i2c0::ic_enable::ABORT_W">ABORT_W</a></div><div class="desc docblock-short">Field <code>ABORT</code> writer - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.</div></li><li><div class="item-name"><a class="type" href="type.ENABLE_R.html" title="type rp2040_pac::i2c0::ic_enable::ENABLE_R">ENABL<wbr>E_<wbr>R</a></div><div class="desc docblock-short">Field <code>ENABLE</code> reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in ‘Disabling DW_apb_i2c’.</div></li><li><div class="item-name"><a class="type" href="type.ENABLE_W.html" title="type rp2040_pac::i2c0::ic_enable::ENABLE_W">ENABL<wbr>E_<wbr>W</a></div><div class="desc docblock-short">Field <code>ENABLE</code> writer - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in ‘Disabling DW_apb_i2c’.</div></li><li><div class="item-name"><a class="type" href="type.R.html" title="type rp2040_pac::i2c0::ic_enable::R">R</a></div><div class="desc docblock-short">Register <code>IC_ENABLE</code> reader</div></li><li><div class="item-name"><a class="type" href="type.TX_CMD_BLOCK_R.html" title="type rp2040_pac::i2c0::ic_enable::TX_CMD_BLOCK_R">TX_<wbr>CMD_<wbr>BLOC<wbr>K_<wbr>R</a></div><div class="desc docblock-short">Field <code>TX_CMD_BLOCK</code> reader - In Master mode: - 1’b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1’b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5]
== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT</div></li><li><div class="item-name"><a class="type" href="type.TX_CMD_BLOCK_W.html" title="type rp2040_pac::i2c0::ic_enable::TX_CMD_BLOCK_W">TX_<wbr>CMD_<wbr>BLOC<wbr>K_<wbr>W</a></div><div class="desc docblock-short">Field <code>TX_CMD_BLOCK</code> writer - In Master mode: - 1’b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1’b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5]
== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT</div></li><li><div class="item-name"><a class="type" href="type.W.html" title="type rp2040_pac::i2c0::ic_enable::W">W</a></div><div class="desc docblock-short">Register <code>IC_ENABLE</code> writer</div></li></ul></section></div></main></body></html>
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