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<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="DW_apb_ssi has the following features:"><title>rp2040_pac::xip_ssi - Rust</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-492a78a4a87dcc01.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="rp2040_pac" data-themes="" data-resource-suffix="" data-rustdoc-version="1.82.0 (f6e511eec 2024-10-15)" data-channel="1.82.0" data-search-js="search-a99f1315e7cc5121.js" data-settings-js="settings-4313503d2e1961c2.js" ><script src="../../static.files/storage-118b08c4c78b968e.js"></script><script defer src="../sidebar-items.js"></script><script defer src="../../static.files/main-921df33f47b8780c.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-3b12f09e550e0385.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc mod"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="mobile-topbar"><button class="sidebar-menu-toggle" title="show sidebar"></button></nav><nav class="sidebar"><div class="sidebar-crate"><h2><a href="../../rp2040_pac/index.html">rp2040_<wbr>pac</a><span class="version">0.6.0</span></h2></div><h2 class="location"><a href="#">Module xip_ssi</a></h2><div class="sidebar-elems"><section><ul class="block"><li><a href="#modules">Modules</a></li><li><a href="#structs">Structs</a></li><li><a href="#types">Type Aliases</a></li></ul></section><h2><a href="../index.html">In crate rp2040_<wbr>pac</a></h2></div></nav><div class="sidebar-resizer"></div><main><div class="width-limiter"><rustdoc-search></rustdoc-search><section id="main-content" class="content"><div class="main-heading"><h1>Module <a href="../index.html">rp2040_pac</a>::<wbr><a class="mod" href="#">xip_ssi</a><button id="copy-path" title="Copy item path to clipboard">Copy item path</button></h1><span class="out-of-band"><a class="src" href="../../src/rp2040_pac/xip_ssi.rs.html#1-427">source</a> · <button id="toggle-all-docs" title="collapse all docs">[<span>&#x2212;</span>]</button></span></div><details class="toggle top-doc" open><summary class="hideme"><span>Expand description</span></summary><div class="docblock"><p>DW_apb_ssi has the following features:</p>
<ul>
<li>APB interface - Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.</li>
<li>APB3 and APB4 protocol support.</li>
<li>Scalable APB data bus width - Supports APB data bus widths of 8, 16, and 32 bits.</li>
<li>Serial-master or serial-slave operation - Enables serial communication with serial-master or serial-slave peripheral devices.</li>
<li>Programmable Dual/Quad/Octal SPI support in Master Mode.</li>
<li>Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.</li>
<li>Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.</li>
<li>eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.</li>
<li>DMA Controller Interface - Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.</li>
<li>Independent masking of interrupts - Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.</li>
<li>Multi-master contention detection - Informs the processor of multiple serial-master accesses on the serial bus.</li>
<li>Bypass of meta-stability flip-flops for synchronous clocks - When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.</li>
<li>Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.</li>
<li>Programmable features:</li>
</ul>
<ul>
<li>Serial interface operation - Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.</li>
<li>Clock bit-rate - Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.</li>
<li>Data Item size (4 to 32 bits) - Item size of each data transfer under the control of the programmer.</li>
</ul>
<ul>
<li>Configured features:</li>
</ul>
<ul>
<li>FIFO depth - 16 words deep. The FIFO width is fixed at 32 bits.</li>
<li>1 slave select output.</li>
<li>Hardware slave-select - Dedicated hardware slave-select line.</li>
<li>Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.</li>
<li>Interrupt polarity - active high interrupt lines.</li>
<li>Serial clock polarity - low serial-clock polarity directly after reset.</li>
<li>Serial clock phase - capture on first edge of serial-clock directly after reset.</li>
</ul>
</div></details><h2 id="modules" class="section-header">Modules<a href="#modules" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="mod" href="baudr/index.html" title="mod rp2040_pac::xip_ssi::baudr">baudr</a></div><div class="desc docblock-short">Baud rate</div></li><li><div class="item-name"><a class="mod" href="ctrlr0/index.html" title="mod rp2040_pac::xip_ssi::ctrlr0">ctrlr0</a></div><div class="desc docblock-short">Control register 0</div></li><li><div class="item-name"><a class="mod" href="ctrlr1/index.html" title="mod rp2040_pac::xip_ssi::ctrlr1">ctrlr1</a></div><div class="desc docblock-short">Master Control register 1</div></li><li><div class="item-name"><a class="mod" href="dmacr/index.html" title="mod rp2040_pac::xip_ssi::dmacr">dmacr</a></div><div class="desc docblock-short">DMA control</div></li><li><div class="item-name"><a class="mod" href="dmardlr/index.html" title="mod rp2040_pac::xip_ssi::dmardlr">dmardlr</a></div><div class="desc docblock-short">DMA RX data level</div></li><li><div class="item-name"><a class="mod" href="dmatdlr/index.html" title="mod rp2040_pac::xip_ssi::dmatdlr">dmatdlr</a></div><div class="desc docblock-short">DMA TX data level</div></li><li><div class="item-name"><a class="mod" href="dr0/index.html" title="mod rp2040_pac::xip_ssi::dr0">dr0</a></div><div class="desc docblock-short">Data Register 0 (of 36)</div></li><li><div class="item-name"><a class="mod" href="icr/index.html" title="mod rp2040_pac::xip_ssi::icr">icr</a></div><div class="desc docblock-short">Interrupt clear</div></li><li><div class="item-name"><a class="mod" href="idr/index.html" title="mod rp2040_pac::xip_ssi::idr">idr</a></div><div class="desc docblock-short">Identification register</div></li><li><div class="item-name"><a class="mod" href="imr/index.html" title="mod rp2040_pac::xip_ssi::imr">imr</a></div><div class="desc docblock-short">Interrupt mask</div></li><li><div class="item-name"><a class="mod" href="isr/index.html" title="mod rp2040_pac::xip_ssi::isr">isr</a></div><div class="desc docblock-short">Interrupt status</div></li><li><div class="item-name"><a class="mod" href="msticr/index.html" title="mod rp2040_pac::xip_ssi::msticr">msticr</a></div><div class="desc docblock-short">Multi-master interrupt clear</div></li><li><div class="item-name"><a class="mod" href="mwcr/index.html" title="mod rp2040_pac::xip_ssi::mwcr">mwcr</a></div><div class="desc docblock-short">Microwire Control</div></li><li><div class="item-name"><a class="mod" href="risr/index.html" title="mod rp2040_pac::xip_ssi::risr">risr</a></div><div class="desc docblock-short">Raw interrupt status</div></li><li><div class="item-name"><a class="mod" href="rx_sample_dly/index.html" title="mod rp2040_pac::xip_ssi::rx_sample_dly">rx_<wbr>sample_<wbr>dly</a></div><div class="desc docblock-short">RX sample delay</div></li><li><div class="item-name"><a class="mod" href="rxflr/index.html" title="mod rp2040_pac::xip_ssi::rxflr">rxflr</a></div><div class="desc docblock-short">RX FIFO level</div></li><li><div class="item-name"><a class="mod" href="rxftlr/index.html" title="mod rp2040_pac::xip_ssi::rxftlr">rxftlr</a></div><div class="desc docblock-short">RX FIFO threshold level</div></li><li><div class="item-name"><a class="mod" href="rxoicr/index.html" title="mod rp2040_pac::xip_ssi::rxoicr">rxoicr</a></div><div class="desc docblock-short">RX FIFO overflow interrupt clear</div></li><li><div class="item-name"><a class="mod" href="rxuicr/index.html" title="mod rp2040_pac::xip_ssi::rxuicr">rxuicr</a></div><div class="desc docblock-short">RX FIFO underflow interrupt clear</div></li><li><div class="item-name"><a class="mod" href="ser/index.html" title="mod rp2040_pac::xip_ssi::ser">ser</a></div><div class="desc docblock-short">Slave enable</div></li><li><div class="item-name"><a class="mod" href="spi_ctrlr0/index.html" title="mod rp2040_pac::xip_ssi::spi_ctrlr0">spi_<wbr>ctrlr0</a></div><div class="desc docblock-short">SPI control</div></li><li><div class="item-name"><a class="mod" href="sr/index.html" title="mod rp2040_pac::xip_ssi::sr">sr</a></div><div class="desc docblock-short">Status register</div></li><li><div class="item-name"><a class="mod" href="ssi_version_id/index.html" title="mod rp2040_pac::xip_ssi::ssi_version_id">ssi_<wbr>version_<wbr>id</a></div><div class="desc docblock-short">Version ID</div></li><li><div class="item-name"><a class="mod" href="ssienr/index.html" title="mod rp2040_pac::xip_ssi::ssienr">ssienr</a></div><div class="desc docblock-short">SSI Enable</div></li><li><div class="item-name"><a class="mod" href="txd_drive_edge/index.html" title="mod rp2040_pac::xip_ssi::txd_drive_edge">txd_<wbr>drive_<wbr>edge</a></div><div class="desc docblock-short">TX drive edge</div></li><li><div class="item-name"><a class="mod" href="txflr/index.html" title="mod rp2040_pac::xip_ssi::txflr">txflr</a></div><div class="desc docblock-short">TX FIFO level</div></li><li><div class="item-name"><a class="mod" href="txftlr/index.html" title="mod rp2040_pac::xip_ssi::txftlr">txftlr</a></div><div class="desc docblock-short">TX FIFO threshold level</div></li><li><div class="item-name"><a class="mod" href="txoicr/index.html" title="mod rp2040_pac::xip_ssi::txoicr">txoicr</a></div><div class="desc docblock-short">TX FIFO overflow interrupt clear</div></li></ul><h2 id="structs" class="section-header">Structs<a href="#structs" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="struct" href="struct.RegisterBlock.html" title="struct rp2040_pac::xip_ssi::RegisterBlock">Register<wbr>Block</a></div><div class="desc docblock-short">Register block</div></li></ul><h2 id="types" class="section-header">Type Aliases<a href="#types" class="anchor">§</a></h2><ul class="item-table"><li><div class="item-name"><a class="type" href="type.BAUDR.html" title="type rp2040_pac::xip_ssi::BAUDR">BAUDR</a></div><div class="desc docblock-short">BAUDR (rw) register accessor: Baud rate</div></li><li><div class="item-name"><a class="type" href="type.CTRLR0.html" title="type rp2040_pac::xip_ssi::CTRLR0">CTRLR0</a></div><div class="desc docblock-short">CTRLR0 (rw) register accessor: Control register 0</div></li><li><div class="item-name"><a class="type" href="type.CTRLR1.html" title="type rp2040_pac::xip_ssi::CTRLR1">CTRLR1</a></div><div class="desc docblock-short">CTRLR1 (rw) register accessor: Master Control register 1</div></li><li><div class="item-name"><a class="type" href="type.DMACR.html" title="type rp2040_pac::xip_ssi::DMACR">DMACR</a></div><div class="desc docblock-short">DMACR (rw) register accessor: DMA control</div></li><li><div class="item-name"><a class="type" href="type.DMARDLR.html" title="type rp2040_pac::xip_ssi::DMARDLR">DMARDLR</a></div><div class="desc docblock-short">DMARDLR (rw) register accessor: DMA RX data level</div></li><li><div class="item-name"><a class="type" href="type.DMATDLR.html" title="type rp2040_pac::xip_ssi::DMATDLR">DMATDLR</a></div><div class="desc docblock-short">DMATDLR (rw) register accessor: DMA TX data level</div></li><li><div class="item-name"><a class="type" href="type.DR0.html" title="type rp2040_pac::xip_ssi::DR0">DR0</a></div><div class="desc docblock-short">DR0 (rw) register accessor: Data Register 0 (of 36)</div></li><li><div class="item-name"><a class="type" href="type.ICR.html" title="type rp2040_pac::xip_ssi::ICR">ICR</a></div><div class="desc docblock-short">ICR (r) register accessor: Interrupt clear</div></li><li><div class="item-name"><a class="type" href="type.IDR.html" title="type rp2040_pac::xip_ssi::IDR">IDR</a></div><div class="desc docblock-short">IDR (r) register accessor: Identification register</div></li><li><div class="item-name"><a class="type" href="type.IMR.html" title="type rp2040_pac::xip_ssi::IMR">IMR</a></div><div class="desc docblock-short">IMR (rw) register accessor: Interrupt mask</div></li><li><div class="item-name"><a class="type" href="type.ISR.html" title="type rp2040_pac::xip_ssi::ISR">ISR</a></div><div class="desc docblock-short">ISR (r) register accessor: Interrupt status</div></li><li><div class="item-name"><a class="type" href="type.MSTICR.html" title="type rp2040_pac::xip_ssi::MSTICR">MSTICR</a></div><div class="desc docblock-short">MSTICR (r) register accessor: Multi-master interrupt clear</div></li><li><div class="item-name"><a class="type" href="type.MWCR.html" title="type rp2040_pac::xip_ssi::MWCR">MWCR</a></div><div class="desc docblock-short">MWCR (rw) register accessor: Microwire Control</div></li><li><div class="item-name"><a class="type" href="type.RISR.html" title="type rp2040_pac::xip_ssi::RISR">RISR</a></div><div class="desc docblock-short">RISR (r) register accessor: Raw interrupt status</div></li><li><div class="item-name"><a class="type" href="type.RXFLR.html" title="type rp2040_pac::xip_ssi::RXFLR">RXFLR</a></div><div class="desc docblock-short">RXFLR (r) register accessor: RX FIFO level</div></li><li><div class="item-name"><a class="type" href="type.RXFTLR.html" title="type rp2040_pac::xip_ssi::RXFTLR">RXFTLR</a></div><div class="desc docblock-short">RXFTLR (rw) register accessor: RX FIFO threshold level</div></li><li><div class="item-name"><a class="type" href="type.RXOICR.html" title="type rp2040_pac::xip_ssi::RXOICR">RXOICR</a></div><div class="desc docblock-short">RXOICR (r) register accessor: RX FIFO overflow interrupt clear</div></li><li><div class="item-name"><a class="type" href="type.RXUICR.html" title="type rp2040_pac::xip_ssi::RXUICR">RXUICR</a></div><div class="desc docblock-short">RXUICR (r) register accessor: RX FIFO underflow interrupt clear</div></li><li><div class="item-name"><a class="type" href="type.RX_SAMPLE_DLY.html" title="type rp2040_pac::xip_ssi::RX_SAMPLE_DLY">RX_<wbr>SAMPL<wbr>E_<wbr>DLY</a></div><div class="desc docblock-short">RX_SAMPLE_DLY (rw) register accessor: RX sample delay</div></li><li><div class="item-name"><a class="type" href="type.SER.html" title="type rp2040_pac::xip_ssi::SER">SER</a></div><div class="desc docblock-short">SER (rw) register accessor: Slave enable</div></li><li><div class="item-name"><a class="type" href="type.SPI_CTRLR0.html" title="type rp2040_pac::xip_ssi::SPI_CTRLR0">SPI_<wbr>CTRL<wbr>R0</a></div><div class="desc docblock-short">SPI_CTRLR0 (rw) register accessor: SPI control</div></li><li><div class="item-name"><a class="type" href="type.SR.html" title="type rp2040_pac::xip_ssi::SR">SR</a></div><div class="desc docblock-short">SR (r) register accessor: Status register</div></li><li><div class="item-name"><a class="type" href="type.SSIENR.html" title="type rp2040_pac::xip_ssi::SSIENR">SSIENR</a></div><div class="desc docblock-short">SSIENR (rw) register accessor: SSI Enable</div></li><li><div class="item-name"><a class="type" href="type.SSI_VERSION_ID.html" title="type rp2040_pac::xip_ssi::SSI_VERSION_ID">SSI_<wbr>VERSIO<wbr>N_<wbr>ID</a></div><div class="desc docblock-short">SSI_VERSION_ID (r) register accessor: Version ID</div></li><li><div class="item-name"><a class="type" href="type.TXD_DRIVE_EDGE.html" title="type rp2040_pac::xip_ssi::TXD_DRIVE_EDGE">TXD_<wbr>DRIV<wbr>E_<wbr>EDGE</a></div><div class="desc docblock-short">TXD_DRIVE_EDGE (rw) register accessor: TX drive edge</div></li><li><div class="item-name"><a class="type" href="type.TXFLR.html" title="type rp2040_pac::xip_ssi::TXFLR">TXFLR</a></div><div class="desc docblock-short">TXFLR (r) register accessor: TX FIFO level</div></li><li><div class="item-name"><a class="type" href="type.TXFTLR.html" title="type rp2040_pac::xip_ssi::TXFTLR">TXFTLR</a></div><div class="desc docblock-short">TXFTLR (rw) register accessor: TX FIFO threshold level</div></li><li><div class="item-name"><a class="type" href="type.TXOICR.html" title="type rp2040_pac::xip_ssi::TXOICR">TXOICR</a></div><div class="desc docblock-short">TXOICR (r) register accessor: TX FIFO overflow interrupt clear</div></li></ul></section></div></main></body></html>
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