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Use cortex-m InterruptNumber iso bare_metal Nr

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This commit is contained in:
Jorgeig 2021-08-10 17:51:10 +08:00
parent 356f53ddc3
commit 9bcb32329f
6 changed files with 16 additions and 16 deletions
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4
Cargo.toml
View file

@ -13,7 +13,7 @@ license = "MIT OR Apache-2.0"
name = "cortex-m-rtic" name = "cortex-m-rtic"
readme = "README.md" readme = "README.md"
repository = "https://github.com/rtic-rs/cortex-m-rtic" repository = "https://github.com/rtic-rs/cortex-m-rtic"
version = "0.5.7" version = "0.5.8"
[lib] [lib]
name = "rtic" name = "rtic"
@ -51,7 +51,7 @@ name = "types"
required-features = ["__v7"] required-features = ["__v7"]
[dependencies] [dependencies]
cortex-m = "0.6.2" cortex-m = "0.7.3"
cortex-m-rtic-macros = { path = "macros", version = "0.5.3" } cortex-m-rtic-macros = { path = "macros", version = "0.5.3" }
rtic-core = "0.3.0" rtic-core = "0.3.0"
cortex-m-rt = "0.6.9" cortex-m-rt = "0.6.9"

2
heterogeneous/Cargo.toml
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@ -7,7 +7,7 @@ publish = false
version = "0.0.0-alpha.0" version = "0.0.0-alpha.0"
[dependencies] [dependencies]
bare-metal = "0.2.4" cortex-m = "0.7.3"
[dependencies.cortex-m-rtic] [dependencies.cortex-m-rtic]
path = ".." path = ".."

10
heterogeneous/src/lib.rs
View file

@ -7,7 +7,7 @@ use core::{
ops::{Add, Sub}, ops::{Add, Sub},
}; };
use bare_metal::Nr; use cortex_m::interrupt::InterruptNumber;
use rtic::{Fraction, Monotonic, MultiCore}; use rtic::{Fraction, Monotonic, MultiCore};
// both cores have the exact same interrupts // both cores have the exact same interrupts
@ -16,7 +16,7 @@ pub use Interrupt_0 as Interrupt_1;
// Fake priority bits // Fake priority bits
pub const NVIC_PRIO_BITS: u8 = 3; pub const NVIC_PRIO_BITS: u8 = 3;
pub fn xpend(_core: u8, _interrupt: impl Nr) {} pub fn xpend(_core: u8, _interrupt: impl InterruptNumber) {}
/// Fake monotonic timer /// Fake monotonic timer
pub struct MT; pub struct MT;
@ -92,8 +92,8 @@ pub enum Interrupt_0 {
I7 = 7, I7 = 7,
} }
unsafe impl Nr for Interrupt_0 { unsafe impl InterruptNumber for Interrupt_0 {
fn nr(&self) -> u8 { fn number(self) -> u16 {
*self as u8 self as u16
} }
} }

2
homogeneous/Cargo.toml
View file

@ -7,7 +7,7 @@ publish = false
version = "0.0.0-alpha.0" version = "0.0.0-alpha.0"
[dependencies] [dependencies]
bare-metal = "0.2.4" cortex-m = "0.7.3"
[dependencies.cortex-m-rtic] [dependencies.cortex-m-rtic]
path = ".." path = ".."

10
homogeneous/src/lib.rs
View file

@ -7,7 +7,7 @@ use core::{
ops::{Add, Sub}, ops::{Add, Sub},
}; };
use bare_metal::Nr; use cortex_m::interrupt::InterruptNumber;
use rtic::{Fraction, Monotonic, MultiCore}; use rtic::{Fraction, Monotonic, MultiCore};
// both cores have the exact same interrupts // both cores have the exact same interrupts
@ -16,7 +16,7 @@ pub use Interrupt_0 as Interrupt_1;
// Fake priority bits // Fake priority bits
pub const NVIC_PRIO_BITS: u8 = 3; pub const NVIC_PRIO_BITS: u8 = 3;
pub fn xpend(_core: u8, _interrupt: impl Nr) {} pub fn xpend(_core: u8, _interrupt: impl InterruptNumber) {}
/// Fake monotonic timer /// Fake monotonic timer
pub struct MT; pub struct MT;
@ -92,8 +92,8 @@ pub enum Interrupt_0 {
I7 = 7, I7 = 7,
} }
unsafe impl Nr for Interrupt_0 { unsafe impl InterruptNumber for Interrupt_0 {
fn nr(&self) -> u8 { fn number(self) -> u16 {
*self as u8 self as u16
} }
} }

4
src/lib.rs
View file

@ -45,7 +45,7 @@
use core::ops::Sub; use core::ops::Sub;
use cortex_m::{ use cortex_m::{
interrupt::Nr, interrupt::InterruptNumber,
peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, TPIU}, peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, TPIU},
}; };
#[cfg(all(not(feature = "heterogeneous"), not(feature = "homogeneous")))] #[cfg(all(not(feature = "heterogeneous"), not(feature = "homogeneous")))]
@ -170,7 +170,7 @@ pub trait MultiCore {}
/// [`NVIC::pend`](../cortex_m/peripheral/struct.NVIC.html#method.pend) /// [`NVIC::pend`](../cortex_m/peripheral/struct.NVIC.html#method.pend)
pub fn pend<I>(interrupt: I) pub fn pend<I>(interrupt: I)
where where
I: Nr, I: InterruptNumber,
{ {
NVIC::pend(interrupt) NVIC::pend(interrupt)
} }