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68 lines
4.4 KiB
Markdown
68 lines
4.4 KiB
Markdown
# Target Architecture
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While RTIC can currently target all Cortex-m devices there are some key architecture differences that
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users should be aware of. Namely, the absence of Base Priority Mask Register (`BASEPRI`) which lends
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itself exceptionally well to the hardware priority ceiling support used in RTIC, in the ARMv6-M and
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ARMv8-M-base architectures, which forces RTIC to use source masking instead. For each implementation
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of lock and a detailed commentary of pros and cons, see the implementation of
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[lock in src/export.rs][src_export].
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[src_export]: https://github.com/rtic-rs/rtic/blob/master/src/export.rs
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These differences influence how critical sections are realized, but functionality should be the same
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except that ARMv6-M/ARMv8-M-base cannot have tasks with shared resources bound to exception
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handlers, as these cannot be masked in hardware.
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Table 1 below shows a list of Cortex-m processors and which type of critical section they employ.
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#### *Table 1: Critical Section Implementation by Processor Architecture*
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| Processor | Architecture | Priority Ceiling | Source Masking |
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| :--------- | :----------: | :--------------: | :------------: |
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| Cortex-M0 | ARMv6-M | | ✓ |
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| Cortex-M0+ | ARMv6-M | | ✓ |
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| Cortex-M3 | ARMv7-M | ✓ | |
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| Cortex-M4 | ARMv7-M | ✓ | |
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| Cortex-M7 | ARMv7-M | ✓ | |
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| Cortex-M23 | ARMv8-M-base | | ✓ |
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| Cortex-M33 | ARMv8-M-main | ✓ | |
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## Priority Ceiling
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This is covered by the [Resources][resources] page of this book.
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## Source Masking
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Without a `BASEPRI` register which allows for directly setting a priority ceiling in the Nested
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Vectored Interrupt Controller (NVIC), RTIC must instead rely on disabling (masking) interrupts.
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Consider Figure 1 below, showing two tasks A and B where A has higher priority but shares a resource
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with B.
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#### *Figure 1: Shared Resources and Source Masking*
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```text
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┌────────────────────────────────────────────────────────────────┐
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│ │
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│ │
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3 │ Pending Preempts │
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2 │ ↑- - -A- - - - -↓A─────────► │
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1 │ B───────────────────► - - - - B────────► │
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0 │Idle┌─────► Resumes ┌────────► │
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├────┴────────────────────────────────────────────┴──────────────┤
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│ │
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└────────────────────────────────────────────────────────────────┴──► Time
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t1 t2 t3 t4
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```
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At time *t1*, task B locks the shared resource by selectively disabling (using the NVIC) all other
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tasks which have a priority equal to or less than any task which shares resources with B. In effect
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this creates a virtual priority ceiling, mirroring the `BASEPRI` approach. Task A is one such task that shares resources with
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task B. At time *t2*, task A is either spawned by task B or becomes pending through an interrupt
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condition, but does not yet preempt task B even though its priority is greater. This is because the
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NVIC is preventing it from starting due to task A being disabled. At time *t3*, task B
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releases the lock by re-enabling the tasks in the NVIC. Because task A was pending and has a higher
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priority than task B, it immediately preempts task B and is free to use the shared resource without
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risk of data race conditions. At time *t4*, task A completes and returns the execution context to B.
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Since source masking relies on use of the NVIC, core exception sources such as HardFault, SVCall,
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PendSV, and SysTick cannot share data with other tasks.
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